1 /* 2 * arch/powerpc/kernel/pci_auto.c 3 * 4 * PCI autoconfiguration library 5 * 6 * Author: Matt Porter <mporter@mvista.com> 7 * 8 * Copyright 2000 MontaVista Software Inc. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <errno.h> 15 #include <pci.h> 16 17 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ 18 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE 19 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 20 #endif 21 22 /* 23 * 24 */ 25 26 void pciauto_region_init(struct pci_region *res) 27 { 28 /* 29 * Avoid allocating PCI resources from address 0 -- this is illegal 30 * according to PCI 2.1 and moreover, this is known to cause Linux IDE 31 * drivers to fail. Use a reasonable starting value of 0x1000 instead. 32 */ 33 res->bus_lower = res->bus_start ? res->bus_start : 0x1000; 34 } 35 36 void pciauto_region_align(struct pci_region *res, pci_size_t size) 37 { 38 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1; 39 } 40 41 int pciauto_region_allocate(struct pci_region *res, pci_size_t size, 42 pci_addr_t *bar) 43 { 44 pci_addr_t addr; 45 46 if (!res) { 47 debug("No resource"); 48 goto error; 49 } 50 51 addr = ((res->bus_lower - 1) | (size - 1)) + 1; 52 53 if (addr - res->bus_start + size > res->size) { 54 debug("No room in resource"); 55 goto error; 56 } 57 58 res->bus_lower = addr + size; 59 60 debug("address=0x%llx bus_lower=0x%llx", (unsigned long long)addr, 61 (unsigned long long)res->bus_lower); 62 63 *bar = addr; 64 return 0; 65 66 error: 67 *bar = (pci_addr_t)-1; 68 return -1; 69 } 70 71 /* 72 * 73 */ 74 75 void pciauto_setup_device(struct pci_controller *hose, 76 pci_dev_t dev, int bars_num, 77 struct pci_region *mem, 78 struct pci_region *prefetch, 79 struct pci_region *io) 80 { 81 u32 bar_response; 82 pci_size_t bar_size; 83 u16 cmdstat = 0; 84 int bar, bar_nr = 0; 85 #ifndef CONFIG_PCI_ENUM_ONLY 86 u8 header_type; 87 int rom_addr; 88 pci_addr_t bar_value; 89 struct pci_region *bar_res; 90 int found_mem64 = 0; 91 #endif 92 93 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); 94 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; 95 96 for (bar = PCI_BASE_ADDRESS_0; 97 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { 98 /* Tickle the BAR and get the response */ 99 #ifndef CONFIG_PCI_ENUM_ONLY 100 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); 101 #endif 102 pci_hose_read_config_dword(hose, dev, bar, &bar_response); 103 104 /* If BAR is not implemented go to the next BAR */ 105 if (!bar_response) 106 continue; 107 108 #ifndef CONFIG_PCI_ENUM_ONLY 109 found_mem64 = 0; 110 #endif 111 112 /* Check the BAR type and set our address mask */ 113 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 114 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) 115 & 0xffff) + 1; 116 #ifndef CONFIG_PCI_ENUM_ONLY 117 bar_res = io; 118 #endif 119 120 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", 121 bar_nr, (unsigned long long)bar_size); 122 } else { 123 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 124 PCI_BASE_ADDRESS_MEM_TYPE_64) { 125 u32 bar_response_upper; 126 u64 bar64; 127 128 #ifndef CONFIG_PCI_ENUM_ONLY 129 pci_hose_write_config_dword(hose, dev, bar + 4, 130 0xffffffff); 131 #endif 132 pci_hose_read_config_dword(hose, dev, bar + 4, 133 &bar_response_upper); 134 135 bar64 = ((u64)bar_response_upper << 32) | bar_response; 136 137 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; 138 #ifndef CONFIG_PCI_ENUM_ONLY 139 found_mem64 = 1; 140 #endif 141 } else { 142 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); 143 } 144 #ifndef CONFIG_PCI_ENUM_ONLY 145 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH)) 146 bar_res = prefetch; 147 else 148 bar_res = mem; 149 #endif 150 151 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ", 152 bar_nr, bar_res == prefetch ? "Prf" : "Mem", 153 (unsigned long long)bar_size); 154 } 155 156 #ifndef CONFIG_PCI_ENUM_ONLY 157 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) { 158 /* Write it out and update our limit */ 159 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value); 160 161 if (found_mem64) { 162 bar += 4; 163 #ifdef CONFIG_SYS_PCI_64BIT 164 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32)); 165 #else 166 /* 167 * If we are a 64-bit decoder then increment to the 168 * upper 32 bits of the bar and force it to locate 169 * in the lower 4GB of memory. 170 */ 171 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); 172 #endif 173 } 174 175 } 176 #endif 177 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? 178 PCI_COMMAND_IO : PCI_COMMAND_MEMORY; 179 180 debug("\n"); 181 182 bar_nr++; 183 } 184 185 #ifndef CONFIG_PCI_ENUM_ONLY 186 /* Configure the expansion ROM address */ 187 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); 188 if (header_type != PCI_HEADER_TYPE_CARDBUS) { 189 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? 190 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; 191 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe); 192 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response); 193 if (bar_response) { 194 bar_size = -(bar_response & ~1); 195 debug("PCI Autoconfig: ROM, size=%#x, ", 196 (unsigned int)bar_size); 197 if (pciauto_region_allocate(mem, bar_size, 198 &bar_value) == 0) { 199 pci_hose_write_config_dword(hose, dev, rom_addr, 200 bar_value); 201 } 202 cmdstat |= PCI_COMMAND_MEMORY; 203 debug("\n"); 204 } 205 } 206 #endif 207 208 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat); 209 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 210 CONFIG_SYS_PCI_CACHE_LINE_SIZE); 211 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 212 } 213 214 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 215 pci_dev_t dev, int sub_bus) 216 { 217 struct pci_region *pci_mem; 218 struct pci_region *pci_prefetch; 219 struct pci_region *pci_io; 220 u16 cmdstat, prefechable_64; 221 222 #ifdef CONFIG_DM_PCI 223 /* The root controller has the region information */ 224 struct pci_controller *ctlr_hose = pci_bus_to_hose(0); 225 226 pci_mem = ctlr_hose->pci_mem; 227 pci_prefetch = ctlr_hose->pci_prefetch; 228 pci_io = ctlr_hose->pci_io; 229 #else 230 pci_mem = hose->pci_mem; 231 pci_prefetch = hose->pci_prefetch; 232 pci_io = hose->pci_io; 233 #endif 234 235 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); 236 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 237 &prefechable_64); 238 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 239 240 /* Configure bus number registers */ 241 #ifdef CONFIG_DM_PCI 242 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev)); 243 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus); 244 #else 245 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, 246 PCI_BUS(dev) - hose->first_busno); 247 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, 248 sub_bus - hose->first_busno); 249 #endif 250 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); 251 252 if (pci_mem) { 253 /* Round memory allocator to 1MB boundary */ 254 pciauto_region_align(pci_mem, 0x100000); 255 256 /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 257 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE, 258 (pci_mem->bus_lower & 0xfff00000) >> 16); 259 260 cmdstat |= PCI_COMMAND_MEMORY; 261 } 262 263 if (pci_prefetch) { 264 /* Round memory allocator to 1MB boundary */ 265 pciauto_region_align(pci_prefetch, 0x100000); 266 267 /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 268 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 269 (pci_prefetch->bus_lower & 0xfff00000) >> 16); 270 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 271 #ifdef CONFIG_SYS_PCI_64BIT 272 pci_hose_write_config_dword(hose, dev, 273 PCI_PREF_BASE_UPPER32, 274 pci_prefetch->bus_lower >> 32); 275 #else 276 pci_hose_write_config_dword(hose, dev, 277 PCI_PREF_BASE_UPPER32, 278 0x0); 279 #endif 280 281 cmdstat |= PCI_COMMAND_MEMORY; 282 } else { 283 /* We don't support prefetchable memory for now, so disable */ 284 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); 285 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0); 286 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { 287 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0); 288 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0); 289 } 290 } 291 292 if (pci_io) { 293 /* Round I/O allocator to 4KB boundary */ 294 pciauto_region_align(pci_io, 0x1000); 295 296 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE, 297 (pci_io->bus_lower & 0x0000f000) >> 8); 298 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16, 299 (pci_io->bus_lower & 0xffff0000) >> 16); 300 301 cmdstat |= PCI_COMMAND_IO; 302 } 303 304 /* Enable memory and I/O accesses, enable bus master */ 305 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 306 cmdstat | PCI_COMMAND_MASTER); 307 } 308 309 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 310 pci_dev_t dev, int sub_bus) 311 { 312 struct pci_region *pci_mem; 313 struct pci_region *pci_prefetch; 314 struct pci_region *pci_io; 315 316 #ifdef CONFIG_DM_PCI 317 /* The root controller has the region information */ 318 struct pci_controller *ctlr_hose = pci_bus_to_hose(0); 319 320 pci_mem = ctlr_hose->pci_mem; 321 pci_prefetch = ctlr_hose->pci_prefetch; 322 pci_io = ctlr_hose->pci_io; 323 #else 324 pci_mem = hose->pci_mem; 325 pci_prefetch = hose->pci_prefetch; 326 pci_io = hose->pci_io; 327 #endif 328 329 /* Configure bus number registers */ 330 #ifdef CONFIG_DM_PCI 331 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus); 332 #else 333 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 334 sub_bus - hose->first_busno); 335 #endif 336 337 if (pci_mem) { 338 /* Round memory allocator to 1MB boundary */ 339 pciauto_region_align(pci_mem, 0x100000); 340 341 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT, 342 (pci_mem->bus_lower - 1) >> 16); 343 } 344 345 if (pci_prefetch) { 346 u16 prefechable_64; 347 348 pci_hose_read_config_word(hose, dev, 349 PCI_PREF_MEMORY_LIMIT, 350 &prefechable_64); 351 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 352 353 /* Round memory allocator to 1MB boundary */ 354 pciauto_region_align(pci_prefetch, 0x100000); 355 356 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 357 (pci_prefetch->bus_lower - 1) >> 16); 358 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 359 #ifdef CONFIG_SYS_PCI_64BIT 360 pci_hose_write_config_dword(hose, dev, 361 PCI_PREF_LIMIT_UPPER32, 362 (pci_prefetch->bus_lower - 1) >> 32); 363 #else 364 pci_hose_write_config_dword(hose, dev, 365 PCI_PREF_LIMIT_UPPER32, 366 0x0); 367 #endif 368 } 369 370 if (pci_io) { 371 /* Round I/O allocator to 4KB boundary */ 372 pciauto_region_align(pci_io, 0x1000); 373 374 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT, 375 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); 376 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16, 377 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); 378 } 379 } 380 381 /* 382 * 383 */ 384 385 void pciauto_config_init(struct pci_controller *hose) 386 { 387 int i; 388 389 hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL; 390 391 for (i = 0; i < hose->region_count; i++) { 392 switch(hose->regions[i].flags) { 393 case PCI_REGION_IO: 394 if (!hose->pci_io || 395 hose->pci_io->size < hose->regions[i].size) 396 hose->pci_io = hose->regions + i; 397 break; 398 case PCI_REGION_MEM: 399 if (!hose->pci_mem || 400 hose->pci_mem->size < hose->regions[i].size) 401 hose->pci_mem = hose->regions + i; 402 break; 403 case (PCI_REGION_MEM | PCI_REGION_PREFETCH): 404 if (!hose->pci_prefetch || 405 hose->pci_prefetch->size < hose->regions[i].size) 406 hose->pci_prefetch = hose->regions + i; 407 break; 408 } 409 } 410 411 412 if (hose->pci_mem) { 413 pciauto_region_init(hose->pci_mem); 414 415 debug("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n" 416 "\t\tPhysical Memory [%llx-%llxx]\n", 417 (u64)hose->pci_mem->bus_start, 418 (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1), 419 (u64)hose->pci_mem->phys_start, 420 (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1)); 421 } 422 423 if (hose->pci_prefetch) { 424 pciauto_region_init(hose->pci_prefetch); 425 426 debug("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n" 427 "\t\tPhysical Memory [%llx-%llx]\n", 428 (u64)hose->pci_prefetch->bus_start, 429 (u64)(hose->pci_prefetch->bus_start + 430 hose->pci_prefetch->size - 1), 431 (u64)hose->pci_prefetch->phys_start, 432 (u64)(hose->pci_prefetch->phys_start + 433 hose->pci_prefetch->size - 1)); 434 } 435 436 if (hose->pci_io) { 437 pciauto_region_init(hose->pci_io); 438 439 debug("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n" 440 "\t\tPhysical Memory: [%llx-%llx]\n", 441 (u64)hose->pci_io->bus_start, 442 (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1), 443 (u64)hose->pci_io->phys_start, 444 (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1)); 445 446 } 447 } 448 449 /* 450 * HJF: Changed this to return int. I think this is required 451 * to get the correct result when scanning bridges 452 */ 453 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) 454 { 455 struct pci_region *pci_mem; 456 struct pci_region *pci_prefetch; 457 struct pci_region *pci_io; 458 unsigned int sub_bus = PCI_BUS(dev); 459 unsigned short class; 460 int n; 461 462 #ifdef CONFIG_DM_PCI 463 /* The root controller has the region information */ 464 struct pci_controller *ctlr_hose = pci_bus_to_hose(0); 465 466 pci_mem = ctlr_hose->pci_mem; 467 pci_prefetch = ctlr_hose->pci_prefetch; 468 pci_io = ctlr_hose->pci_io; 469 #else 470 pci_mem = hose->pci_mem; 471 pci_prefetch = hose->pci_prefetch; 472 pci_io = hose->pci_io; 473 #endif 474 475 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 476 477 switch (class) { 478 case PCI_CLASS_BRIDGE_PCI: 479 debug("PCI Autoconfig: Found P2P bridge, device %d\n", 480 PCI_DEV(dev)); 481 482 pciauto_setup_device(hose, dev, 2, pci_mem, 483 pci_prefetch, pci_io); 484 485 #ifdef CONFIG_DM_PCI 486 n = dm_pci_hose_probe_bus(hose, dev); 487 if (n < 0) 488 return n; 489 sub_bus = (unsigned int)n; 490 #else 491 /* Passing in current_busno allows for sibling P2P bridges */ 492 hose->current_busno++; 493 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 494 /* 495 * need to figure out if this is a subordinate bridge on the bus 496 * to be able to properly set the pri/sec/sub bridge registers. 497 */ 498 n = pci_hose_scan_bus(hose, hose->current_busno); 499 500 /* figure out the deepest we've gone for this leg */ 501 sub_bus = max((unsigned int)n, sub_bus); 502 pciauto_postscan_setup_bridge(hose, dev, sub_bus); 503 504 sub_bus = hose->current_busno; 505 #endif 506 break; 507 508 case PCI_CLASS_BRIDGE_CARDBUS: 509 /* 510 * just do a minimal setup of the bridge, 511 * let the OS take care of the rest 512 */ 513 pciauto_setup_device(hose, dev, 0, pci_mem, 514 pci_prefetch, pci_io); 515 516 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n", 517 PCI_DEV(dev)); 518 519 #ifndef CONFIG_DM_PCI 520 hose->current_busno++; 521 #endif 522 break; 523 524 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) 525 case PCI_CLASS_BRIDGE_OTHER: 526 debug("PCI Autoconfig: Skipping bridge device %d\n", 527 PCI_DEV(dev)); 528 break; 529 #endif 530 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) 531 case PCI_CLASS_BRIDGE_OTHER: 532 /* 533 * The host/PCI bridge 1 seems broken in 8349 - it presents 534 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ 535 * device claiming resources io/mem/irq.. we only allow for 536 * the PIMMR window to be allocated (BAR0 - 1MB size) 537 */ 538 debug("PCI Autoconfig: Broken bridge found, only minimal config\n"); 539 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 540 hose->pci_prefetch, hose->pci_io); 541 break; 542 #endif 543 544 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ 545 debug("PCI AutoConfig: Found PowerPC device\n"); 546 547 default: 548 pciauto_setup_device(hose, dev, 6, pci_mem, 549 pci_prefetch, pci_io); 550 break; 551 } 552 553 return sub_bus; 554 } 555