1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCI autoconfiguration library 4 * 5 * Author: Matt Porter <mporter@mvista.com> 6 * 7 * Copyright 2000 MontaVista Software Inc. 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <pci.h> 14 15 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ 16 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE 17 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 18 #endif 19 20 void dm_pciauto_setup_device(struct udevice *dev, int bars_num, 21 struct pci_region *mem, 22 struct pci_region *prefetch, struct pci_region *io, 23 bool enum_only) 24 { 25 u32 bar_response; 26 pci_size_t bar_size; 27 u16 cmdstat = 0; 28 int bar, bar_nr = 0; 29 u8 header_type; 30 int rom_addr; 31 pci_addr_t bar_value; 32 struct pci_region *bar_res = NULL; 33 int found_mem64 = 0; 34 u16 class; 35 36 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); 37 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | 38 PCI_COMMAND_MASTER; 39 40 for (bar = PCI_BASE_ADDRESS_0; 41 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { 42 /* Tickle the BAR and get the response */ 43 if (!enum_only) 44 dm_pci_write_config32(dev, bar, 0xffffffff); 45 dm_pci_read_config32(dev, bar, &bar_response); 46 47 /* If BAR is not implemented go to the next BAR */ 48 if (!bar_response) 49 continue; 50 51 found_mem64 = 0; 52 53 /* Check the BAR type and set our address mask */ 54 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 55 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) 56 & 0xffff) + 1; 57 if (!enum_only) 58 bar_res = io; 59 60 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", 61 bar_nr, (unsigned long long)bar_size); 62 } else { 63 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 64 PCI_BASE_ADDRESS_MEM_TYPE_64) { 65 u32 bar_response_upper; 66 u64 bar64; 67 68 if (!enum_only) { 69 dm_pci_write_config32(dev, bar + 4, 70 0xffffffff); 71 } 72 dm_pci_read_config32(dev, bar + 4, 73 &bar_response_upper); 74 75 bar64 = ((u64)bar_response_upper << 32) | 76 bar_response; 77 78 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) 79 + 1; 80 if (!enum_only) 81 found_mem64 = 1; 82 } else { 83 bar_size = (u32)(~(bar_response & 84 PCI_BASE_ADDRESS_MEM_MASK) + 1); 85 } 86 if (!enum_only) { 87 if (prefetch && (bar_response & 88 PCI_BASE_ADDRESS_MEM_PREFETCH)) { 89 bar_res = prefetch; 90 } else { 91 bar_res = mem; 92 } 93 } 94 95 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ", 96 bar_nr, bar_res == prefetch ? "Prf" : "Mem", 97 (unsigned long long)bar_size); 98 } 99 100 if (!enum_only && pciauto_region_allocate(bar_res, bar_size, 101 &bar_value) == 0) { 102 /* Write it out and update our limit */ 103 dm_pci_write_config32(dev, bar, (u32)bar_value); 104 105 if (found_mem64) { 106 bar += 4; 107 #ifdef CONFIG_SYS_PCI_64BIT 108 dm_pci_write_config32(dev, bar, 109 (u32)(bar_value >> 32)); 110 #else 111 /* 112 * If we are a 64-bit decoder then increment to 113 * the upper 32 bits of the bar and force it to 114 * locate in the lower 4GB of memory. 115 */ 116 dm_pci_write_config32(dev, bar, 0x00000000); 117 #endif 118 } 119 } 120 121 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? 122 PCI_COMMAND_IO : PCI_COMMAND_MEMORY; 123 124 debug("\n"); 125 126 bar_nr++; 127 } 128 129 if (!enum_only) { 130 /* Configure the expansion ROM address */ 131 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); 132 header_type &= 0x7f; 133 if (header_type != PCI_HEADER_TYPE_CARDBUS) { 134 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? 135 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; 136 dm_pci_write_config32(dev, rom_addr, 0xfffffffe); 137 dm_pci_read_config32(dev, rom_addr, &bar_response); 138 if (bar_response) { 139 bar_size = -(bar_response & ~1); 140 debug("PCI Autoconfig: ROM, size=%#x, ", 141 (unsigned int)bar_size); 142 if (pciauto_region_allocate(mem, bar_size, 143 &bar_value) == 0) { 144 dm_pci_write_config32(dev, rom_addr, 145 bar_value); 146 } 147 cmdstat |= PCI_COMMAND_MEMORY; 148 debug("\n"); 149 } 150 } 151 } 152 153 /* PCI_COMMAND_IO must be set for VGA device */ 154 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class); 155 if (class == PCI_CLASS_DISPLAY_VGA) 156 cmdstat |= PCI_COMMAND_IO; 157 158 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat); 159 dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 160 CONFIG_SYS_PCI_CACHE_LINE_SIZE); 161 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80); 162 } 163 164 void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) 165 { 166 struct pci_region *pci_mem; 167 struct pci_region *pci_prefetch; 168 struct pci_region *pci_io; 169 u16 cmdstat, prefechable_64; 170 struct udevice *ctlr = pci_get_controller(dev); 171 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); 172 173 pci_mem = ctlr_hose->pci_mem; 174 pci_prefetch = ctlr_hose->pci_prefetch; 175 pci_io = ctlr_hose->pci_io; 176 177 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); 178 dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64); 179 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 180 181 /* Configure bus number registers */ 182 dm_pci_write_config8(dev, PCI_PRIMARY_BUS, 183 PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq); 184 dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq); 185 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff); 186 187 if (pci_mem) { 188 /* Round memory allocator to 1MB boundary */ 189 pciauto_region_align(pci_mem, 0x100000); 190 191 /* 192 * Set up memory and I/O filter limits, assume 32-bit 193 * I/O space 194 */ 195 dm_pci_write_config16(dev, PCI_MEMORY_BASE, 196 (pci_mem->bus_lower & 0xfff00000) >> 16); 197 198 cmdstat |= PCI_COMMAND_MEMORY; 199 } 200 201 if (pci_prefetch) { 202 /* Round memory allocator to 1MB boundary */ 203 pciauto_region_align(pci_prefetch, 0x100000); 204 205 /* 206 * Set up memory and I/O filter limits, assume 32-bit 207 * I/O space 208 */ 209 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 210 (pci_prefetch->bus_lower & 0xfff00000) >> 16); 211 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 212 #ifdef CONFIG_SYS_PCI_64BIT 213 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 214 pci_prefetch->bus_lower >> 32); 215 #else 216 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0); 217 #endif 218 219 cmdstat |= PCI_COMMAND_MEMORY; 220 } else { 221 /* We don't support prefetchable memory for now, so disable */ 222 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000); 223 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0); 224 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { 225 dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0); 226 dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0); 227 } 228 } 229 230 if (pci_io) { 231 /* Round I/O allocator to 4KB boundary */ 232 pciauto_region_align(pci_io, 0x1000); 233 234 dm_pci_write_config8(dev, PCI_IO_BASE, 235 (pci_io->bus_lower & 0x0000f000) >> 8); 236 dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, 237 (pci_io->bus_lower & 0xffff0000) >> 16); 238 239 cmdstat |= PCI_COMMAND_IO; 240 } 241 242 /* Enable memory and I/O accesses, enable bus master */ 243 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); 244 } 245 246 void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) 247 { 248 struct pci_region *pci_mem; 249 struct pci_region *pci_prefetch; 250 struct pci_region *pci_io; 251 struct udevice *ctlr = pci_get_controller(dev); 252 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); 253 254 pci_mem = ctlr_hose->pci_mem; 255 pci_prefetch = ctlr_hose->pci_prefetch; 256 pci_io = ctlr_hose->pci_io; 257 258 /* Configure bus number registers */ 259 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq); 260 261 if (pci_mem) { 262 /* Round memory allocator to 1MB boundary */ 263 pciauto_region_align(pci_mem, 0x100000); 264 265 dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, 266 (pci_mem->bus_lower - 1) >> 16); 267 } 268 269 if (pci_prefetch) { 270 u16 prefechable_64; 271 272 dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT, 273 &prefechable_64); 274 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 275 276 /* Round memory allocator to 1MB boundary */ 277 pciauto_region_align(pci_prefetch, 0x100000); 278 279 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 280 (pci_prefetch->bus_lower - 1) >> 16); 281 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 282 #ifdef CONFIG_SYS_PCI_64BIT 283 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 284 (pci_prefetch->bus_lower - 1) >> 32); 285 #else 286 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0); 287 #endif 288 } 289 290 if (pci_io) { 291 /* Round I/O allocator to 4KB boundary */ 292 pciauto_region_align(pci_io, 0x1000); 293 294 dm_pci_write_config8(dev, PCI_IO_LIMIT, 295 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); 296 dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 297 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); 298 } 299 } 300 301 /* 302 * HJF: Changed this to return int. I think this is required 303 * to get the correct result when scanning bridges 304 */ 305 int dm_pciauto_config_device(struct udevice *dev) 306 { 307 struct pci_region *pci_mem; 308 struct pci_region *pci_prefetch; 309 struct pci_region *pci_io; 310 unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev)); 311 unsigned short class; 312 bool enum_only = false; 313 struct udevice *ctlr = pci_get_controller(dev); 314 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); 315 int n; 316 317 #ifdef CONFIG_PCI_ENUM_ONLY 318 enum_only = true; 319 #endif 320 321 pci_mem = ctlr_hose->pci_mem; 322 pci_prefetch = ctlr_hose->pci_prefetch; 323 pci_io = ctlr_hose->pci_io; 324 325 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class); 326 327 switch (class) { 328 case PCI_CLASS_BRIDGE_PCI: 329 debug("PCI Autoconfig: Found P2P bridge, device %d\n", 330 PCI_DEV(dm_pci_get_bdf(dev))); 331 332 dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io, 333 enum_only); 334 335 n = dm_pci_hose_probe_bus(dev); 336 if (n < 0) 337 return n; 338 sub_bus = (unsigned int)n; 339 break; 340 341 case PCI_CLASS_BRIDGE_CARDBUS: 342 /* 343 * just do a minimal setup of the bridge, 344 * let the OS take care of the rest 345 */ 346 dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io, 347 enum_only); 348 349 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n", 350 PCI_DEV(dm_pci_get_bdf(dev))); 351 352 break; 353 354 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) 355 case PCI_CLASS_BRIDGE_OTHER: 356 debug("PCI Autoconfig: Skipping bridge device %d\n", 357 PCI_DEV(dm_pci_get_bdf(dev))); 358 break; 359 #endif 360 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) 361 case PCI_CLASS_BRIDGE_OTHER: 362 /* 363 * The host/PCI bridge 1 seems broken in 8349 - it presents 364 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ 365 * device claiming resources io/mem/irq.. we only allow for 366 * the PIMMR window to be allocated (BAR0 - 1MB size) 367 */ 368 debug("PCI Autoconfig: Broken bridge found, only minimal config\n"); 369 dm_pciauto_setup_device(dev, 0, hose->pci_mem, 370 hose->pci_prefetch, hose->pci_io, 371 enum_only); 372 break; 373 #endif 374 375 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ 376 debug("PCI AutoConfig: Found PowerPC device\n"); 377 /* fall through */ 378 379 default: 380 dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io, 381 enum_only); 382 break; 383 } 384 385 return sub_bus; 386 } 387