1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCI autoconfiguration library 4 * 5 * Author: Matt Porter <mporter@mvista.com> 6 * 7 * Copyright 2000 MontaVista Software Inc. 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <pci.h> 14 15 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ 16 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE 17 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 18 #endif 19 20 void dm_pciauto_setup_device(struct udevice *dev, int bars_num, 21 struct pci_region *mem, 22 struct pci_region *prefetch, struct pci_region *io, 23 bool enum_only) 24 { 25 u32 bar_response; 26 pci_size_t bar_size; 27 u16 cmdstat = 0; 28 int bar, bar_nr = 0; 29 u8 header_type; 30 int rom_addr; 31 pci_addr_t bar_value; 32 struct pci_region *bar_res = NULL; 33 int found_mem64 = 0; 34 u16 class; 35 36 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); 37 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | 38 PCI_COMMAND_MASTER; 39 40 for (bar = PCI_BASE_ADDRESS_0; 41 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { 42 /* Tickle the BAR and get the response */ 43 if (!enum_only) 44 dm_pci_write_config32(dev, bar, 0xffffffff); 45 dm_pci_read_config32(dev, bar, &bar_response); 46 47 /* If BAR is not implemented go to the next BAR */ 48 if (!bar_response) 49 continue; 50 51 found_mem64 = 0; 52 53 /* Check the BAR type and set our address mask */ 54 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 55 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) 56 & 0xffff) + 1; 57 if (!enum_only) 58 bar_res = io; 59 60 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", 61 bar_nr, (unsigned long long)bar_size); 62 } else { 63 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 64 PCI_BASE_ADDRESS_MEM_TYPE_64) { 65 u32 bar_response_upper; 66 u64 bar64; 67 68 if (!enum_only) { 69 dm_pci_write_config32(dev, bar + 4, 70 0xffffffff); 71 } 72 dm_pci_read_config32(dev, bar + 4, 73 &bar_response_upper); 74 75 bar64 = ((u64)bar_response_upper << 32) | 76 bar_response; 77 78 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) 79 + 1; 80 if (!enum_only) 81 found_mem64 = 1; 82 } else { 83 bar_size = (u32)(~(bar_response & 84 PCI_BASE_ADDRESS_MEM_MASK) + 1); 85 } 86 if (!enum_only) { 87 if (prefetch && (bar_response & 88 PCI_BASE_ADDRESS_MEM_PREFETCH)) { 89 bar_res = prefetch; 90 } else { 91 bar_res = mem; 92 } 93 } 94 95 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ", 96 bar_nr, bar_res == prefetch ? "Prf" : "Mem", 97 (unsigned long long)bar_size); 98 } 99 100 if (!enum_only && pciauto_region_allocate(bar_res, bar_size, 101 &bar_value, 102 found_mem64) == 0) { 103 /* Write it out and update our limit */ 104 dm_pci_write_config32(dev, bar, (u32)bar_value); 105 106 if (found_mem64) { 107 bar += 4; 108 #ifdef CONFIG_SYS_PCI_64BIT 109 dm_pci_write_config32(dev, bar, 110 (u32)(bar_value >> 32)); 111 #else 112 /* 113 * If we are a 64-bit decoder then increment to 114 * the upper 32 bits of the bar and force it to 115 * locate in the lower 4GB of memory. 116 */ 117 dm_pci_write_config32(dev, bar, 0x00000000); 118 #endif 119 } 120 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? 121 PCI_COMMAND_IO : PCI_COMMAND_MEMORY; 122 } 123 124 debug("\n"); 125 126 bar_nr++; 127 } 128 129 if (!enum_only) { 130 /* Configure the expansion ROM address */ 131 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); 132 header_type &= 0x7f; 133 if (header_type != PCI_HEADER_TYPE_CARDBUS) { 134 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? 135 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; 136 dm_pci_write_config32(dev, rom_addr, 0xfffffffe); 137 dm_pci_read_config32(dev, rom_addr, &bar_response); 138 if (bar_response) { 139 bar_size = -(bar_response & ~1); 140 debug("PCI Autoconfig: ROM, size=%#x, ", 141 (unsigned int)bar_size); 142 if (pciauto_region_allocate(mem, bar_size, 143 &bar_value, 144 false) == 0) { 145 dm_pci_write_config32(dev, rom_addr, 146 bar_value); 147 } 148 cmdstat |= PCI_COMMAND_MEMORY; 149 debug("\n"); 150 } 151 } 152 } 153 154 /* PCI_COMMAND_IO must be set for VGA device */ 155 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class); 156 if (class == PCI_CLASS_DISPLAY_VGA) 157 cmdstat |= PCI_COMMAND_IO; 158 159 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat); 160 dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 161 CONFIG_SYS_PCI_CACHE_LINE_SIZE); 162 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80); 163 } 164 165 void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) 166 { 167 struct pci_region *pci_mem; 168 struct pci_region *pci_prefetch; 169 struct pci_region *pci_io; 170 u16 cmdstat, prefechable_64; 171 struct udevice *ctlr = pci_get_controller(dev); 172 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); 173 174 pci_mem = ctlr_hose->pci_mem; 175 pci_prefetch = ctlr_hose->pci_prefetch; 176 pci_io = ctlr_hose->pci_io; 177 178 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); 179 dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64); 180 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 181 182 /* Configure bus number registers */ 183 dm_pci_write_config8(dev, PCI_PRIMARY_BUS, 184 PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq); 185 dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq); 186 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff); 187 188 if (pci_mem) { 189 /* Round memory allocator to 1MB boundary */ 190 pciauto_region_align(pci_mem, 0x100000); 191 192 /* 193 * Set up memory and I/O filter limits, assume 32-bit 194 * I/O space 195 */ 196 dm_pci_write_config16(dev, PCI_MEMORY_BASE, 197 (pci_mem->bus_lower & 0xfff00000) >> 16); 198 199 cmdstat |= PCI_COMMAND_MEMORY; 200 } 201 202 if (pci_prefetch) { 203 /* Round memory allocator to 1MB boundary */ 204 pciauto_region_align(pci_prefetch, 0x100000); 205 206 /* 207 * Set up memory and I/O filter limits, assume 32-bit 208 * I/O space 209 */ 210 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 211 (pci_prefetch->bus_lower & 0xfff00000) >> 16); 212 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 213 #ifdef CONFIG_SYS_PCI_64BIT 214 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 215 pci_prefetch->bus_lower >> 32); 216 #else 217 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0); 218 #endif 219 220 cmdstat |= PCI_COMMAND_MEMORY; 221 } else { 222 /* We don't support prefetchable memory for now, so disable */ 223 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000); 224 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0); 225 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { 226 dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0); 227 dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0); 228 } 229 } 230 231 if (pci_io) { 232 /* Round I/O allocator to 4KB boundary */ 233 pciauto_region_align(pci_io, 0x1000); 234 235 dm_pci_write_config8(dev, PCI_IO_BASE, 236 (pci_io->bus_lower & 0x0000f000) >> 8); 237 dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, 238 (pci_io->bus_lower & 0xffff0000) >> 16); 239 240 cmdstat |= PCI_COMMAND_IO; 241 } 242 243 /* Enable memory and I/O accesses, enable bus master */ 244 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); 245 } 246 247 void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) 248 { 249 struct pci_region *pci_mem; 250 struct pci_region *pci_prefetch; 251 struct pci_region *pci_io; 252 struct udevice *ctlr = pci_get_controller(dev); 253 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); 254 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); 255 256 pci_mem = ctlr_hose->pci_mem; 257 pci_prefetch = ctlr_hose->pci_prefetch; 258 pci_io = ctlr_hose->pci_io; 259 260 /* Configure bus number registers */ 261 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq); 262 263 //ast2600 0x1a03 0x1150 pcie re-train for gen 2 config 264 if((pplat->vendor == 0x1a03) && (pplat->device == 0x1150)) 265 dm_pci_write_config8(dev, 0x90, 0x20); 266 267 if (pci_mem) { 268 /* Round memory allocator to 1MB boundary */ 269 pciauto_region_align(pci_mem, 0x100000); 270 271 dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, 272 (pci_mem->bus_lower - 1) >> 16); 273 } 274 275 if (pci_prefetch) { 276 u16 prefechable_64; 277 278 dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT, 279 &prefechable_64); 280 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 281 282 /* Round memory allocator to 1MB boundary */ 283 pciauto_region_align(pci_prefetch, 0x100000); 284 285 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 286 (pci_prefetch->bus_lower - 1) >> 16); 287 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 288 #ifdef CONFIG_SYS_PCI_64BIT 289 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 290 (pci_prefetch->bus_lower - 1) >> 32); 291 #else 292 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0); 293 #endif 294 } 295 296 if (pci_io) { 297 /* Round I/O allocator to 4KB boundary */ 298 pciauto_region_align(pci_io, 0x1000); 299 300 dm_pci_write_config8(dev, PCI_IO_LIMIT, 301 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); 302 dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 303 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); 304 } 305 } 306 307 /* 308 * HJF: Changed this to return int. I think this is required 309 * to get the correct result when scanning bridges 310 */ 311 int dm_pciauto_config_device(struct udevice *dev) 312 { 313 struct pci_region *pci_mem; 314 struct pci_region *pci_prefetch; 315 struct pci_region *pci_io; 316 unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev)); 317 unsigned short class; 318 bool enum_only = false; 319 struct udevice *ctlr = pci_get_controller(dev); 320 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); 321 int n; 322 323 #ifdef CONFIG_PCI_ENUM_ONLY 324 enum_only = true; 325 #endif 326 327 pci_mem = ctlr_hose->pci_mem; 328 pci_prefetch = ctlr_hose->pci_prefetch; 329 pci_io = ctlr_hose->pci_io; 330 331 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class); 332 333 switch (class) { 334 case PCI_CLASS_BRIDGE_PCI: 335 debug("PCI Autoconfig: Found P2P bridge, device %d\n", 336 PCI_DEV(dm_pci_get_bdf(dev))); 337 338 dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io, 339 enum_only); 340 341 n = dm_pci_hose_probe_bus(dev); 342 if (n < 0) 343 return n; 344 sub_bus = (unsigned int)n; 345 break; 346 347 case PCI_CLASS_BRIDGE_CARDBUS: 348 /* 349 * just do a minimal setup of the bridge, 350 * let the OS take care of the rest 351 */ 352 dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io, 353 enum_only); 354 355 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n", 356 PCI_DEV(dm_pci_get_bdf(dev))); 357 358 break; 359 360 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) 361 case PCI_CLASS_BRIDGE_OTHER: 362 debug("PCI Autoconfig: Skipping bridge device %d\n", 363 PCI_DEV(dm_pci_get_bdf(dev))); 364 break; 365 #endif 366 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) 367 case PCI_CLASS_BRIDGE_OTHER: 368 /* 369 * The host/PCI bridge 1 seems broken in 8349 - it presents 370 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ 371 * device claiming resources io/mem/irq.. we only allow for 372 * the PIMMR window to be allocated (BAR0 - 1MB size) 373 */ 374 debug("PCI Autoconfig: Broken bridge found, only minimal config\n"); 375 dm_pciauto_setup_device(dev, 0, hose->pci_mem, 376 hose->pci_prefetch, hose->pci_io, 377 enum_only); 378 break; 379 #endif 380 381 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ 382 debug("PCI AutoConfig: Found PowerPC device\n"); 383 /* fall through */ 384 385 default: 386 dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io, 387 enum_only); 388 break; 389 } 390 391 return sub_bus; 392 } 393