15e23b8b4SSimon Glass /* 25e23b8b4SSimon Glass * PCI autoconfiguration library 35e23b8b4SSimon Glass * 45e23b8b4SSimon Glass * Author: Matt Porter <mporter@mvista.com> 55e23b8b4SSimon Glass * 65e23b8b4SSimon Glass * Copyright 2000 MontaVista Software Inc. 75e23b8b4SSimon Glass * 85e23b8b4SSimon Glass * SPDX-License-Identifier: GPL-2.0+ 95e23b8b4SSimon Glass */ 105e23b8b4SSimon Glass 115e23b8b4SSimon Glass #include <common.h> 124439bc35SSimon Glass #include <dm.h> 135e23b8b4SSimon Glass #include <errno.h> 145e23b8b4SSimon Glass #include <pci.h> 155e23b8b4SSimon Glass 165e23b8b4SSimon Glass /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ 175e23b8b4SSimon Glass #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE 185e23b8b4SSimon Glass #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 195e23b8b4SSimon Glass #endif 205e23b8b4SSimon Glass 215e23b8b4SSimon Glass void dm_pciauto_setup_device(struct udevice *dev, int bars_num, 225e23b8b4SSimon Glass struct pci_region *mem, 235e23b8b4SSimon Glass struct pci_region *prefetch, struct pci_region *io, 245e23b8b4SSimon Glass bool enum_only) 255e23b8b4SSimon Glass { 265e23b8b4SSimon Glass u32 bar_response; 275e23b8b4SSimon Glass pci_size_t bar_size; 285e23b8b4SSimon Glass u16 cmdstat = 0; 295e23b8b4SSimon Glass int bar, bar_nr = 0; 305e23b8b4SSimon Glass u8 header_type; 315e23b8b4SSimon Glass int rom_addr; 325e23b8b4SSimon Glass pci_addr_t bar_value; 336796704bSBin Meng struct pci_region *bar_res = NULL; 345e23b8b4SSimon Glass int found_mem64 = 0; 355e23b8b4SSimon Glass u16 class; 365e23b8b4SSimon Glass 375e23b8b4SSimon Glass dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); 385e23b8b4SSimon Glass cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | 395e23b8b4SSimon Glass PCI_COMMAND_MASTER; 405e23b8b4SSimon Glass 415e23b8b4SSimon Glass for (bar = PCI_BASE_ADDRESS_0; 425e23b8b4SSimon Glass bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { 435e23b8b4SSimon Glass /* Tickle the BAR and get the response */ 445e23b8b4SSimon Glass if (!enum_only) 455e23b8b4SSimon Glass dm_pci_write_config32(dev, bar, 0xffffffff); 465e23b8b4SSimon Glass dm_pci_read_config32(dev, bar, &bar_response); 475e23b8b4SSimon Glass 485e23b8b4SSimon Glass /* If BAR is not implemented go to the next BAR */ 495e23b8b4SSimon Glass if (!bar_response) 505e23b8b4SSimon Glass continue; 515e23b8b4SSimon Glass 525e23b8b4SSimon Glass found_mem64 = 0; 535e23b8b4SSimon Glass 545e23b8b4SSimon Glass /* Check the BAR type and set our address mask */ 555e23b8b4SSimon Glass if (bar_response & PCI_BASE_ADDRESS_SPACE) { 565e23b8b4SSimon Glass bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) 575e23b8b4SSimon Glass & 0xffff) + 1; 585e23b8b4SSimon Glass if (!enum_only) 595e23b8b4SSimon Glass bar_res = io; 605e23b8b4SSimon Glass 615e23b8b4SSimon Glass debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", 625e23b8b4SSimon Glass bar_nr, (unsigned long long)bar_size); 635e23b8b4SSimon Glass } else { 645e23b8b4SSimon Glass if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 655e23b8b4SSimon Glass PCI_BASE_ADDRESS_MEM_TYPE_64) { 665e23b8b4SSimon Glass u32 bar_response_upper; 675e23b8b4SSimon Glass u64 bar64; 685e23b8b4SSimon Glass 695e23b8b4SSimon Glass if (!enum_only) { 705e23b8b4SSimon Glass dm_pci_write_config32(dev, bar + 4, 715e23b8b4SSimon Glass 0xffffffff); 725e23b8b4SSimon Glass } 735e23b8b4SSimon Glass dm_pci_read_config32(dev, bar + 4, 745e23b8b4SSimon Glass &bar_response_upper); 755e23b8b4SSimon Glass 765e23b8b4SSimon Glass bar64 = ((u64)bar_response_upper << 32) | 775e23b8b4SSimon Glass bar_response; 785e23b8b4SSimon Glass 795e23b8b4SSimon Glass bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) 805e23b8b4SSimon Glass + 1; 815e23b8b4SSimon Glass if (!enum_only) 825e23b8b4SSimon Glass found_mem64 = 1; 835e23b8b4SSimon Glass } else { 845e23b8b4SSimon Glass bar_size = (u32)(~(bar_response & 855e23b8b4SSimon Glass PCI_BASE_ADDRESS_MEM_MASK) + 1); 865e23b8b4SSimon Glass } 875e23b8b4SSimon Glass if (!enum_only) { 885e23b8b4SSimon Glass if (prefetch && (bar_response & 895e23b8b4SSimon Glass PCI_BASE_ADDRESS_MEM_PREFETCH)) { 905e23b8b4SSimon Glass bar_res = prefetch; 915e23b8b4SSimon Glass } else { 925e23b8b4SSimon Glass bar_res = mem; 935e23b8b4SSimon Glass } 945e23b8b4SSimon Glass } 955e23b8b4SSimon Glass 965e23b8b4SSimon Glass debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ", 975e23b8b4SSimon Glass bar_nr, bar_res == prefetch ? "Prf" : "Mem", 985e23b8b4SSimon Glass (unsigned long long)bar_size); 995e23b8b4SSimon Glass } 1005e23b8b4SSimon Glass 1015e23b8b4SSimon Glass if (!enum_only && pciauto_region_allocate(bar_res, bar_size, 1025e23b8b4SSimon Glass &bar_value) == 0) { 1035e23b8b4SSimon Glass /* Write it out and update our limit */ 1045e23b8b4SSimon Glass dm_pci_write_config32(dev, bar, (u32)bar_value); 1055e23b8b4SSimon Glass 1065e23b8b4SSimon Glass if (found_mem64) { 1075e23b8b4SSimon Glass bar += 4; 1085e23b8b4SSimon Glass #ifdef CONFIG_SYS_PCI_64BIT 1095e23b8b4SSimon Glass dm_pci_write_config32(dev, bar, 1105e23b8b4SSimon Glass (u32)(bar_value >> 32)); 1115e23b8b4SSimon Glass #else 1125e23b8b4SSimon Glass /* 1135e23b8b4SSimon Glass * If we are a 64-bit decoder then increment to 1145e23b8b4SSimon Glass * the upper 32 bits of the bar and force it to 1155e23b8b4SSimon Glass * locate in the lower 4GB of memory. 1165e23b8b4SSimon Glass */ 1175e23b8b4SSimon Glass dm_pci_write_config32(dev, bar, 0x00000000); 1185e23b8b4SSimon Glass #endif 1195e23b8b4SSimon Glass } 1205e23b8b4SSimon Glass } 1215e23b8b4SSimon Glass 1225e23b8b4SSimon Glass cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? 1235e23b8b4SSimon Glass PCI_COMMAND_IO : PCI_COMMAND_MEMORY; 1245e23b8b4SSimon Glass 1255e23b8b4SSimon Glass debug("\n"); 1265e23b8b4SSimon Glass 1275e23b8b4SSimon Glass bar_nr++; 1285e23b8b4SSimon Glass } 1295e23b8b4SSimon Glass 1305e23b8b4SSimon Glass if (!enum_only) { 1315e23b8b4SSimon Glass /* Configure the expansion ROM address */ 1325e23b8b4SSimon Glass dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); 1335e23b8b4SSimon Glass header_type &= 0x7f; 1345e23b8b4SSimon Glass if (header_type != PCI_HEADER_TYPE_CARDBUS) { 1355e23b8b4SSimon Glass rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? 1365e23b8b4SSimon Glass PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; 1375e23b8b4SSimon Glass dm_pci_write_config32(dev, rom_addr, 0xfffffffe); 1385e23b8b4SSimon Glass dm_pci_read_config32(dev, rom_addr, &bar_response); 1395e23b8b4SSimon Glass if (bar_response) { 1405e23b8b4SSimon Glass bar_size = -(bar_response & ~1); 1415e23b8b4SSimon Glass debug("PCI Autoconfig: ROM, size=%#x, ", 1425e23b8b4SSimon Glass (unsigned int)bar_size); 1435e23b8b4SSimon Glass if (pciauto_region_allocate(mem, bar_size, 1445e23b8b4SSimon Glass &bar_value) == 0) { 1455e23b8b4SSimon Glass dm_pci_write_config32(dev, rom_addr, 1465e23b8b4SSimon Glass bar_value); 1475e23b8b4SSimon Glass } 1485e23b8b4SSimon Glass cmdstat |= PCI_COMMAND_MEMORY; 1495e23b8b4SSimon Glass debug("\n"); 1505e23b8b4SSimon Glass } 1515e23b8b4SSimon Glass } 1525e23b8b4SSimon Glass } 1535e23b8b4SSimon Glass 1545e23b8b4SSimon Glass /* PCI_COMMAND_IO must be set for VGA device */ 1555e23b8b4SSimon Glass dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class); 1565e23b8b4SSimon Glass if (class == PCI_CLASS_DISPLAY_VGA) 1575e23b8b4SSimon Glass cmdstat |= PCI_COMMAND_IO; 1585e23b8b4SSimon Glass 1595e23b8b4SSimon Glass dm_pci_write_config16(dev, PCI_COMMAND, cmdstat); 1605e23b8b4SSimon Glass dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 1615e23b8b4SSimon Glass CONFIG_SYS_PCI_CACHE_LINE_SIZE); 1625e23b8b4SSimon Glass dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80); 1635e23b8b4SSimon Glass } 1645e23b8b4SSimon Glass 1655e23b8b4SSimon Glass void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) 1665e23b8b4SSimon Glass { 1675e23b8b4SSimon Glass struct pci_region *pci_mem; 1685e23b8b4SSimon Glass struct pci_region *pci_prefetch; 1695e23b8b4SSimon Glass struct pci_region *pci_io; 1705e23b8b4SSimon Glass u16 cmdstat, prefechable_64; 1714439bc35SSimon Glass struct udevice *ctlr = pci_get_controller(dev); 1724439bc35SSimon Glass struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); 1735e23b8b4SSimon Glass 1745e23b8b4SSimon Glass pci_mem = ctlr_hose->pci_mem; 1755e23b8b4SSimon Glass pci_prefetch = ctlr_hose->pci_prefetch; 1765e23b8b4SSimon Glass pci_io = ctlr_hose->pci_io; 1775e23b8b4SSimon Glass 1785e23b8b4SSimon Glass dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); 1795e23b8b4SSimon Glass dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64); 1805e23b8b4SSimon Glass prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 1815e23b8b4SSimon Glass 1825e23b8b4SSimon Glass /* Configure bus number registers */ 1835e23b8b4SSimon Glass dm_pci_write_config8(dev, PCI_PRIMARY_BUS, 184*3977dcd5SMinghuan Lian PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq); 185*3977dcd5SMinghuan Lian dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq); 1865e23b8b4SSimon Glass dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff); 1875e23b8b4SSimon Glass 1885e23b8b4SSimon Glass if (pci_mem) { 1895e23b8b4SSimon Glass /* Round memory allocator to 1MB boundary */ 1905e23b8b4SSimon Glass pciauto_region_align(pci_mem, 0x100000); 1915e23b8b4SSimon Glass 1925e23b8b4SSimon Glass /* 1935e23b8b4SSimon Glass * Set up memory and I/O filter limits, assume 32-bit 1945e23b8b4SSimon Glass * I/O space 1955e23b8b4SSimon Glass */ 1965e23b8b4SSimon Glass dm_pci_write_config16(dev, PCI_MEMORY_BASE, 1975e23b8b4SSimon Glass (pci_mem->bus_lower & 0xfff00000) >> 16); 1985e23b8b4SSimon Glass 1995e23b8b4SSimon Glass cmdstat |= PCI_COMMAND_MEMORY; 2005e23b8b4SSimon Glass } 2015e23b8b4SSimon Glass 2025e23b8b4SSimon Glass if (pci_prefetch) { 2035e23b8b4SSimon Glass /* Round memory allocator to 1MB boundary */ 2045e23b8b4SSimon Glass pciauto_region_align(pci_prefetch, 0x100000); 2055e23b8b4SSimon Glass 2065e23b8b4SSimon Glass /* 2075e23b8b4SSimon Glass * Set up memory and I/O filter limits, assume 32-bit 2085e23b8b4SSimon Glass * I/O space 2095e23b8b4SSimon Glass */ 2105e23b8b4SSimon Glass dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 2115e23b8b4SSimon Glass (pci_prefetch->bus_lower & 0xfff00000) >> 16); 2125e23b8b4SSimon Glass if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 2135e23b8b4SSimon Glass #ifdef CONFIG_SYS_PCI_64BIT 2145e23b8b4SSimon Glass dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 2155e23b8b4SSimon Glass pci_prefetch->bus_lower >> 32); 2165e23b8b4SSimon Glass #else 2175e23b8b4SSimon Glass dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0); 2185e23b8b4SSimon Glass #endif 2195e23b8b4SSimon Glass 2205e23b8b4SSimon Glass cmdstat |= PCI_COMMAND_MEMORY; 2215e23b8b4SSimon Glass } else { 2225e23b8b4SSimon Glass /* We don't support prefetchable memory for now, so disable */ 2235e23b8b4SSimon Glass dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000); 2245e23b8b4SSimon Glass dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0); 2255e23b8b4SSimon Glass if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { 2265e23b8b4SSimon Glass dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0); 2275e23b8b4SSimon Glass dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0); 2285e23b8b4SSimon Glass } 2295e23b8b4SSimon Glass } 2305e23b8b4SSimon Glass 2315e23b8b4SSimon Glass if (pci_io) { 2325e23b8b4SSimon Glass /* Round I/O allocator to 4KB boundary */ 2335e23b8b4SSimon Glass pciauto_region_align(pci_io, 0x1000); 2345e23b8b4SSimon Glass 2355e23b8b4SSimon Glass dm_pci_write_config8(dev, PCI_IO_BASE, 2365e23b8b4SSimon Glass (pci_io->bus_lower & 0x0000f000) >> 8); 2375e23b8b4SSimon Glass dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, 2385e23b8b4SSimon Glass (pci_io->bus_lower & 0xffff0000) >> 16); 2395e23b8b4SSimon Glass 2405e23b8b4SSimon Glass cmdstat |= PCI_COMMAND_IO; 2415e23b8b4SSimon Glass } 2425e23b8b4SSimon Glass 2435e23b8b4SSimon Glass /* Enable memory and I/O accesses, enable bus master */ 2445e23b8b4SSimon Glass dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); 2455e23b8b4SSimon Glass } 2465e23b8b4SSimon Glass 2475e23b8b4SSimon Glass void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) 2485e23b8b4SSimon Glass { 2495e23b8b4SSimon Glass struct pci_region *pci_mem; 2505e23b8b4SSimon Glass struct pci_region *pci_prefetch; 2515e23b8b4SSimon Glass struct pci_region *pci_io; 2524439bc35SSimon Glass struct udevice *ctlr = pci_get_controller(dev); 2534439bc35SSimon Glass struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); 2545e23b8b4SSimon Glass 2555e23b8b4SSimon Glass pci_mem = ctlr_hose->pci_mem; 2565e23b8b4SSimon Glass pci_prefetch = ctlr_hose->pci_prefetch; 2575e23b8b4SSimon Glass pci_io = ctlr_hose->pci_io; 2585e23b8b4SSimon Glass 2595e23b8b4SSimon Glass /* Configure bus number registers */ 260*3977dcd5SMinghuan Lian dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq); 2615e23b8b4SSimon Glass 2625e23b8b4SSimon Glass if (pci_mem) { 2635e23b8b4SSimon Glass /* Round memory allocator to 1MB boundary */ 2645e23b8b4SSimon Glass pciauto_region_align(pci_mem, 0x100000); 2655e23b8b4SSimon Glass 2665e23b8b4SSimon Glass dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, 2675e23b8b4SSimon Glass (pci_mem->bus_lower - 1) >> 16); 2685e23b8b4SSimon Glass } 2695e23b8b4SSimon Glass 2705e23b8b4SSimon Glass if (pci_prefetch) { 2715e23b8b4SSimon Glass u16 prefechable_64; 2725e23b8b4SSimon Glass 2735e23b8b4SSimon Glass dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT, 2745e23b8b4SSimon Glass &prefechable_64); 2755e23b8b4SSimon Glass prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 2765e23b8b4SSimon Glass 2775e23b8b4SSimon Glass /* Round memory allocator to 1MB boundary */ 2785e23b8b4SSimon Glass pciauto_region_align(pci_prefetch, 0x100000); 2795e23b8b4SSimon Glass 2805e23b8b4SSimon Glass dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 2815e23b8b4SSimon Glass (pci_prefetch->bus_lower - 1) >> 16); 2825e23b8b4SSimon Glass if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 2835e23b8b4SSimon Glass #ifdef CONFIG_SYS_PCI_64BIT 2845e23b8b4SSimon Glass dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 2855e23b8b4SSimon Glass (pci_prefetch->bus_lower - 1) >> 32); 2865e23b8b4SSimon Glass #else 2875e23b8b4SSimon Glass dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0); 2885e23b8b4SSimon Glass #endif 2895e23b8b4SSimon Glass } 2905e23b8b4SSimon Glass 2915e23b8b4SSimon Glass if (pci_io) { 2925e23b8b4SSimon Glass /* Round I/O allocator to 4KB boundary */ 2935e23b8b4SSimon Glass pciauto_region_align(pci_io, 0x1000); 2945e23b8b4SSimon Glass 2955e23b8b4SSimon Glass dm_pci_write_config8(dev, PCI_IO_LIMIT, 2965e23b8b4SSimon Glass ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); 2975e23b8b4SSimon Glass dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 2985e23b8b4SSimon Glass ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); 2995e23b8b4SSimon Glass } 3005e23b8b4SSimon Glass } 3015e23b8b4SSimon Glass 3025e23b8b4SSimon Glass /* 3035e23b8b4SSimon Glass * HJF: Changed this to return int. I think this is required 3045e23b8b4SSimon Glass * to get the correct result when scanning bridges 3055e23b8b4SSimon Glass */ 3065e23b8b4SSimon Glass int dm_pciauto_config_device(struct udevice *dev) 3075e23b8b4SSimon Glass { 3085e23b8b4SSimon Glass struct pci_region *pci_mem; 3095e23b8b4SSimon Glass struct pci_region *pci_prefetch; 3105e23b8b4SSimon Glass struct pci_region *pci_io; 3115e23b8b4SSimon Glass unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev)); 3125e23b8b4SSimon Glass unsigned short class; 3135e23b8b4SSimon Glass bool enum_only = false; 3144439bc35SSimon Glass struct udevice *ctlr = pci_get_controller(dev); 3154439bc35SSimon Glass struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); 3165e23b8b4SSimon Glass int n; 3175e23b8b4SSimon Glass 3185e23b8b4SSimon Glass #ifdef CONFIG_PCI_ENUM_ONLY 3195e23b8b4SSimon Glass enum_only = true; 3205e23b8b4SSimon Glass #endif 3215e23b8b4SSimon Glass 3225e23b8b4SSimon Glass pci_mem = ctlr_hose->pci_mem; 3235e23b8b4SSimon Glass pci_prefetch = ctlr_hose->pci_prefetch; 3245e23b8b4SSimon Glass pci_io = ctlr_hose->pci_io; 3255e23b8b4SSimon Glass 3265e23b8b4SSimon Glass dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class); 3275e23b8b4SSimon Glass 3285e23b8b4SSimon Glass switch (class) { 3295e23b8b4SSimon Glass case PCI_CLASS_BRIDGE_PCI: 3305e23b8b4SSimon Glass debug("PCI Autoconfig: Found P2P bridge, device %d\n", 3315e23b8b4SSimon Glass PCI_DEV(dm_pci_get_bdf(dev))); 3325e23b8b4SSimon Glass 3335e23b8b4SSimon Glass dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io, 3345e23b8b4SSimon Glass enum_only); 3355e23b8b4SSimon Glass 3365e23b8b4SSimon Glass n = dm_pci_hose_probe_bus(dev); 3375e23b8b4SSimon Glass if (n < 0) 3385e23b8b4SSimon Glass return n; 3395e23b8b4SSimon Glass sub_bus = (unsigned int)n; 3405e23b8b4SSimon Glass break; 3415e23b8b4SSimon Glass 3425e23b8b4SSimon Glass case PCI_CLASS_BRIDGE_CARDBUS: 3435e23b8b4SSimon Glass /* 3445e23b8b4SSimon Glass * just do a minimal setup of the bridge, 3455e23b8b4SSimon Glass * let the OS take care of the rest 3465e23b8b4SSimon Glass */ 3475e23b8b4SSimon Glass dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io, 3485e23b8b4SSimon Glass enum_only); 3495e23b8b4SSimon Glass 3505e23b8b4SSimon Glass debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n", 3515e23b8b4SSimon Glass PCI_DEV(dm_pci_get_bdf(dev))); 3525e23b8b4SSimon Glass 3535e23b8b4SSimon Glass break; 3545e23b8b4SSimon Glass 3555e23b8b4SSimon Glass #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) 3565e23b8b4SSimon Glass case PCI_CLASS_BRIDGE_OTHER: 3575e23b8b4SSimon Glass debug("PCI Autoconfig: Skipping bridge device %d\n", 3585e23b8b4SSimon Glass PCI_DEV(dm_pci_get_bdf(dev))); 3595e23b8b4SSimon Glass break; 3605e23b8b4SSimon Glass #endif 3615e23b8b4SSimon Glass #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) 3625e23b8b4SSimon Glass case PCI_CLASS_BRIDGE_OTHER: 3635e23b8b4SSimon Glass /* 3645e23b8b4SSimon Glass * The host/PCI bridge 1 seems broken in 8349 - it presents 3655e23b8b4SSimon Glass * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ 3665e23b8b4SSimon Glass * device claiming resources io/mem/irq.. we only allow for 3675e23b8b4SSimon Glass * the PIMMR window to be allocated (BAR0 - 1MB size) 3685e23b8b4SSimon Glass */ 3695e23b8b4SSimon Glass debug("PCI Autoconfig: Broken bridge found, only minimal config\n"); 3705e23b8b4SSimon Glass dm_pciauto_setup_device(dev, 0, hose->pci_mem, 3715e23b8b4SSimon Glass hose->pci_prefetch, hose->pci_io, 3725e23b8b4SSimon Glass enum_only); 3735e23b8b4SSimon Glass break; 3745e23b8b4SSimon Glass #endif 3755e23b8b4SSimon Glass 3765e23b8b4SSimon Glass case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ 3775e23b8b4SSimon Glass debug("PCI AutoConfig: Found PowerPC device\n"); 378f19345b5SSimon Glass /* fall through */ 3795e23b8b4SSimon Glass 3805e23b8b4SSimon Glass default: 3815e23b8b4SSimon Glass dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io, 3825e23b8b4SSimon Glass enum_only); 3835e23b8b4SSimon Glass break; 3845e23b8b4SSimon Glass } 3855e23b8b4SSimon Glass 3865e23b8b4SSimon Glass return sub_bus; 3875e23b8b4SSimon Glass } 388