xref: /openbmc/u-boot/drivers/pci/pci.c (revision d330e04d9d427a26381b59f40875af17f4c288a2)
1  /*
2   * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3   * Andreas Heppel <aheppel@sysgo.de>
4   *
5   * (C) Copyright 2002, 2003
6   * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7   *
8   * SPDX-License-Identifier:	GPL-2.0+
9   */
10  
11  /*
12   * Old PCI routines
13   *
14   * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
15   * and change pci-uclass.c.
16   */
17  
18  #include <common.h>
19  
20  #include <command.h>
21  #include <errno.h>
22  #include <asm/processor.h>
23  #include <asm/io.h>
24  #include <pci.h>
25  
26  DECLARE_GLOBAL_DATA_PTR;
27  
28  #define PCI_HOSE_OP(rw, size, type)					\
29  int pci_hose_##rw##_config_##size(struct pci_controller *hose,		\
30  				  pci_dev_t dev,			\
31  				  int offset, type value)		\
32  {									\
33  	return hose->rw##_##size(hose, dev, offset, value);		\
34  }
35  
36  PCI_HOSE_OP(read, byte, u8 *)
37  PCI_HOSE_OP(read, word, u16 *)
38  PCI_HOSE_OP(read, dword, u32 *)
39  PCI_HOSE_OP(write, byte, u8)
40  PCI_HOSE_OP(write, word, u16)
41  PCI_HOSE_OP(write, dword, u32)
42  
43  #define PCI_OP(rw, size, type, error_code)				\
44  int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)	\
45  {									\
46  	struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));	\
47  									\
48  	if (!hose)							\
49  	{								\
50  		error_code;						\
51  		return -1;						\
52  	}								\
53  									\
54  	return pci_hose_##rw##_config_##size(hose, dev, offset, value);	\
55  }
56  
57  PCI_OP(read, byte, u8 *, *value = 0xff)
58  PCI_OP(read, word, u16 *, *value = 0xffff)
59  PCI_OP(read, dword, u32 *, *value = 0xffffffff)
60  PCI_OP(write, byte, u8, )
61  PCI_OP(write, word, u16, )
62  PCI_OP(write, dword, u32, )
63  
64  #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)			\
65  int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
66  					pci_dev_t dev,			\
67  					int offset, type val)		\
68  {									\
69  	u32 val32;							\
70  									\
71  	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) {	\
72  		*val = -1;						\
73  		return -1;						\
74  	}								\
75  									\
76  	*val = (val32 >> ((offset & (int)off_mask) * 8));		\
77  									\
78  	return 0;							\
79  }
80  
81  #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)		\
82  int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
83  					     pci_dev_t dev,		\
84  					     int offset, type val)	\
85  {									\
86  	u32 val32, mask, ldata, shift;					\
87  									\
88  	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
89  		return -1;						\
90  									\
91  	shift = ((offset & (int)off_mask) * 8);				\
92  	ldata = (((unsigned long)val) & val_mask) << shift;		\
93  	mask = val_mask << shift;					\
94  	val32 = (val32 & ~mask) | ldata;				\
95  									\
96  	if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
97  		return -1;						\
98  									\
99  	return 0;							\
100  }
101  
102  PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
103  PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
104  PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
105  PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
106  
107  /*
108   *
109   */
110  
111  static struct pci_controller* hose_head;
112  
113  struct pci_controller *pci_get_hose_head(void)
114  {
115  	if (gd->hose)
116  		return gd->hose;
117  
118  	return hose_head;
119  }
120  
121  void pci_register_hose(struct pci_controller* hose)
122  {
123  	struct pci_controller **phose = &hose_head;
124  
125  	while(*phose)
126  		phose = &(*phose)->next;
127  
128  	hose->next = NULL;
129  
130  	*phose = hose;
131  }
132  
133  struct pci_controller *pci_bus_to_hose(int bus)
134  {
135  	struct pci_controller *hose;
136  
137  	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
138  		if (bus >= hose->first_busno && bus <= hose->last_busno)
139  			return hose;
140  	}
141  
142  	printf("pci_bus_to_hose() failed\n");
143  	return NULL;
144  }
145  
146  struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
147  {
148  	struct pci_controller *hose;
149  
150  	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
151  		if (hose->cfg_addr == cfg_addr)
152  			return hose;
153  	}
154  
155  	return NULL;
156  }
157  
158  int pci_last_busno(void)
159  {
160  	struct pci_controller *hose = pci_get_hose_head();
161  
162  	if (!hose)
163  		return -1;
164  
165  	while (hose->next)
166  		hose = hose->next;
167  
168  	return hose->last_busno;
169  }
170  
171  pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
172  {
173  	struct pci_controller * hose;
174  	pci_dev_t bdf;
175  	int bus;
176  
177  	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
178  		for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
179  			bdf = pci_hose_find_devices(hose, bus, ids, &index);
180  			if (bdf != -1)
181  				return bdf;
182  		}
183  	}
184  
185  	return -1;
186  }
187  
188  int pci_hose_config_device(struct pci_controller *hose,
189  			   pci_dev_t dev,
190  			   unsigned long io,
191  			   pci_addr_t mem,
192  			   unsigned long command)
193  {
194  	u32 bar_response;
195  	unsigned int old_command;
196  	pci_addr_t bar_value;
197  	pci_size_t bar_size;
198  	unsigned char pin;
199  	int bar, found_mem64;
200  
201  	debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
202  		(u64)mem, command);
203  
204  	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
205  
206  	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
207  		pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
208  		pci_hose_read_config_dword(hose, dev, bar, &bar_response);
209  
210  		if (!bar_response)
211  			continue;
212  
213  		found_mem64 = 0;
214  
215  		/* Check the BAR type and set our address mask */
216  		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
217  			bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
218  			/* round up region base address to a multiple of size */
219  			io = ((io - 1) | (bar_size - 1)) + 1;
220  			bar_value = io;
221  			/* compute new region base address */
222  			io = io + bar_size;
223  		} else {
224  			if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
225  				PCI_BASE_ADDRESS_MEM_TYPE_64) {
226  				u32 bar_response_upper;
227  				u64 bar64;
228  				pci_hose_write_config_dword(hose, dev, bar + 4,
229  					0xffffffff);
230  				pci_hose_read_config_dword(hose, dev, bar + 4,
231  					&bar_response_upper);
232  
233  				bar64 = ((u64)bar_response_upper << 32) | bar_response;
234  
235  				bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
236  				found_mem64 = 1;
237  			} else {
238  				bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
239  			}
240  
241  			/* round up region base address to multiple of size */
242  			mem = ((mem - 1) | (bar_size - 1)) + 1;
243  			bar_value = mem;
244  			/* compute new region base address */
245  			mem = mem + bar_size;
246  		}
247  
248  		/* Write it out and update our limit */
249  		pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
250  
251  		if (found_mem64) {
252  			bar += 4;
253  #ifdef CONFIG_SYS_PCI_64BIT
254  			pci_hose_write_config_dword(hose, dev, bar,
255  				(u32)(bar_value >> 32));
256  #else
257  			pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
258  #endif
259  		}
260  	}
261  
262  	/* Configure Cache Line Size Register */
263  	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
264  
265  	/* Configure Latency Timer */
266  	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
267  
268  	/* Disable interrupt line, if device says it wants to use interrupts */
269  	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
270  	if (pin != 0) {
271  		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
272  					   PCI_INTERRUPT_LINE_DISABLE);
273  	}
274  
275  	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
276  	pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
277  				     (old_command & 0xffff0000) | command);
278  
279  	return 0;
280  }
281  
282  /*
283   *
284   */
285  
286  struct pci_config_table *pci_find_config(struct pci_controller *hose,
287  					 unsigned short class,
288  					 unsigned int vendor,
289  					 unsigned int device,
290  					 unsigned int bus,
291  					 unsigned int dev,
292  					 unsigned int func)
293  {
294  	struct pci_config_table *table;
295  
296  	for (table = hose->config_table; table && table->vendor; table++) {
297  		if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
298  		    (table->device == PCI_ANY_ID || table->device == device) &&
299  		    (table->class  == PCI_ANY_ID || table->class  == class)  &&
300  		    (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
301  		    (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
302  		    (table->func   == PCI_ANY_ID || table->func   == func)) {
303  			return table;
304  		}
305  	}
306  
307  	return NULL;
308  }
309  
310  void pci_cfgfunc_config_device(struct pci_controller *hose,
311  			       pci_dev_t dev,
312  			       struct pci_config_table *entry)
313  {
314  	pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
315  		entry->priv[2]);
316  }
317  
318  void pci_cfgfunc_do_nothing(struct pci_controller *hose,
319  			    pci_dev_t dev, struct pci_config_table *entry)
320  {
321  }
322  
323  /*
324   * HJF: Changed this to return int. I think this is required
325   * to get the correct result when scanning bridges
326   */
327  extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
328  
329  #ifdef CONFIG_PCI_SCAN_SHOW
330  __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
331  {
332  	if (dev == PCI_BDF(hose->first_busno, 0, 0))
333  		return 0;
334  
335  	return 1;
336  }
337  #endif /* CONFIG_PCI_SCAN_SHOW */
338  
339  int pci_hose_scan_bus(struct pci_controller *hose, int bus)
340  {
341  	unsigned int sub_bus, found_multi = 0;
342  	unsigned short vendor, device, class;
343  	unsigned char header_type;
344  #ifndef CONFIG_PCI_PNP
345  	struct pci_config_table *cfg;
346  #endif
347  	pci_dev_t dev;
348  #ifdef CONFIG_PCI_SCAN_SHOW
349  	static int indent = 0;
350  #endif
351  
352  	sub_bus = bus;
353  
354  	for (dev =  PCI_BDF(bus,0,0);
355  	     dev <  PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
356  				PCI_MAX_PCI_FUNCTIONS - 1);
357  	     dev += PCI_BDF(0, 0, 1)) {
358  
359  		if (pci_skip_dev(hose, dev))
360  			continue;
361  
362  		if (PCI_FUNC(dev) && !found_multi)
363  			continue;
364  
365  		pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
366  
367  		pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
368  
369  		if (vendor == 0xffff || vendor == 0x0000)
370  			continue;
371  
372  		if (!PCI_FUNC(dev))
373  			found_multi = header_type & 0x80;
374  
375  		debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
376  			PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
377  
378  		pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
379  		pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
380  
381  #ifdef CONFIG_PCI_FIXUP_DEV
382  		board_pci_fixup_dev(hose, dev, vendor, device, class);
383  #endif
384  
385  #ifdef CONFIG_PCI_SCAN_SHOW
386  		indent++;
387  
388  		/* Print leading space, including bus indentation */
389  		printf("%*c", indent + 1, ' ');
390  
391  		if (pci_print_dev(hose, dev)) {
392  			printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
393  			       PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
394  			       vendor, device, pci_class_str(class >> 8));
395  		}
396  #endif
397  
398  #ifdef CONFIG_PCI_PNP
399  		sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
400  			      sub_bus);
401  #else
402  		cfg = pci_find_config(hose, class, vendor, device,
403  				      PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
404  		if (cfg) {
405  			cfg->config_device(hose, dev, cfg);
406  			sub_bus = max(sub_bus,
407  				      (unsigned int)hose->current_busno);
408  		}
409  #endif
410  
411  #ifdef CONFIG_PCI_SCAN_SHOW
412  		indent--;
413  #endif
414  
415  		if (hose->fixup_irq)
416  			hose->fixup_irq(hose, dev);
417  	}
418  
419  	return sub_bus;
420  }
421  
422  int pci_hose_scan(struct pci_controller *hose)
423  {
424  #if defined(CONFIG_PCI_BOOTDELAY)
425  	char *s;
426  	int i;
427  
428  	if (!gd->pcidelay_done) {
429  		/* wait "pcidelay" ms (if defined)... */
430  		s = env_get("pcidelay");
431  		if (s) {
432  			int val = simple_strtoul(s, NULL, 10);
433  			for (i = 0; i < val; i++)
434  				udelay(1000);
435  		}
436  		gd->pcidelay_done = 1;
437  	}
438  #endif /* CONFIG_PCI_BOOTDELAY */
439  
440  #ifdef CONFIG_PCI_SCAN_SHOW
441  	puts("PCI:\n");
442  #endif
443  
444  	/*
445  	 * Start scan at current_busno.
446  	 * PCIe will start scan at first_busno+1.
447  	 */
448  	/* For legacy support, ensure current >= first */
449  	if (hose->first_busno > hose->current_busno)
450  		hose->current_busno = hose->first_busno;
451  #ifdef CONFIG_PCI_PNP
452  	pciauto_config_init(hose);
453  #endif
454  	return pci_hose_scan_bus(hose, hose->current_busno);
455  }
456  
457  void pci_init(void)
458  {
459  	hose_head = NULL;
460  
461  	/* allow env to disable pci init/enum */
462  	if (env_get("pcidisable") != NULL)
463  		return;
464  
465  	/* now call board specific pci_init()... */
466  	pci_init_board();
467  }
468  
469  /* Returns the address of the requested capability structure within the
470   * device's PCI configuration space or 0 in case the device does not
471   * support it.
472   * */
473  int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
474  			     int cap)
475  {
476  	int pos;
477  	u8 hdr_type;
478  
479  	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
480  
481  	pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
482  
483  	if (pos)
484  		pos = pci_find_cap(hose, dev, pos, cap);
485  
486  	return pos;
487  }
488  
489  /* Find the header pointer to the Capabilities*/
490  int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
491  			    u8 hdr_type)
492  {
493  	u16 status;
494  
495  	pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
496  
497  	if (!(status & PCI_STATUS_CAP_LIST))
498  		return 0;
499  
500  	switch (hdr_type) {
501  	case PCI_HEADER_TYPE_NORMAL:
502  	case PCI_HEADER_TYPE_BRIDGE:
503  		return PCI_CAPABILITY_LIST;
504  	case PCI_HEADER_TYPE_CARDBUS:
505  		return PCI_CB_CAPABILITY_LIST;
506  	default:
507  		return 0;
508  	}
509  }
510  
511  int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
512  {
513  	int ttl = PCI_FIND_CAP_TTL;
514  	u8 id;
515  	u8 next_pos;
516  
517  	while (ttl--) {
518  		pci_hose_read_config_byte(hose, dev, pos, &next_pos);
519  		if (next_pos < CAP_START_POS)
520  			break;
521  		next_pos &= ~3;
522  		pos = (int) next_pos;
523  		pci_hose_read_config_byte(hose, dev,
524  					  pos + PCI_CAP_LIST_ID, &id);
525  		if (id == 0xff)
526  			break;
527  		if (id == cap)
528  			return pos;
529  		pos += PCI_CAP_LIST_NEXT;
530  	}
531  	return 0;
532  }
533  
534  /**
535   * pci_find_next_ext_capability - Find an extended capability
536   *
537   * Returns the address of the next matching extended capability structure
538   * within the device's PCI configuration space or 0 if the device does
539   * not support it.  Some capabilities can occur several times, e.g., the
540   * vendor-specific capability, and this provides a way to find them all.
541   */
542  int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
543  				 int start, int cap)
544  {
545  	u32 header;
546  	int ttl, pos = PCI_CFG_SPACE_SIZE;
547  
548  	/* minimum 8 bytes per capability */
549  	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
550  
551  	if (start)
552  		pos = start;
553  
554  	pci_hose_read_config_dword(hose, dev, pos, &header);
555  	if (header == 0xffffffff || header == 0)
556  		return 0;
557  
558  	while (ttl-- > 0) {
559  		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
560  			return pos;
561  
562  		pos = PCI_EXT_CAP_NEXT(header);
563  		if (pos < PCI_CFG_SPACE_SIZE)
564  			break;
565  
566  		pci_hose_read_config_dword(hose, dev, pos, &header);
567  		if (header == 0xffffffff || header == 0)
568  			break;
569  	}
570  
571  	return 0;
572  }
573  
574  /**
575   * pci_hose_find_ext_capability - Find an extended capability
576   *
577   * Returns the address of the requested extended capability structure
578   * within the device's PCI configuration space or 0 if the device does
579   * not support it.
580   */
581  int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
582  				 int cap)
583  {
584  	return pci_find_next_ext_capability(hose, dev, 0, cap);
585  }
586