1 /* 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3 * Andreas Heppel <aheppel@sysgo.de> 4 * 5 * (C) Copyright 2002, 2003 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * PCI routines 13 */ 14 15 #include <common.h> 16 17 #include <command.h> 18 #include <asm/processor.h> 19 #include <asm/io.h> 20 #include <pci.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 #define PCI_HOSE_OP(rw, size, type) \ 25 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ 26 pci_dev_t dev, \ 27 int offset, type value) \ 28 { \ 29 return hose->rw##_##size(hose, dev, offset, value); \ 30 } 31 32 PCI_HOSE_OP(read, byte, u8 *) 33 PCI_HOSE_OP(read, word, u16 *) 34 PCI_HOSE_OP(read, dword, u32 *) 35 PCI_HOSE_OP(write, byte, u8) 36 PCI_HOSE_OP(write, word, u16) 37 PCI_HOSE_OP(write, dword, u32) 38 39 #define PCI_OP(rw, size, type, error_code) \ 40 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ 41 { \ 42 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ 43 \ 44 if (!hose) \ 45 { \ 46 error_code; \ 47 return -1; \ 48 } \ 49 \ 50 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ 51 } 52 53 PCI_OP(read, byte, u8 *, *value = 0xff) 54 PCI_OP(read, word, u16 *, *value = 0xffff) 55 PCI_OP(read, dword, u32 *, *value = 0xffffffff) 56 PCI_OP(write, byte, u8, ) 57 PCI_OP(write, word, u16, ) 58 PCI_OP(write, dword, u32, ) 59 60 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ 61 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ 62 pci_dev_t dev, \ 63 int offset, type val) \ 64 { \ 65 u32 val32; \ 66 \ 67 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ 68 *val = -1; \ 69 return -1; \ 70 } \ 71 \ 72 *val = (val32 >> ((offset & (int)off_mask) * 8)); \ 73 \ 74 return 0; \ 75 } 76 77 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ 78 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\ 79 pci_dev_t dev, \ 80 int offset, type val) \ 81 { \ 82 u32 val32, mask, ldata, shift; \ 83 \ 84 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ 85 return -1; \ 86 \ 87 shift = ((offset & (int)off_mask) * 8); \ 88 ldata = (((unsigned long)val) & val_mask) << shift; \ 89 mask = val_mask << shift; \ 90 val32 = (val32 & ~mask) | ldata; \ 91 \ 92 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\ 93 return -1; \ 94 \ 95 return 0; \ 96 } 97 98 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) 99 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) 100 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) 101 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) 102 103 /* Get a virtual address associated with a BAR region */ 104 void *pci_map_bar(pci_dev_t pdev, int bar, int flags) 105 { 106 pci_addr_t pci_bus_addr; 107 u32 bar_response; 108 109 /* read BAR address */ 110 pci_read_config_dword(pdev, bar, &bar_response); 111 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); 112 113 /* 114 * Pass "0" as the length argument to pci_bus_to_virt. The arg 115 * isn't actualy used on any platform because u-boot assumes a static 116 * linear mapping. In the future, this could read the BAR size 117 * and pass that as the size if needed. 118 */ 119 return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE); 120 } 121 122 /* 123 * 124 */ 125 126 static struct pci_controller* hose_head; 127 128 struct pci_controller *pci_get_hose_head(void) 129 { 130 if (gd->hose) 131 return gd->hose; 132 133 return hose_head; 134 } 135 136 void pci_register_hose(struct pci_controller* hose) 137 { 138 struct pci_controller **phose = &hose_head; 139 140 while(*phose) 141 phose = &(*phose)->next; 142 143 hose->next = NULL; 144 145 *phose = hose; 146 } 147 148 struct pci_controller *pci_bus_to_hose(int bus) 149 { 150 struct pci_controller *hose; 151 152 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 153 if (bus >= hose->first_busno && bus <= hose->last_busno) 154 return hose; 155 } 156 157 printf("pci_bus_to_hose() failed\n"); 158 return NULL; 159 } 160 161 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) 162 { 163 struct pci_controller *hose; 164 165 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 166 if (hose->cfg_addr == cfg_addr) 167 return hose; 168 } 169 170 return NULL; 171 } 172 173 int pci_last_busno(void) 174 { 175 struct pci_controller *hose = pci_get_hose_head(); 176 177 if (!hose) 178 return -1; 179 180 while (hose->next) 181 hose = hose->next; 182 183 return hose->last_busno; 184 } 185 186 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) 187 { 188 struct pci_controller * hose; 189 u16 vendor, device; 190 u8 header_type; 191 pci_dev_t bdf; 192 int i, bus, found_multi = 0; 193 194 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 195 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 196 for (bus = hose->last_busno; bus >= hose->first_busno; bus--) 197 #else 198 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) 199 #endif 200 for (bdf = PCI_BDF(bus, 0, 0); 201 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX) 202 bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, 203 PCI_MAX_PCI_FUNCTIONS - 1); 204 #else 205 bdf < PCI_BDF(bus + 1, 0, 0); 206 #endif 207 bdf += PCI_BDF(0, 0, 1)) { 208 if (pci_skip_dev(hose, bdf)) 209 continue; 210 211 if (!PCI_FUNC(bdf)) { 212 pci_read_config_byte(bdf, 213 PCI_HEADER_TYPE, 214 &header_type); 215 216 found_multi = header_type & 0x80; 217 } else { 218 if (!found_multi) 219 continue; 220 } 221 222 pci_read_config_word(bdf, 223 PCI_VENDOR_ID, 224 &vendor); 225 pci_read_config_word(bdf, 226 PCI_DEVICE_ID, 227 &device); 228 229 for (i = 0; ids[i].vendor != 0; i++) { 230 if (vendor == ids[i].vendor && 231 device == ids[i].device) { 232 if (index <= 0) 233 return bdf; 234 235 index--; 236 } 237 } 238 } 239 } 240 241 return -1; 242 } 243 244 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) 245 { 246 struct pci_device_id ids[2] = { {}, {0, 0} }; 247 248 ids[0].vendor = vendor; 249 ids[0].device = device; 250 251 return pci_find_devices(ids, index); 252 } 253 254 /* 255 * 256 */ 257 258 int __pci_hose_phys_to_bus(struct pci_controller *hose, 259 phys_addr_t phys_addr, 260 unsigned long flags, 261 unsigned long skip_mask, 262 pci_addr_t *ba) 263 { 264 struct pci_region *res; 265 pci_addr_t bus_addr; 266 int i; 267 268 for (i = 0; i < hose->region_count; i++) { 269 res = &hose->regions[i]; 270 271 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) 272 continue; 273 274 if (res->flags & skip_mask) 275 continue; 276 277 bus_addr = phys_addr - res->phys_start + res->bus_start; 278 279 if (bus_addr >= res->bus_start && 280 bus_addr < res->bus_start + res->size) { 281 *ba = bus_addr; 282 return 0; 283 } 284 } 285 286 return 1; 287 } 288 289 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose, 290 phys_addr_t phys_addr, 291 unsigned long flags) 292 { 293 pci_addr_t bus_addr = 0; 294 int ret; 295 296 if (!hose) { 297 puts("pci_hose_phys_to_bus: invalid hose\n"); 298 return bus_addr; 299 } 300 301 /* 302 * if PCI_REGION_MEM is set we do a two pass search with preference 303 * on matches that don't have PCI_REGION_SYS_MEMORY set 304 */ 305 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) { 306 ret = __pci_hose_phys_to_bus(hose, phys_addr, 307 flags, PCI_REGION_SYS_MEMORY, &bus_addr); 308 if (!ret) 309 return bus_addr; 310 } 311 312 ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr); 313 314 if (ret) 315 puts("pci_hose_phys_to_bus: invalid physical address\n"); 316 317 return bus_addr; 318 } 319 320 int __pci_hose_bus_to_phys(struct pci_controller *hose, 321 pci_addr_t bus_addr, 322 unsigned long flags, 323 unsigned long skip_mask, 324 phys_addr_t *pa) 325 { 326 struct pci_region *res; 327 int i; 328 329 for (i = 0; i < hose->region_count; i++) { 330 res = &hose->regions[i]; 331 332 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) 333 continue; 334 335 if (res->flags & skip_mask) 336 continue; 337 338 if (bus_addr >= res->bus_start && 339 (bus_addr - res->bus_start) < res->size) { 340 *pa = (bus_addr - res->bus_start + res->phys_start); 341 return 0; 342 } 343 } 344 345 return 1; 346 } 347 348 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 349 pci_addr_t bus_addr, 350 unsigned long flags) 351 { 352 phys_addr_t phys_addr = 0; 353 int ret; 354 355 if (!hose) { 356 puts("pci_hose_bus_to_phys: invalid hose\n"); 357 return phys_addr; 358 } 359 360 /* 361 * if PCI_REGION_MEM is set we do a two pass search with preference 362 * on matches that don't have PCI_REGION_SYS_MEMORY set 363 */ 364 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) { 365 ret = __pci_hose_bus_to_phys(hose, bus_addr, 366 flags, PCI_REGION_SYS_MEMORY, &phys_addr); 367 if (!ret) 368 return phys_addr; 369 } 370 371 ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr); 372 373 if (ret) 374 puts("pci_hose_bus_to_phys: invalid physical address\n"); 375 376 return phys_addr; 377 } 378 379 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, 380 u32 addr_and_ctrl) 381 { 382 int bar; 383 384 bar = PCI_BASE_ADDRESS_0 + barnum * 4; 385 pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl); 386 } 387 388 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum) 389 { 390 u32 addr; 391 int bar; 392 393 bar = PCI_BASE_ADDRESS_0 + barnum * 4; 394 pci_hose_read_config_dword(hose, dev, bar, &addr); 395 if (addr & PCI_BASE_ADDRESS_SPACE_IO) 396 return addr & PCI_BASE_ADDRESS_IO_MASK; 397 else 398 return addr & PCI_BASE_ADDRESS_MEM_MASK; 399 } 400 401 int pci_hose_config_device(struct pci_controller *hose, 402 pci_dev_t dev, 403 unsigned long io, 404 pci_addr_t mem, 405 unsigned long command) 406 { 407 u32 bar_response; 408 unsigned int old_command; 409 pci_addr_t bar_value; 410 pci_size_t bar_size; 411 unsigned char pin; 412 int bar, found_mem64; 413 414 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io, 415 (u64)mem, command); 416 417 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0); 418 419 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { 420 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); 421 pci_hose_read_config_dword(hose, dev, bar, &bar_response); 422 423 if (!bar_response) 424 continue; 425 426 found_mem64 = 0; 427 428 /* Check the BAR type and set our address mask */ 429 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 430 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; 431 /* round up region base address to a multiple of size */ 432 io = ((io - 1) | (bar_size - 1)) + 1; 433 bar_value = io; 434 /* compute new region base address */ 435 io = io + bar_size; 436 } else { 437 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 438 PCI_BASE_ADDRESS_MEM_TYPE_64) { 439 u32 bar_response_upper; 440 u64 bar64; 441 pci_hose_write_config_dword(hose, dev, bar + 4, 442 0xffffffff); 443 pci_hose_read_config_dword(hose, dev, bar + 4, 444 &bar_response_upper); 445 446 bar64 = ((u64)bar_response_upper << 32) | bar_response; 447 448 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; 449 found_mem64 = 1; 450 } else { 451 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); 452 } 453 454 /* round up region base address to multiple of size */ 455 mem = ((mem - 1) | (bar_size - 1)) + 1; 456 bar_value = mem; 457 /* compute new region base address */ 458 mem = mem + bar_size; 459 } 460 461 /* Write it out and update our limit */ 462 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value); 463 464 if (found_mem64) { 465 bar += 4; 466 #ifdef CONFIG_SYS_PCI_64BIT 467 pci_hose_write_config_dword(hose, dev, bar, 468 (u32)(bar_value >> 32)); 469 #else 470 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); 471 #endif 472 } 473 } 474 475 /* Configure Cache Line Size Register */ 476 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 477 478 /* Configure Latency Timer */ 479 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 480 481 /* Disable interrupt line, if device says it wants to use interrupts */ 482 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); 483 if (pin != 0) { 484 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff); 485 } 486 487 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command); 488 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 489 (old_command & 0xffff0000) | command); 490 491 return 0; 492 } 493 494 /* 495 * 496 */ 497 498 struct pci_config_table *pci_find_config(struct pci_controller *hose, 499 unsigned short class, 500 unsigned int vendor, 501 unsigned int device, 502 unsigned int bus, 503 unsigned int dev, 504 unsigned int func) 505 { 506 struct pci_config_table *table; 507 508 for (table = hose->config_table; table && table->vendor; table++) { 509 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && 510 (table->device == PCI_ANY_ID || table->device == device) && 511 (table->class == PCI_ANY_ID || table->class == class) && 512 (table->bus == PCI_ANY_ID || table->bus == bus) && 513 (table->dev == PCI_ANY_ID || table->dev == dev) && 514 (table->func == PCI_ANY_ID || table->func == func)) { 515 return table; 516 } 517 } 518 519 return NULL; 520 } 521 522 void pci_cfgfunc_config_device(struct pci_controller *hose, 523 pci_dev_t dev, 524 struct pci_config_table *entry) 525 { 526 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], 527 entry->priv[2]); 528 } 529 530 void pci_cfgfunc_do_nothing(struct pci_controller *hose, 531 pci_dev_t dev, struct pci_config_table *entry) 532 { 533 } 534 535 /* 536 * HJF: Changed this to return int. I think this is required 537 * to get the correct result when scanning bridges 538 */ 539 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 540 541 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW) 542 const char * pci_class_str(u8 class) 543 { 544 switch (class) { 545 case PCI_CLASS_NOT_DEFINED: 546 return "Build before PCI Rev2.0"; 547 break; 548 case PCI_BASE_CLASS_STORAGE: 549 return "Mass storage controller"; 550 break; 551 case PCI_BASE_CLASS_NETWORK: 552 return "Network controller"; 553 break; 554 case PCI_BASE_CLASS_DISPLAY: 555 return "Display controller"; 556 break; 557 case PCI_BASE_CLASS_MULTIMEDIA: 558 return "Multimedia device"; 559 break; 560 case PCI_BASE_CLASS_MEMORY: 561 return "Memory controller"; 562 break; 563 case PCI_BASE_CLASS_BRIDGE: 564 return "Bridge device"; 565 break; 566 case PCI_BASE_CLASS_COMMUNICATION: 567 return "Simple comm. controller"; 568 break; 569 case PCI_BASE_CLASS_SYSTEM: 570 return "Base system peripheral"; 571 break; 572 case PCI_BASE_CLASS_INPUT: 573 return "Input device"; 574 break; 575 case PCI_BASE_CLASS_DOCKING: 576 return "Docking station"; 577 break; 578 case PCI_BASE_CLASS_PROCESSOR: 579 return "Processor"; 580 break; 581 case PCI_BASE_CLASS_SERIAL: 582 return "Serial bus controller"; 583 break; 584 case PCI_BASE_CLASS_INTELLIGENT: 585 return "Intelligent controller"; 586 break; 587 case PCI_BASE_CLASS_SATELLITE: 588 return "Satellite controller"; 589 break; 590 case PCI_BASE_CLASS_CRYPT: 591 return "Cryptographic device"; 592 break; 593 case PCI_BASE_CLASS_SIGNAL_PROCESSING: 594 return "DSP"; 595 break; 596 case PCI_CLASS_OTHERS: 597 return "Does not fit any class"; 598 break; 599 default: 600 return "???"; 601 break; 602 }; 603 } 604 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */ 605 606 __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) 607 { 608 /* 609 * Check if pci device should be skipped in configuration 610 */ 611 if (dev == PCI_BDF(hose->first_busno, 0, 0)) { 612 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */ 613 /* 614 * Only skip configuration if "pciconfighost" is not set 615 */ 616 if (getenv("pciconfighost") == NULL) 617 return 1; 618 #else 619 return 1; 620 #endif 621 } 622 623 return 0; 624 } 625 626 #ifdef CONFIG_PCI_SCAN_SHOW 627 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) 628 { 629 if (dev == PCI_BDF(hose->first_busno, 0, 0)) 630 return 0; 631 632 return 1; 633 } 634 #endif /* CONFIG_PCI_SCAN_SHOW */ 635 636 int pci_hose_scan_bus(struct pci_controller *hose, int bus) 637 { 638 unsigned int sub_bus, found_multi = 0; 639 unsigned short vendor, device, class; 640 unsigned char header_type; 641 #ifndef CONFIG_PCI_PNP 642 struct pci_config_table *cfg; 643 #endif 644 pci_dev_t dev; 645 #ifdef CONFIG_PCI_SCAN_SHOW 646 static int indent = 0; 647 #endif 648 649 sub_bus = bus; 650 651 for (dev = PCI_BDF(bus,0,0); 652 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, 653 PCI_MAX_PCI_FUNCTIONS - 1); 654 dev += PCI_BDF(0, 0, 1)) { 655 656 if (pci_skip_dev(hose, dev)) 657 continue; 658 659 if (PCI_FUNC(dev) && !found_multi) 660 continue; 661 662 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); 663 664 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); 665 666 if (vendor == 0xffff || vendor == 0x0000) 667 continue; 668 669 if (!PCI_FUNC(dev)) 670 found_multi = header_type & 0x80; 671 672 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n", 673 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 674 675 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); 676 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 677 678 #ifdef CONFIG_PCI_FIXUP_DEV 679 board_pci_fixup_dev(hose, dev, vendor, device, class); 680 #endif 681 682 #ifdef CONFIG_PCI_SCAN_SHOW 683 indent++; 684 685 /* Print leading space, including bus indentation */ 686 printf("%*c", indent + 1, ' '); 687 688 if (pci_print_dev(hose, dev)) { 689 printf("%02x:%02x.%-*x - %04x:%04x - %s\n", 690 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev), 691 vendor, device, pci_class_str(class >> 8)); 692 } 693 #endif 694 695 #ifdef CONFIG_PCI_PNP 696 sub_bus = max((unsigned int)pciauto_config_device(hose, dev), 697 sub_bus); 698 #else 699 cfg = pci_find_config(hose, class, vendor, device, 700 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 701 if (cfg) { 702 cfg->config_device(hose, dev, cfg); 703 sub_bus = max(sub_bus, 704 (unsigned int)hose->current_busno); 705 } 706 #endif 707 708 #ifdef CONFIG_PCI_SCAN_SHOW 709 indent--; 710 #endif 711 712 if (hose->fixup_irq) 713 hose->fixup_irq(hose, dev); 714 } 715 716 return sub_bus; 717 } 718 719 int pci_hose_scan(struct pci_controller *hose) 720 { 721 #if defined(CONFIG_PCI_BOOTDELAY) 722 char *s; 723 int i; 724 725 if (!gd->pcidelay_done) { 726 /* wait "pcidelay" ms (if defined)... */ 727 s = getenv("pcidelay"); 728 if (s) { 729 int val = simple_strtoul(s, NULL, 10); 730 for (i = 0; i < val; i++) 731 udelay(1000); 732 } 733 gd->pcidelay_done = 1; 734 } 735 #endif /* CONFIG_PCI_BOOTDELAY */ 736 737 /* 738 * Start scan at current_busno. 739 * PCIe will start scan at first_busno+1. 740 */ 741 /* For legacy support, ensure current >= first */ 742 if (hose->first_busno > hose->current_busno) 743 hose->current_busno = hose->first_busno; 744 #ifdef CONFIG_PCI_PNP 745 pciauto_config_init(hose); 746 #endif 747 return pci_hose_scan_bus(hose, hose->current_busno); 748 } 749 750 void pci_init(void) 751 { 752 hose_head = NULL; 753 754 /* now call board specific pci_init()... */ 755 pci_init_board(); 756 } 757 758 /* Returns the address of the requested capability structure within the 759 * device's PCI configuration space or 0 in case the device does not 760 * support it. 761 * */ 762 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 763 int cap) 764 { 765 int pos; 766 u8 hdr_type; 767 768 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); 769 770 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); 771 772 if (pos) 773 pos = pci_find_cap(hose, dev, pos, cap); 774 775 return pos; 776 } 777 778 /* Find the header pointer to the Capabilities*/ 779 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 780 u8 hdr_type) 781 { 782 u16 status; 783 784 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); 785 786 if (!(status & PCI_STATUS_CAP_LIST)) 787 return 0; 788 789 switch (hdr_type) { 790 case PCI_HEADER_TYPE_NORMAL: 791 case PCI_HEADER_TYPE_BRIDGE: 792 return PCI_CAPABILITY_LIST; 793 case PCI_HEADER_TYPE_CARDBUS: 794 return PCI_CB_CAPABILITY_LIST; 795 default: 796 return 0; 797 } 798 } 799 800 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) 801 { 802 int ttl = PCI_FIND_CAP_TTL; 803 u8 id; 804 u8 next_pos; 805 806 while (ttl--) { 807 pci_hose_read_config_byte(hose, dev, pos, &next_pos); 808 if (next_pos < CAP_START_POS) 809 break; 810 next_pos &= ~3; 811 pos = (int) next_pos; 812 pci_hose_read_config_byte(hose, dev, 813 pos + PCI_CAP_LIST_ID, &id); 814 if (id == 0xff) 815 break; 816 if (id == cap) 817 return pos; 818 pos += PCI_CAP_LIST_NEXT; 819 } 820 return 0; 821 } 822