1 /* 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3 * Andreas Heppel <aheppel@sysgo.de> 4 * 5 * (C) Copyright 2002, 2003 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * PCI routines 13 */ 14 15 #include <common.h> 16 17 #include <command.h> 18 #include <errno.h> 19 #include <asm/processor.h> 20 #include <asm/io.h> 21 #include <pci.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define PCI_HOSE_OP(rw, size, type) \ 26 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ 27 pci_dev_t dev, \ 28 int offset, type value) \ 29 { \ 30 return hose->rw##_##size(hose, dev, offset, value); \ 31 } 32 33 PCI_HOSE_OP(read, byte, u8 *) 34 PCI_HOSE_OP(read, word, u16 *) 35 PCI_HOSE_OP(read, dword, u32 *) 36 PCI_HOSE_OP(write, byte, u8) 37 PCI_HOSE_OP(write, word, u16) 38 PCI_HOSE_OP(write, dword, u32) 39 40 #define PCI_OP(rw, size, type, error_code) \ 41 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ 42 { \ 43 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ 44 \ 45 if (!hose) \ 46 { \ 47 error_code; \ 48 return -1; \ 49 } \ 50 \ 51 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ 52 } 53 54 PCI_OP(read, byte, u8 *, *value = 0xff) 55 PCI_OP(read, word, u16 *, *value = 0xffff) 56 PCI_OP(read, dword, u32 *, *value = 0xffffffff) 57 PCI_OP(write, byte, u8, ) 58 PCI_OP(write, word, u16, ) 59 PCI_OP(write, dword, u32, ) 60 61 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ 62 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ 63 pci_dev_t dev, \ 64 int offset, type val) \ 65 { \ 66 u32 val32; \ 67 \ 68 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ 69 *val = -1; \ 70 return -1; \ 71 } \ 72 \ 73 *val = (val32 >> ((offset & (int)off_mask) * 8)); \ 74 \ 75 return 0; \ 76 } 77 78 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ 79 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\ 80 pci_dev_t dev, \ 81 int offset, type val) \ 82 { \ 83 u32 val32, mask, ldata, shift; \ 84 \ 85 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ 86 return -1; \ 87 \ 88 shift = ((offset & (int)off_mask) * 8); \ 89 ldata = (((unsigned long)val) & val_mask) << shift; \ 90 mask = val_mask << shift; \ 91 val32 = (val32 & ~mask) | ldata; \ 92 \ 93 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\ 94 return -1; \ 95 \ 96 return 0; \ 97 } 98 99 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) 100 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) 101 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) 102 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) 103 104 /* 105 * 106 */ 107 108 static struct pci_controller* hose_head; 109 110 struct pci_controller *pci_get_hose_head(void) 111 { 112 if (gd->hose) 113 return gd->hose; 114 115 return hose_head; 116 } 117 118 void pci_register_hose(struct pci_controller* hose) 119 { 120 struct pci_controller **phose = &hose_head; 121 122 while(*phose) 123 phose = &(*phose)->next; 124 125 hose->next = NULL; 126 127 *phose = hose; 128 } 129 130 struct pci_controller *pci_bus_to_hose(int bus) 131 { 132 struct pci_controller *hose; 133 134 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 135 if (bus >= hose->first_busno && bus <= hose->last_busno) 136 return hose; 137 } 138 139 printf("pci_bus_to_hose() failed\n"); 140 return NULL; 141 } 142 143 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) 144 { 145 struct pci_controller *hose; 146 147 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 148 if (hose->cfg_addr == cfg_addr) 149 return hose; 150 } 151 152 return NULL; 153 } 154 155 int pci_last_busno(void) 156 { 157 struct pci_controller *hose = pci_get_hose_head(); 158 159 if (!hose) 160 return -1; 161 162 while (hose->next) 163 hose = hose->next; 164 165 return hose->last_busno; 166 } 167 168 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) 169 { 170 struct pci_controller * hose; 171 pci_dev_t bdf; 172 int bus; 173 174 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 175 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 176 for (bus = hose->last_busno; bus >= hose->first_busno; bus--) { 177 #else 178 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) { 179 #endif 180 bdf = pci_hose_find_devices(hose, bus, ids, &index); 181 if (bdf != -1) 182 return bdf; 183 } 184 } 185 186 return -1; 187 } 188 189 int pci_hose_config_device(struct pci_controller *hose, 190 pci_dev_t dev, 191 unsigned long io, 192 pci_addr_t mem, 193 unsigned long command) 194 { 195 u32 bar_response; 196 unsigned int old_command; 197 pci_addr_t bar_value; 198 pci_size_t bar_size; 199 unsigned char pin; 200 int bar, found_mem64; 201 202 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io, 203 (u64)mem, command); 204 205 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0); 206 207 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { 208 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); 209 pci_hose_read_config_dword(hose, dev, bar, &bar_response); 210 211 if (!bar_response) 212 continue; 213 214 found_mem64 = 0; 215 216 /* Check the BAR type and set our address mask */ 217 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 218 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; 219 /* round up region base address to a multiple of size */ 220 io = ((io - 1) | (bar_size - 1)) + 1; 221 bar_value = io; 222 /* compute new region base address */ 223 io = io + bar_size; 224 } else { 225 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 226 PCI_BASE_ADDRESS_MEM_TYPE_64) { 227 u32 bar_response_upper; 228 u64 bar64; 229 pci_hose_write_config_dword(hose, dev, bar + 4, 230 0xffffffff); 231 pci_hose_read_config_dword(hose, dev, bar + 4, 232 &bar_response_upper); 233 234 bar64 = ((u64)bar_response_upper << 32) | bar_response; 235 236 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; 237 found_mem64 = 1; 238 } else { 239 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); 240 } 241 242 /* round up region base address to multiple of size */ 243 mem = ((mem - 1) | (bar_size - 1)) + 1; 244 bar_value = mem; 245 /* compute new region base address */ 246 mem = mem + bar_size; 247 } 248 249 /* Write it out and update our limit */ 250 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value); 251 252 if (found_mem64) { 253 bar += 4; 254 #ifdef CONFIG_SYS_PCI_64BIT 255 pci_hose_write_config_dword(hose, dev, bar, 256 (u32)(bar_value >> 32)); 257 #else 258 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); 259 #endif 260 } 261 } 262 263 /* Configure Cache Line Size Register */ 264 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 265 266 /* Configure Latency Timer */ 267 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 268 269 /* Disable interrupt line, if device says it wants to use interrupts */ 270 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); 271 if (pin != 0) { 272 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff); 273 } 274 275 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command); 276 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 277 (old_command & 0xffff0000) | command); 278 279 return 0; 280 } 281 282 /* 283 * 284 */ 285 286 struct pci_config_table *pci_find_config(struct pci_controller *hose, 287 unsigned short class, 288 unsigned int vendor, 289 unsigned int device, 290 unsigned int bus, 291 unsigned int dev, 292 unsigned int func) 293 { 294 struct pci_config_table *table; 295 296 for (table = hose->config_table; table && table->vendor; table++) { 297 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && 298 (table->device == PCI_ANY_ID || table->device == device) && 299 (table->class == PCI_ANY_ID || table->class == class) && 300 (table->bus == PCI_ANY_ID || table->bus == bus) && 301 (table->dev == PCI_ANY_ID || table->dev == dev) && 302 (table->func == PCI_ANY_ID || table->func == func)) { 303 return table; 304 } 305 } 306 307 return NULL; 308 } 309 310 void pci_cfgfunc_config_device(struct pci_controller *hose, 311 pci_dev_t dev, 312 struct pci_config_table *entry) 313 { 314 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], 315 entry->priv[2]); 316 } 317 318 void pci_cfgfunc_do_nothing(struct pci_controller *hose, 319 pci_dev_t dev, struct pci_config_table *entry) 320 { 321 } 322 323 /* 324 * HJF: Changed this to return int. I think this is required 325 * to get the correct result when scanning bridges 326 */ 327 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 328 329 #ifdef CONFIG_PCI_SCAN_SHOW 330 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) 331 { 332 if (dev == PCI_BDF(hose->first_busno, 0, 0)) 333 return 0; 334 335 return 1; 336 } 337 #endif /* CONFIG_PCI_SCAN_SHOW */ 338 339 int pci_hose_scan_bus(struct pci_controller *hose, int bus) 340 { 341 unsigned int sub_bus, found_multi = 0; 342 unsigned short vendor, device, class; 343 unsigned char header_type; 344 #ifndef CONFIG_PCI_PNP 345 struct pci_config_table *cfg; 346 #endif 347 pci_dev_t dev; 348 #ifdef CONFIG_PCI_SCAN_SHOW 349 static int indent = 0; 350 #endif 351 352 sub_bus = bus; 353 354 for (dev = PCI_BDF(bus,0,0); 355 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, 356 PCI_MAX_PCI_FUNCTIONS - 1); 357 dev += PCI_BDF(0, 0, 1)) { 358 359 if (pci_skip_dev(hose, dev)) 360 continue; 361 362 if (PCI_FUNC(dev) && !found_multi) 363 continue; 364 365 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); 366 367 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); 368 369 if (vendor == 0xffff || vendor == 0x0000) 370 continue; 371 372 if (!PCI_FUNC(dev)) 373 found_multi = header_type & 0x80; 374 375 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n", 376 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 377 378 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); 379 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 380 381 #ifdef CONFIG_PCI_FIXUP_DEV 382 board_pci_fixup_dev(hose, dev, vendor, device, class); 383 #endif 384 385 #ifdef CONFIG_PCI_SCAN_SHOW 386 indent++; 387 388 /* Print leading space, including bus indentation */ 389 printf("%*c", indent + 1, ' '); 390 391 if (pci_print_dev(hose, dev)) { 392 printf("%02x:%02x.%-*x - %04x:%04x - %s\n", 393 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev), 394 vendor, device, pci_class_str(class >> 8)); 395 } 396 #endif 397 398 #ifdef CONFIG_PCI_PNP 399 sub_bus = max((unsigned int)pciauto_config_device(hose, dev), 400 sub_bus); 401 #else 402 cfg = pci_find_config(hose, class, vendor, device, 403 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 404 if (cfg) { 405 cfg->config_device(hose, dev, cfg); 406 sub_bus = max(sub_bus, 407 (unsigned int)hose->current_busno); 408 } 409 #endif 410 411 #ifdef CONFIG_PCI_SCAN_SHOW 412 indent--; 413 #endif 414 415 if (hose->fixup_irq) 416 hose->fixup_irq(hose, dev); 417 } 418 419 return sub_bus; 420 } 421 422 int pci_hose_scan(struct pci_controller *hose) 423 { 424 #if defined(CONFIG_PCI_BOOTDELAY) 425 char *s; 426 int i; 427 428 if (!gd->pcidelay_done) { 429 /* wait "pcidelay" ms (if defined)... */ 430 s = getenv("pcidelay"); 431 if (s) { 432 int val = simple_strtoul(s, NULL, 10); 433 for (i = 0; i < val; i++) 434 udelay(1000); 435 } 436 gd->pcidelay_done = 1; 437 } 438 #endif /* CONFIG_PCI_BOOTDELAY */ 439 440 #ifdef CONFIG_PCI_SCAN_SHOW 441 puts("PCI:\n"); 442 #endif 443 444 /* 445 * Start scan at current_busno. 446 * PCIe will start scan at first_busno+1. 447 */ 448 /* For legacy support, ensure current >= first */ 449 if (hose->first_busno > hose->current_busno) 450 hose->current_busno = hose->first_busno; 451 #ifdef CONFIG_PCI_PNP 452 pciauto_config_init(hose); 453 #endif 454 return pci_hose_scan_bus(hose, hose->current_busno); 455 } 456 457 void pci_init(void) 458 { 459 hose_head = NULL; 460 461 /* now call board specific pci_init()... */ 462 pci_init_board(); 463 } 464 465 /* Returns the address of the requested capability structure within the 466 * device's PCI configuration space or 0 in case the device does not 467 * support it. 468 * */ 469 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 470 int cap) 471 { 472 int pos; 473 u8 hdr_type; 474 475 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); 476 477 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); 478 479 if (pos) 480 pos = pci_find_cap(hose, dev, pos, cap); 481 482 return pos; 483 } 484 485 /* Find the header pointer to the Capabilities*/ 486 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 487 u8 hdr_type) 488 { 489 u16 status; 490 491 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); 492 493 if (!(status & PCI_STATUS_CAP_LIST)) 494 return 0; 495 496 switch (hdr_type) { 497 case PCI_HEADER_TYPE_NORMAL: 498 case PCI_HEADER_TYPE_BRIDGE: 499 return PCI_CAPABILITY_LIST; 500 case PCI_HEADER_TYPE_CARDBUS: 501 return PCI_CB_CAPABILITY_LIST; 502 default: 503 return 0; 504 } 505 } 506 507 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) 508 { 509 int ttl = PCI_FIND_CAP_TTL; 510 u8 id; 511 u8 next_pos; 512 513 while (ttl--) { 514 pci_hose_read_config_byte(hose, dev, pos, &next_pos); 515 if (next_pos < CAP_START_POS) 516 break; 517 next_pos &= ~3; 518 pos = (int) next_pos; 519 pci_hose_read_config_byte(hose, dev, 520 pos + PCI_CAP_LIST_ID, &id); 521 if (id == 0xff) 522 break; 523 if (id == cap) 524 return pos; 525 pos += PCI_CAP_LIST_NEXT; 526 } 527 return 0; 528 } 529