1 /* 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3 * Andreas Heppel <aheppel@sysgo.de> 4 * 5 * (C) Copyright 2002, 2003 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 /* 28 * PCI routines 29 */ 30 31 #include <common.h> 32 33 #include <command.h> 34 #include <asm/processor.h> 35 #include <asm/io.h> 36 #include <pci.h> 37 38 #define PCI_HOSE_OP(rw, size, type) \ 39 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ 40 pci_dev_t dev, \ 41 int offset, type value) \ 42 { \ 43 return hose->rw##_##size(hose, dev, offset, value); \ 44 } 45 46 PCI_HOSE_OP(read, byte, u8 *) 47 PCI_HOSE_OP(read, word, u16 *) 48 PCI_HOSE_OP(read, dword, u32 *) 49 PCI_HOSE_OP(write, byte, u8) 50 PCI_HOSE_OP(write, word, u16) 51 PCI_HOSE_OP(write, dword, u32) 52 53 #ifndef CONFIG_IXP425 54 #define PCI_OP(rw, size, type, error_code) \ 55 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ 56 { \ 57 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ 58 \ 59 if (!hose) \ 60 { \ 61 error_code; \ 62 return -1; \ 63 } \ 64 \ 65 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ 66 } 67 68 PCI_OP(read, byte, u8 *, *value = 0xff) 69 PCI_OP(read, word, u16 *, *value = 0xffff) 70 PCI_OP(read, dword, u32 *, *value = 0xffffffff) 71 PCI_OP(write, byte, u8, ) 72 PCI_OP(write, word, u16, ) 73 PCI_OP(write, dword, u32, ) 74 #endif /* CONFIG_IXP425 */ 75 76 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ 77 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ 78 pci_dev_t dev, \ 79 int offset, type val) \ 80 { \ 81 u32 val32; \ 82 \ 83 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ 84 *val = -1; \ 85 return -1; \ 86 } \ 87 \ 88 *val = (val32 >> ((offset & (int)off_mask) * 8)); \ 89 \ 90 return 0; \ 91 } 92 93 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ 94 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\ 95 pci_dev_t dev, \ 96 int offset, type val) \ 97 { \ 98 u32 val32, mask, ldata, shift; \ 99 \ 100 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ 101 return -1; \ 102 \ 103 shift = ((offset & (int)off_mask) * 8); \ 104 ldata = (((unsigned long)val) & val_mask) << shift; \ 105 mask = val_mask << shift; \ 106 val32 = (val32 & ~mask) | ldata; \ 107 \ 108 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\ 109 return -1; \ 110 \ 111 return 0; \ 112 } 113 114 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) 115 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) 116 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) 117 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) 118 119 /* 120 * 121 */ 122 123 static struct pci_controller* hose_head = NULL; 124 125 void pci_register_hose(struct pci_controller* hose) 126 { 127 struct pci_controller **phose = &hose_head; 128 129 while(*phose) 130 phose = &(*phose)->next; 131 132 hose->next = NULL; 133 134 *phose = hose; 135 } 136 137 struct pci_controller *pci_bus_to_hose (int bus) 138 { 139 struct pci_controller *hose; 140 141 for (hose = hose_head; hose; hose = hose->next) 142 if (bus >= hose->first_busno && bus <= hose->last_busno) 143 return hose; 144 145 printf("pci_bus_to_hose() failed\n"); 146 return NULL; 147 } 148 149 #ifndef CONFIG_IXP425 150 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) 151 { 152 struct pci_controller * hose; 153 u16 vendor, device; 154 u8 header_type; 155 pci_dev_t bdf; 156 int i, bus, found_multi = 0; 157 158 for (hose = hose_head; hose; hose = hose->next) 159 { 160 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 161 for (bus = hose->last_busno; bus >= hose->first_busno; bus--) 162 #else 163 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) 164 #endif 165 for (bdf = PCI_BDF(bus,0,0); 166 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX) 167 bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); 168 #else 169 bdf < PCI_BDF(bus+1,0,0); 170 #endif 171 bdf += PCI_BDF(0,0,1)) 172 { 173 if (!PCI_FUNC(bdf)) { 174 pci_read_config_byte(bdf, 175 PCI_HEADER_TYPE, 176 &header_type); 177 178 found_multi = header_type & 0x80; 179 } else { 180 if (!found_multi) 181 continue; 182 } 183 184 pci_read_config_word(bdf, 185 PCI_VENDOR_ID, 186 &vendor); 187 pci_read_config_word(bdf, 188 PCI_DEVICE_ID, 189 &device); 190 191 for (i=0; ids[i].vendor != 0; i++) 192 if (vendor == ids[i].vendor && 193 device == ids[i].device) 194 { 195 if (index <= 0) 196 return bdf; 197 198 index--; 199 } 200 } 201 } 202 203 return (-1); 204 } 205 #endif /* CONFIG_IXP425 */ 206 207 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) 208 { 209 static struct pci_device_id ids[2] = {{}, {0, 0}}; 210 211 ids[0].vendor = vendor; 212 ids[0].device = device; 213 214 return pci_find_devices(ids, index); 215 } 216 217 /* 218 * 219 */ 220 221 unsigned long pci_hose_phys_to_bus (struct pci_controller *hose, 222 phys_addr_t phys_addr, 223 unsigned long flags) 224 { 225 struct pci_region *res; 226 unsigned long bus_addr; 227 int i; 228 229 if (!hose) { 230 printf ("pci_hose_phys_to_bus: %s\n", "invalid hose"); 231 goto Done; 232 } 233 234 for (i = 0; i < hose->region_count; i++) { 235 res = &hose->regions[i]; 236 237 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) 238 continue; 239 240 bus_addr = phys_addr - res->phys_start + res->bus_start; 241 242 if (bus_addr >= res->bus_start && 243 bus_addr < res->bus_start + res->size) { 244 return bus_addr; 245 } 246 } 247 248 printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address"); 249 250 Done: 251 return 0; 252 } 253 254 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 255 unsigned long bus_addr, 256 unsigned long flags) 257 { 258 struct pci_region *res; 259 int i; 260 261 if (!hose) { 262 printf ("pci_hose_bus_to_phys: %s\n", "invalid hose"); 263 goto Done; 264 } 265 266 for (i = 0; i < hose->region_count; i++) { 267 res = &hose->regions[i]; 268 269 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) 270 continue; 271 272 if (bus_addr >= res->bus_start && 273 bus_addr < res->bus_start + res->size) { 274 return bus_addr - res->bus_start + res->phys_start; 275 } 276 } 277 278 printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address"); 279 280 Done: 281 return 0; 282 } 283 284 /* 285 * 286 */ 287 288 int pci_hose_config_device(struct pci_controller *hose, 289 pci_dev_t dev, 290 unsigned long io, 291 unsigned long mem, 292 unsigned long command) 293 { 294 unsigned int bar_response, bar_size, bar_value, old_command; 295 unsigned char pin; 296 int bar, found_mem64; 297 298 debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n", 299 io, mem, command); 300 301 pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0); 302 303 for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) { 304 pci_hose_write_config_dword (hose, dev, bar, 0xffffffff); 305 pci_hose_read_config_dword (hose, dev, bar, &bar_response); 306 307 if (!bar_response) 308 continue; 309 310 found_mem64 = 0; 311 312 /* Check the BAR type and set our address mask */ 313 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 314 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; 315 /* round up region base address to a multiple of size */ 316 io = ((io - 1) | (bar_size - 1)) + 1; 317 bar_value = io; 318 /* compute new region base address */ 319 io = io + bar_size; 320 } else { 321 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 322 PCI_BASE_ADDRESS_MEM_TYPE_64) 323 found_mem64 = 1; 324 325 bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1; 326 327 /* round up region base address to multiple of size */ 328 mem = ((mem - 1) | (bar_size - 1)) + 1; 329 bar_value = mem; 330 /* compute new region base address */ 331 mem = mem + bar_size; 332 } 333 334 /* Write it out and update our limit */ 335 pci_hose_write_config_dword (hose, dev, bar, bar_value); 336 337 if (found_mem64) { 338 bar += 4; 339 pci_hose_write_config_dword (hose, dev, bar, 0x00000000); 340 } 341 } 342 343 /* Configure Cache Line Size Register */ 344 pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 345 346 /* Configure Latency Timer */ 347 pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80); 348 349 /* Disable interrupt line, if device says it wants to use interrupts */ 350 pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin); 351 if (pin != 0) { 352 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff); 353 } 354 355 pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command); 356 pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 357 (old_command & 0xffff0000) | command); 358 359 return 0; 360 } 361 362 /* 363 * 364 */ 365 366 struct pci_config_table *pci_find_config(struct pci_controller *hose, 367 unsigned short class, 368 unsigned int vendor, 369 unsigned int device, 370 unsigned int bus, 371 unsigned int dev, 372 unsigned int func) 373 { 374 struct pci_config_table *table; 375 376 for (table = hose->config_table; table && table->vendor; table++) { 377 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && 378 (table->device == PCI_ANY_ID || table->device == device) && 379 (table->class == PCI_ANY_ID || table->class == class) && 380 (table->bus == PCI_ANY_ID || table->bus == bus) && 381 (table->dev == PCI_ANY_ID || table->dev == dev) && 382 (table->func == PCI_ANY_ID || table->func == func)) { 383 return table; 384 } 385 } 386 387 return NULL; 388 } 389 390 void pci_cfgfunc_config_device(struct pci_controller *hose, 391 pci_dev_t dev, 392 struct pci_config_table *entry) 393 { 394 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]); 395 } 396 397 void pci_cfgfunc_do_nothing(struct pci_controller *hose, 398 pci_dev_t dev, struct pci_config_table *entry) 399 { 400 } 401 402 /* 403 * 404 */ 405 406 /* HJF: Changed this to return int. I think this is required 407 * to get the correct result when scanning bridges 408 */ 409 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 410 extern void pciauto_config_init(struct pci_controller *hose); 411 412 int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) 413 { 414 /* 415 * Check if pci device should be skipped in configuration 416 */ 417 if (dev == PCI_BDF(hose->first_busno, 0, 0)) { 418 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */ 419 /* 420 * Only skip configuration if "pciconfighost" is not set 421 */ 422 if (getenv("pciconfighost") == NULL) 423 return 1; 424 #else 425 return 1; 426 #endif 427 } 428 429 return 0; 430 } 431 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) 432 __attribute__((weak, alias("__pci_skip_dev"))); 433 434 #ifdef CONFIG_PCI_SCAN_SHOW 435 int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev) 436 { 437 if (dev == PCI_BDF(hose->first_busno, 0, 0)) 438 return 0; 439 440 return 1; 441 } 442 int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) 443 __attribute__((weak, alias("__pci_print_dev"))); 444 #endif /* CONFIG_PCI_SCAN_SHOW */ 445 446 int pci_hose_scan_bus(struct pci_controller *hose, int bus) 447 { 448 unsigned int sub_bus, found_multi=0; 449 unsigned short vendor, device, class; 450 unsigned char header_type; 451 struct pci_config_table *cfg; 452 pci_dev_t dev; 453 454 sub_bus = bus; 455 456 for (dev = PCI_BDF(bus,0,0); 457 dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); 458 dev += PCI_BDF(0,0,1)) { 459 460 if (pci_skip_dev(hose, dev)) 461 continue; 462 463 if (PCI_FUNC(dev) && !found_multi) 464 continue; 465 466 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); 467 468 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); 469 470 if (vendor != 0xffff && vendor != 0x0000) { 471 472 if (!PCI_FUNC(dev)) 473 found_multi = header_type & 0x80; 474 475 debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n", 476 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) ); 477 478 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); 479 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 480 481 cfg = pci_find_config(hose, class, vendor, device, 482 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 483 if (cfg) { 484 cfg->config_device(hose, dev, cfg); 485 sub_bus = max(sub_bus, hose->current_busno); 486 #ifdef CONFIG_PCI_PNP 487 } else { 488 int n = pciauto_config_device(hose, dev); 489 490 sub_bus = max(sub_bus, n); 491 #endif 492 } 493 if (hose->fixup_irq) 494 hose->fixup_irq(hose, dev); 495 496 #ifdef CONFIG_PCI_SCAN_SHOW 497 if (pci_print_dev(hose, dev)) { 498 unsigned char int_line; 499 500 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE, 501 &int_line); 502 printf(" %02x %02x %04x %04x %04x %02x\n", 503 PCI_BUS(dev), PCI_DEV(dev), vendor, device, class, 504 int_line); 505 } 506 #endif 507 } 508 } 509 510 return sub_bus; 511 } 512 513 int pci_hose_scan(struct pci_controller *hose) 514 { 515 /* Start scan at current_busno. 516 * PCIe will start scan at first_busno+1. 517 */ 518 /* For legacy support, ensure current>=first */ 519 if (hose->first_busno > hose->current_busno) 520 hose->current_busno = hose->first_busno; 521 #ifdef CONFIG_PCI_PNP 522 pciauto_config_init(hose); 523 #endif 524 return pci_hose_scan_bus(hose, hose->current_busno); 525 } 526 527 void pci_init(void) 528 { 529 #if defined(CONFIG_PCI_BOOTDELAY) 530 char *s; 531 int i; 532 533 /* wait "pcidelay" ms (if defined)... */ 534 s = getenv ("pcidelay"); 535 if (s) { 536 int val = simple_strtoul (s, NULL, 10); 537 for (i=0; i<val; i++) 538 udelay (1000); 539 } 540 #endif /* CONFIG_PCI_BOOTDELAY */ 541 542 /* now call board specific pci_init()... */ 543 pci_init_board(); 544 } 545