1 /* 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3 * Andreas Heppel <aheppel@sysgo.de> 4 * 5 * (C) Copyright 2002, 2003 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * Old PCI routines 13 * 14 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI 15 * and change pci-uclass.c. 16 */ 17 18 #include <common.h> 19 20 #include <command.h> 21 #include <errno.h> 22 #include <asm/processor.h> 23 #include <asm/io.h> 24 #include <pci.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #define PCI_HOSE_OP(rw, size, type) \ 29 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ 30 pci_dev_t dev, \ 31 int offset, type value) \ 32 { \ 33 return hose->rw##_##size(hose, dev, offset, value); \ 34 } 35 36 PCI_HOSE_OP(read, byte, u8 *) 37 PCI_HOSE_OP(read, word, u16 *) 38 PCI_HOSE_OP(read, dword, u32 *) 39 PCI_HOSE_OP(write, byte, u8) 40 PCI_HOSE_OP(write, word, u16) 41 PCI_HOSE_OP(write, dword, u32) 42 43 #define PCI_OP(rw, size, type, error_code) \ 44 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ 45 { \ 46 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ 47 \ 48 if (!hose) \ 49 { \ 50 error_code; \ 51 return -1; \ 52 } \ 53 \ 54 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ 55 } 56 57 PCI_OP(read, byte, u8 *, *value = 0xff) 58 PCI_OP(read, word, u16 *, *value = 0xffff) 59 PCI_OP(read, dword, u32 *, *value = 0xffffffff) 60 PCI_OP(write, byte, u8, ) 61 PCI_OP(write, word, u16, ) 62 PCI_OP(write, dword, u32, ) 63 64 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ 65 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ 66 pci_dev_t dev, \ 67 int offset, type val) \ 68 { \ 69 u32 val32; \ 70 \ 71 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ 72 *val = -1; \ 73 return -1; \ 74 } \ 75 \ 76 *val = (val32 >> ((offset & (int)off_mask) * 8)); \ 77 \ 78 return 0; \ 79 } 80 81 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ 82 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\ 83 pci_dev_t dev, \ 84 int offset, type val) \ 85 { \ 86 u32 val32, mask, ldata, shift; \ 87 \ 88 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ 89 return -1; \ 90 \ 91 shift = ((offset & (int)off_mask) * 8); \ 92 ldata = (((unsigned long)val) & val_mask) << shift; \ 93 mask = val_mask << shift; \ 94 val32 = (val32 & ~mask) | ldata; \ 95 \ 96 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\ 97 return -1; \ 98 \ 99 return 0; \ 100 } 101 102 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) 103 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) 104 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) 105 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) 106 107 /* 108 * 109 */ 110 111 static struct pci_controller* hose_head; 112 113 struct pci_controller *pci_get_hose_head(void) 114 { 115 if (gd->hose) 116 return gd->hose; 117 118 return hose_head; 119 } 120 121 void pci_register_hose(struct pci_controller* hose) 122 { 123 struct pci_controller **phose = &hose_head; 124 125 while(*phose) 126 phose = &(*phose)->next; 127 128 hose->next = NULL; 129 130 *phose = hose; 131 } 132 133 struct pci_controller *pci_bus_to_hose(int bus) 134 { 135 struct pci_controller *hose; 136 137 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 138 if (bus >= hose->first_busno && bus <= hose->last_busno) 139 return hose; 140 } 141 142 printf("pci_bus_to_hose() failed\n"); 143 return NULL; 144 } 145 146 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) 147 { 148 struct pci_controller *hose; 149 150 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 151 if (hose->cfg_addr == cfg_addr) 152 return hose; 153 } 154 155 return NULL; 156 } 157 158 int pci_last_busno(void) 159 { 160 struct pci_controller *hose = pci_get_hose_head(); 161 162 if (!hose) 163 return -1; 164 165 while (hose->next) 166 hose = hose->next; 167 168 return hose->last_busno; 169 } 170 171 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) 172 { 173 struct pci_controller * hose; 174 pci_dev_t bdf; 175 int bus; 176 177 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 178 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 179 for (bus = hose->last_busno; bus >= hose->first_busno; bus--) { 180 #else 181 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) { 182 #endif 183 bdf = pci_hose_find_devices(hose, bus, ids, &index); 184 if (bdf != -1) 185 return bdf; 186 } 187 } 188 189 return -1; 190 } 191 192 int pci_hose_config_device(struct pci_controller *hose, 193 pci_dev_t dev, 194 unsigned long io, 195 pci_addr_t mem, 196 unsigned long command) 197 { 198 u32 bar_response; 199 unsigned int old_command; 200 pci_addr_t bar_value; 201 pci_size_t bar_size; 202 unsigned char pin; 203 int bar, found_mem64; 204 205 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io, 206 (u64)mem, command); 207 208 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0); 209 210 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { 211 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); 212 pci_hose_read_config_dword(hose, dev, bar, &bar_response); 213 214 if (!bar_response) 215 continue; 216 217 found_mem64 = 0; 218 219 /* Check the BAR type and set our address mask */ 220 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 221 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; 222 /* round up region base address to a multiple of size */ 223 io = ((io - 1) | (bar_size - 1)) + 1; 224 bar_value = io; 225 /* compute new region base address */ 226 io = io + bar_size; 227 } else { 228 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 229 PCI_BASE_ADDRESS_MEM_TYPE_64) { 230 u32 bar_response_upper; 231 u64 bar64; 232 pci_hose_write_config_dword(hose, dev, bar + 4, 233 0xffffffff); 234 pci_hose_read_config_dword(hose, dev, bar + 4, 235 &bar_response_upper); 236 237 bar64 = ((u64)bar_response_upper << 32) | bar_response; 238 239 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; 240 found_mem64 = 1; 241 } else { 242 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); 243 } 244 245 /* round up region base address to multiple of size */ 246 mem = ((mem - 1) | (bar_size - 1)) + 1; 247 bar_value = mem; 248 /* compute new region base address */ 249 mem = mem + bar_size; 250 } 251 252 /* Write it out and update our limit */ 253 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value); 254 255 if (found_mem64) { 256 bar += 4; 257 #ifdef CONFIG_SYS_PCI_64BIT 258 pci_hose_write_config_dword(hose, dev, bar, 259 (u32)(bar_value >> 32)); 260 #else 261 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); 262 #endif 263 } 264 } 265 266 /* Configure Cache Line Size Register */ 267 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 268 269 /* Configure Latency Timer */ 270 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 271 272 /* Disable interrupt line, if device says it wants to use interrupts */ 273 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); 274 if (pin != 0) { 275 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 276 PCI_INTERRUPT_LINE_DISABLE); 277 } 278 279 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command); 280 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 281 (old_command & 0xffff0000) | command); 282 283 return 0; 284 } 285 286 /* 287 * 288 */ 289 290 struct pci_config_table *pci_find_config(struct pci_controller *hose, 291 unsigned short class, 292 unsigned int vendor, 293 unsigned int device, 294 unsigned int bus, 295 unsigned int dev, 296 unsigned int func) 297 { 298 struct pci_config_table *table; 299 300 for (table = hose->config_table; table && table->vendor; table++) { 301 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && 302 (table->device == PCI_ANY_ID || table->device == device) && 303 (table->class == PCI_ANY_ID || table->class == class) && 304 (table->bus == PCI_ANY_ID || table->bus == bus) && 305 (table->dev == PCI_ANY_ID || table->dev == dev) && 306 (table->func == PCI_ANY_ID || table->func == func)) { 307 return table; 308 } 309 } 310 311 return NULL; 312 } 313 314 void pci_cfgfunc_config_device(struct pci_controller *hose, 315 pci_dev_t dev, 316 struct pci_config_table *entry) 317 { 318 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], 319 entry->priv[2]); 320 } 321 322 void pci_cfgfunc_do_nothing(struct pci_controller *hose, 323 pci_dev_t dev, struct pci_config_table *entry) 324 { 325 } 326 327 /* 328 * HJF: Changed this to return int. I think this is required 329 * to get the correct result when scanning bridges 330 */ 331 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 332 333 #ifdef CONFIG_PCI_SCAN_SHOW 334 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) 335 { 336 if (dev == PCI_BDF(hose->first_busno, 0, 0)) 337 return 0; 338 339 return 1; 340 } 341 #endif /* CONFIG_PCI_SCAN_SHOW */ 342 343 int pci_hose_scan_bus(struct pci_controller *hose, int bus) 344 { 345 unsigned int sub_bus, found_multi = 0; 346 unsigned short vendor, device, class; 347 unsigned char header_type; 348 #ifndef CONFIG_PCI_PNP 349 struct pci_config_table *cfg; 350 #endif 351 pci_dev_t dev; 352 #ifdef CONFIG_PCI_SCAN_SHOW 353 static int indent = 0; 354 #endif 355 356 sub_bus = bus; 357 358 for (dev = PCI_BDF(bus,0,0); 359 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, 360 PCI_MAX_PCI_FUNCTIONS - 1); 361 dev += PCI_BDF(0, 0, 1)) { 362 363 if (pci_skip_dev(hose, dev)) 364 continue; 365 366 if (PCI_FUNC(dev) && !found_multi) 367 continue; 368 369 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); 370 371 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); 372 373 if (vendor == 0xffff || vendor == 0x0000) 374 continue; 375 376 if (!PCI_FUNC(dev)) 377 found_multi = header_type & 0x80; 378 379 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n", 380 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 381 382 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); 383 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 384 385 #ifdef CONFIG_PCI_FIXUP_DEV 386 board_pci_fixup_dev(hose, dev, vendor, device, class); 387 #endif 388 389 #ifdef CONFIG_PCI_SCAN_SHOW 390 indent++; 391 392 /* Print leading space, including bus indentation */ 393 printf("%*c", indent + 1, ' '); 394 395 if (pci_print_dev(hose, dev)) { 396 printf("%02x:%02x.%-*x - %04x:%04x - %s\n", 397 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev), 398 vendor, device, pci_class_str(class >> 8)); 399 } 400 #endif 401 402 #ifdef CONFIG_PCI_PNP 403 sub_bus = max((unsigned int)pciauto_config_device(hose, dev), 404 sub_bus); 405 #else 406 cfg = pci_find_config(hose, class, vendor, device, 407 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 408 if (cfg) { 409 cfg->config_device(hose, dev, cfg); 410 sub_bus = max(sub_bus, 411 (unsigned int)hose->current_busno); 412 } 413 #endif 414 415 #ifdef CONFIG_PCI_SCAN_SHOW 416 indent--; 417 #endif 418 419 if (hose->fixup_irq) 420 hose->fixup_irq(hose, dev); 421 } 422 423 return sub_bus; 424 } 425 426 int pci_hose_scan(struct pci_controller *hose) 427 { 428 #if defined(CONFIG_PCI_BOOTDELAY) 429 char *s; 430 int i; 431 432 if (!gd->pcidelay_done) { 433 /* wait "pcidelay" ms (if defined)... */ 434 s = getenv("pcidelay"); 435 if (s) { 436 int val = simple_strtoul(s, NULL, 10); 437 for (i = 0; i < val; i++) 438 udelay(1000); 439 } 440 gd->pcidelay_done = 1; 441 } 442 #endif /* CONFIG_PCI_BOOTDELAY */ 443 444 #ifdef CONFIG_PCI_SCAN_SHOW 445 puts("PCI:\n"); 446 #endif 447 448 /* 449 * Start scan at current_busno. 450 * PCIe will start scan at first_busno+1. 451 */ 452 /* For legacy support, ensure current >= first */ 453 if (hose->first_busno > hose->current_busno) 454 hose->current_busno = hose->first_busno; 455 #ifdef CONFIG_PCI_PNP 456 pciauto_config_init(hose); 457 #endif 458 return pci_hose_scan_bus(hose, hose->current_busno); 459 } 460 461 void pci_init(void) 462 { 463 hose_head = NULL; 464 465 /* now call board specific pci_init()... */ 466 pci_init_board(); 467 } 468 469 /* Returns the address of the requested capability structure within the 470 * device's PCI configuration space or 0 in case the device does not 471 * support it. 472 * */ 473 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 474 int cap) 475 { 476 int pos; 477 u8 hdr_type; 478 479 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); 480 481 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); 482 483 if (pos) 484 pos = pci_find_cap(hose, dev, pos, cap); 485 486 return pos; 487 } 488 489 /* Find the header pointer to the Capabilities*/ 490 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 491 u8 hdr_type) 492 { 493 u16 status; 494 495 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); 496 497 if (!(status & PCI_STATUS_CAP_LIST)) 498 return 0; 499 500 switch (hdr_type) { 501 case PCI_HEADER_TYPE_NORMAL: 502 case PCI_HEADER_TYPE_BRIDGE: 503 return PCI_CAPABILITY_LIST; 504 case PCI_HEADER_TYPE_CARDBUS: 505 return PCI_CB_CAPABILITY_LIST; 506 default: 507 return 0; 508 } 509 } 510 511 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) 512 { 513 int ttl = PCI_FIND_CAP_TTL; 514 u8 id; 515 u8 next_pos; 516 517 while (ttl--) { 518 pci_hose_read_config_byte(hose, dev, pos, &next_pos); 519 if (next_pos < CAP_START_POS) 520 break; 521 next_pos &= ~3; 522 pos = (int) next_pos; 523 pci_hose_read_config_byte(hose, dev, 524 pos + PCI_CAP_LIST_ID, &id); 525 if (id == 0xff) 526 break; 527 if (id == cap) 528 return pos; 529 pos += PCI_CAP_LIST_NEXT; 530 } 531 return 0; 532 } 533 534 /** 535 * pci_find_next_ext_capability - Find an extended capability 536 * 537 * Returns the address of the next matching extended capability structure 538 * within the device's PCI configuration space or 0 if the device does 539 * not support it. Some capabilities can occur several times, e.g., the 540 * vendor-specific capability, and this provides a way to find them all. 541 */ 542 int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev, 543 int start, int cap) 544 { 545 u32 header; 546 int ttl, pos = PCI_CFG_SPACE_SIZE; 547 548 /* minimum 8 bytes per capability */ 549 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 550 551 if (start) 552 pos = start; 553 554 pci_hose_read_config_dword(hose, dev, pos, &header); 555 if (header == 0xffffffff || header == 0) 556 return 0; 557 558 while (ttl-- > 0) { 559 if (PCI_EXT_CAP_ID(header) == cap && pos != start) 560 return pos; 561 562 pos = PCI_EXT_CAP_NEXT(header); 563 if (pos < PCI_CFG_SPACE_SIZE) 564 break; 565 566 pci_hose_read_config_dword(hose, dev, pos, &header); 567 if (header == 0xffffffff || header == 0) 568 break; 569 } 570 571 return 0; 572 } 573 574 /** 575 * pci_hose_find_ext_capability - Find an extended capability 576 * 577 * Returns the address of the requested extended capability structure 578 * within the device's PCI configuration space or 0 if the device does 579 * not support it. 580 */ 581 int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev, 582 int cap) 583 { 584 return pci_find_next_ext_capability(hose, dev, 0, cap); 585 } 586