1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Andreas Heppel <aheppel@sysgo.de> 5 * 6 * (C) Copyright 2002, 2003 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 */ 9 10 /* 11 * Old PCI routines 12 * 13 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI 14 * and change pci-uclass.c. 15 */ 16 17 #include <common.h> 18 19 #include <command.h> 20 #include <errno.h> 21 #include <asm/processor.h> 22 #include <asm/io.h> 23 #include <pci.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define PCI_HOSE_OP(rw, size, type) \ 28 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ 29 pci_dev_t dev, \ 30 int offset, type value) \ 31 { \ 32 return hose->rw##_##size(hose, dev, offset, value); \ 33 } 34 35 PCI_HOSE_OP(read, byte, u8 *) 36 PCI_HOSE_OP(read, word, u16 *) 37 PCI_HOSE_OP(read, dword, u32 *) 38 PCI_HOSE_OP(write, byte, u8) 39 PCI_HOSE_OP(write, word, u16) 40 PCI_HOSE_OP(write, dword, u32) 41 42 #define PCI_OP(rw, size, type, error_code) \ 43 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ 44 { \ 45 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ 46 \ 47 if (!hose) \ 48 { \ 49 error_code; \ 50 return -1; \ 51 } \ 52 \ 53 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ 54 } 55 56 PCI_OP(read, byte, u8 *, *value = 0xff) 57 PCI_OP(read, word, u16 *, *value = 0xffff) 58 PCI_OP(read, dword, u32 *, *value = 0xffffffff) 59 PCI_OP(write, byte, u8, ) 60 PCI_OP(write, word, u16, ) 61 PCI_OP(write, dword, u32, ) 62 63 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ 64 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ 65 pci_dev_t dev, \ 66 int offset, type val) \ 67 { \ 68 u32 val32; \ 69 \ 70 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ 71 *val = -1; \ 72 return -1; \ 73 } \ 74 \ 75 *val = (val32 >> ((offset & (int)off_mask) * 8)); \ 76 \ 77 return 0; \ 78 } 79 80 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ 81 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\ 82 pci_dev_t dev, \ 83 int offset, type val) \ 84 { \ 85 u32 val32, mask, ldata, shift; \ 86 \ 87 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ 88 return -1; \ 89 \ 90 shift = ((offset & (int)off_mask) * 8); \ 91 ldata = (((unsigned long)val) & val_mask) << shift; \ 92 mask = val_mask << shift; \ 93 val32 = (val32 & ~mask) | ldata; \ 94 \ 95 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\ 96 return -1; \ 97 \ 98 return 0; \ 99 } 100 101 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) 102 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) 103 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) 104 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) 105 106 /* 107 * 108 */ 109 110 static struct pci_controller* hose_head; 111 112 struct pci_controller *pci_get_hose_head(void) 113 { 114 if (gd->hose) 115 return gd->hose; 116 117 return hose_head; 118 } 119 120 void pci_register_hose(struct pci_controller* hose) 121 { 122 struct pci_controller **phose = &hose_head; 123 124 while(*phose) 125 phose = &(*phose)->next; 126 127 hose->next = NULL; 128 129 *phose = hose; 130 } 131 132 struct pci_controller *pci_bus_to_hose(int bus) 133 { 134 struct pci_controller *hose; 135 136 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 137 if (bus >= hose->first_busno && bus <= hose->last_busno) 138 return hose; 139 } 140 141 printf("pci_bus_to_hose() failed\n"); 142 return NULL; 143 } 144 145 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) 146 { 147 struct pci_controller *hose; 148 149 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 150 if (hose->cfg_addr == cfg_addr) 151 return hose; 152 } 153 154 return NULL; 155 } 156 157 int pci_last_busno(void) 158 { 159 struct pci_controller *hose = pci_get_hose_head(); 160 161 if (!hose) 162 return -1; 163 164 while (hose->next) 165 hose = hose->next; 166 167 return hose->last_busno; 168 } 169 170 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) 171 { 172 struct pci_controller * hose; 173 pci_dev_t bdf; 174 int bus; 175 176 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 177 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) { 178 bdf = pci_hose_find_devices(hose, bus, ids, &index); 179 if (bdf != -1) 180 return bdf; 181 } 182 } 183 184 return -1; 185 } 186 187 static int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev, 188 ulong io, pci_addr_t mem, ulong command) 189 { 190 u32 bar_response; 191 unsigned int old_command; 192 pci_addr_t bar_value; 193 pci_size_t bar_size; 194 unsigned char pin; 195 int bar, found_mem64; 196 197 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io, 198 (u64)mem, command); 199 200 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0); 201 202 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { 203 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); 204 pci_hose_read_config_dword(hose, dev, bar, &bar_response); 205 206 if (!bar_response) 207 continue; 208 209 found_mem64 = 0; 210 211 /* Check the BAR type and set our address mask */ 212 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 213 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; 214 /* round up region base address to a multiple of size */ 215 io = ((io - 1) | (bar_size - 1)) + 1; 216 bar_value = io; 217 /* compute new region base address */ 218 io = io + bar_size; 219 } else { 220 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 221 PCI_BASE_ADDRESS_MEM_TYPE_64) { 222 u32 bar_response_upper; 223 u64 bar64; 224 pci_hose_write_config_dword(hose, dev, bar + 4, 225 0xffffffff); 226 pci_hose_read_config_dword(hose, dev, bar + 4, 227 &bar_response_upper); 228 229 bar64 = ((u64)bar_response_upper << 32) | bar_response; 230 231 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; 232 found_mem64 = 1; 233 } else { 234 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); 235 } 236 237 /* round up region base address to multiple of size */ 238 mem = ((mem - 1) | (bar_size - 1)) + 1; 239 bar_value = mem; 240 /* compute new region base address */ 241 mem = mem + bar_size; 242 } 243 244 /* Write it out and update our limit */ 245 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value); 246 247 if (found_mem64) { 248 bar += 4; 249 #ifdef CONFIG_SYS_PCI_64BIT 250 pci_hose_write_config_dword(hose, dev, bar, 251 (u32)(bar_value >> 32)); 252 #else 253 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); 254 #endif 255 } 256 } 257 258 /* Configure Cache Line Size Register */ 259 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 260 261 /* Configure Latency Timer */ 262 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 263 264 /* Disable interrupt line, if device says it wants to use interrupts */ 265 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); 266 if (pin != 0) { 267 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 268 PCI_INTERRUPT_LINE_DISABLE); 269 } 270 271 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command); 272 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 273 (old_command & 0xffff0000) | command); 274 275 return 0; 276 } 277 278 /* 279 * 280 */ 281 282 struct pci_config_table *pci_find_config(struct pci_controller *hose, 283 unsigned short class, 284 unsigned int vendor, 285 unsigned int device, 286 unsigned int bus, 287 unsigned int dev, 288 unsigned int func) 289 { 290 struct pci_config_table *table; 291 292 for (table = hose->config_table; table && table->vendor; table++) { 293 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && 294 (table->device == PCI_ANY_ID || table->device == device) && 295 (table->class == PCI_ANY_ID || table->class == class) && 296 (table->bus == PCI_ANY_ID || table->bus == bus) && 297 (table->dev == PCI_ANY_ID || table->dev == dev) && 298 (table->func == PCI_ANY_ID || table->func == func)) { 299 return table; 300 } 301 } 302 303 return NULL; 304 } 305 306 void pci_cfgfunc_config_device(struct pci_controller *hose, 307 pci_dev_t dev, 308 struct pci_config_table *entry) 309 { 310 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], 311 entry->priv[2]); 312 } 313 314 void pci_cfgfunc_do_nothing(struct pci_controller *hose, 315 pci_dev_t dev, struct pci_config_table *entry) 316 { 317 } 318 319 /* 320 * HJF: Changed this to return int. I think this is required 321 * to get the correct result when scanning bridges 322 */ 323 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 324 325 #ifdef CONFIG_PCI_SCAN_SHOW 326 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) 327 { 328 if (dev == PCI_BDF(hose->first_busno, 0, 0)) 329 return 0; 330 331 return 1; 332 } 333 #endif /* CONFIG_PCI_SCAN_SHOW */ 334 335 int pci_hose_scan_bus(struct pci_controller *hose, int bus) 336 { 337 unsigned int sub_bus, found_multi = 0; 338 unsigned short vendor, device, class; 339 unsigned char header_type; 340 #ifndef CONFIG_PCI_PNP 341 struct pci_config_table *cfg; 342 #endif 343 pci_dev_t dev; 344 #ifdef CONFIG_PCI_SCAN_SHOW 345 static int indent = 0; 346 #endif 347 348 sub_bus = bus; 349 350 for (dev = PCI_BDF(bus,0,0); 351 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, 352 PCI_MAX_PCI_FUNCTIONS - 1); 353 dev += PCI_BDF(0, 0, 1)) { 354 355 if (pci_skip_dev(hose, dev)) 356 continue; 357 358 if (PCI_FUNC(dev) && !found_multi) 359 continue; 360 361 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); 362 363 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); 364 365 if (vendor == 0xffff || vendor == 0x0000) 366 continue; 367 368 if (!PCI_FUNC(dev)) 369 found_multi = header_type & 0x80; 370 371 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n", 372 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 373 374 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); 375 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 376 377 #ifdef CONFIG_PCI_FIXUP_DEV 378 board_pci_fixup_dev(hose, dev, vendor, device, class); 379 #endif 380 381 #ifdef CONFIG_PCI_SCAN_SHOW 382 indent++; 383 384 /* Print leading space, including bus indentation */ 385 printf("%*c", indent + 1, ' '); 386 387 if (pci_print_dev(hose, dev)) { 388 printf("%02x:%02x.%-*x - %04x:%04x - %s\n", 389 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev), 390 vendor, device, pci_class_str(class >> 8)); 391 } 392 #endif 393 394 #ifdef CONFIG_PCI_PNP 395 sub_bus = max((unsigned int)pciauto_config_device(hose, dev), 396 sub_bus); 397 #else 398 cfg = pci_find_config(hose, class, vendor, device, 399 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 400 if (cfg) { 401 cfg->config_device(hose, dev, cfg); 402 sub_bus = max(sub_bus, 403 (unsigned int)hose->current_busno); 404 } 405 #endif 406 407 #ifdef CONFIG_PCI_SCAN_SHOW 408 indent--; 409 #endif 410 411 if (hose->fixup_irq) 412 hose->fixup_irq(hose, dev); 413 } 414 415 return sub_bus; 416 } 417 418 int pci_hose_scan(struct pci_controller *hose) 419 { 420 #if defined(CONFIG_PCI_BOOTDELAY) 421 char *s; 422 int i; 423 424 if (!gd->pcidelay_done) { 425 /* wait "pcidelay" ms (if defined)... */ 426 s = env_get("pcidelay"); 427 if (s) { 428 int val = simple_strtoul(s, NULL, 10); 429 for (i = 0; i < val; i++) 430 udelay(1000); 431 } 432 gd->pcidelay_done = 1; 433 } 434 #endif /* CONFIG_PCI_BOOTDELAY */ 435 436 #ifdef CONFIG_PCI_SCAN_SHOW 437 puts("PCI:\n"); 438 #endif 439 440 /* 441 * Start scan at current_busno. 442 * PCIe will start scan at first_busno+1. 443 */ 444 /* For legacy support, ensure current >= first */ 445 if (hose->first_busno > hose->current_busno) 446 hose->current_busno = hose->first_busno; 447 #ifdef CONFIG_PCI_PNP 448 pciauto_config_init(hose); 449 #endif 450 return pci_hose_scan_bus(hose, hose->current_busno); 451 } 452 453 void pci_init(void) 454 { 455 hose_head = NULL; 456 457 /* allow env to disable pci init/enum */ 458 if (env_get("pcidisable") != NULL) 459 return; 460 461 /* now call board specific pci_init()... */ 462 pci_init_board(); 463 } 464 465 /* Returns the address of the requested capability structure within the 466 * device's PCI configuration space or 0 in case the device does not 467 * support it. 468 * */ 469 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 470 int cap) 471 { 472 int pos; 473 u8 hdr_type; 474 475 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); 476 477 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); 478 479 if (pos) 480 pos = pci_find_cap(hose, dev, pos, cap); 481 482 return pos; 483 } 484 485 /* Find the header pointer to the Capabilities*/ 486 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 487 u8 hdr_type) 488 { 489 u16 status; 490 491 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); 492 493 if (!(status & PCI_STATUS_CAP_LIST)) 494 return 0; 495 496 switch (hdr_type) { 497 case PCI_HEADER_TYPE_NORMAL: 498 case PCI_HEADER_TYPE_BRIDGE: 499 return PCI_CAPABILITY_LIST; 500 case PCI_HEADER_TYPE_CARDBUS: 501 return PCI_CB_CAPABILITY_LIST; 502 default: 503 return 0; 504 } 505 } 506 507 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) 508 { 509 int ttl = PCI_FIND_CAP_TTL; 510 u8 id; 511 u8 next_pos; 512 513 while (ttl--) { 514 pci_hose_read_config_byte(hose, dev, pos, &next_pos); 515 if (next_pos < CAP_START_POS) 516 break; 517 next_pos &= ~3; 518 pos = (int) next_pos; 519 pci_hose_read_config_byte(hose, dev, 520 pos + PCI_CAP_LIST_ID, &id); 521 if (id == 0xff) 522 break; 523 if (id == cap) 524 return pos; 525 pos += PCI_CAP_LIST_NEXT; 526 } 527 return 0; 528 } 529 530 /** 531 * pci_find_next_ext_capability - Find an extended capability 532 * 533 * Returns the address of the next matching extended capability structure 534 * within the device's PCI configuration space or 0 if the device does 535 * not support it. Some capabilities can occur several times, e.g., the 536 * vendor-specific capability, and this provides a way to find them all. 537 */ 538 int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev, 539 int start, int cap) 540 { 541 u32 header; 542 int ttl, pos = PCI_CFG_SPACE_SIZE; 543 544 /* minimum 8 bytes per capability */ 545 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 546 547 if (start) 548 pos = start; 549 550 pci_hose_read_config_dword(hose, dev, pos, &header); 551 if (header == 0xffffffff || header == 0) 552 return 0; 553 554 while (ttl-- > 0) { 555 if (PCI_EXT_CAP_ID(header) == cap && pos != start) 556 return pos; 557 558 pos = PCI_EXT_CAP_NEXT(header); 559 if (pos < PCI_CFG_SPACE_SIZE) 560 break; 561 562 pci_hose_read_config_dword(hose, dev, pos, &header); 563 if (header == 0xffffffff || header == 0) 564 break; 565 } 566 567 return 0; 568 } 569 570 /** 571 * pci_hose_find_ext_capability - Find an extended capability 572 * 573 * Returns the address of the requested extended capability structure 574 * within the device's PCI configuration space or 0 if the device does 575 * not support it. 576 */ 577 int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev, 578 int cap) 579 { 580 return pci_find_next_ext_capability(hose, dev, 0, cap); 581 } 582