1 /* 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3 * Andreas Heppel <aheppel@sysgo.de> 4 * 5 * (C) Copyright 2002, 2003 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * PCI routines 13 */ 14 15 #include <common.h> 16 17 #include <command.h> 18 #include <errno.h> 19 #include <asm/processor.h> 20 #include <asm/io.h> 21 #include <pci.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define PCI_HOSE_OP(rw, size, type) \ 26 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ 27 pci_dev_t dev, \ 28 int offset, type value) \ 29 { \ 30 return hose->rw##_##size(hose, dev, offset, value); \ 31 } 32 33 PCI_HOSE_OP(read, byte, u8 *) 34 PCI_HOSE_OP(read, word, u16 *) 35 PCI_HOSE_OP(read, dword, u32 *) 36 PCI_HOSE_OP(write, byte, u8) 37 PCI_HOSE_OP(write, word, u16) 38 PCI_HOSE_OP(write, dword, u32) 39 40 #define PCI_OP(rw, size, type, error_code) \ 41 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ 42 { \ 43 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ 44 \ 45 if (!hose) \ 46 { \ 47 error_code; \ 48 return -1; \ 49 } \ 50 \ 51 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ 52 } 53 54 PCI_OP(read, byte, u8 *, *value = 0xff) 55 PCI_OP(read, word, u16 *, *value = 0xffff) 56 PCI_OP(read, dword, u32 *, *value = 0xffffffff) 57 PCI_OP(write, byte, u8, ) 58 PCI_OP(write, word, u16, ) 59 PCI_OP(write, dword, u32, ) 60 61 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ 62 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ 63 pci_dev_t dev, \ 64 int offset, type val) \ 65 { \ 66 u32 val32; \ 67 \ 68 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ 69 *val = -1; \ 70 return -1; \ 71 } \ 72 \ 73 *val = (val32 >> ((offset & (int)off_mask) * 8)); \ 74 \ 75 return 0; \ 76 } 77 78 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ 79 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\ 80 pci_dev_t dev, \ 81 int offset, type val) \ 82 { \ 83 u32 val32, mask, ldata, shift; \ 84 \ 85 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ 86 return -1; \ 87 \ 88 shift = ((offset & (int)off_mask) * 8); \ 89 ldata = (((unsigned long)val) & val_mask) << shift; \ 90 mask = val_mask << shift; \ 91 val32 = (val32 & ~mask) | ldata; \ 92 \ 93 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\ 94 return -1; \ 95 \ 96 return 0; \ 97 } 98 99 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) 100 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) 101 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) 102 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) 103 104 /* 105 * 106 */ 107 108 static struct pci_controller* hose_head; 109 110 struct pci_controller *pci_get_hose_head(void) 111 { 112 if (gd->hose) 113 return gd->hose; 114 115 return hose_head; 116 } 117 118 void pci_register_hose(struct pci_controller* hose) 119 { 120 struct pci_controller **phose = &hose_head; 121 122 while(*phose) 123 phose = &(*phose)->next; 124 125 hose->next = NULL; 126 127 *phose = hose; 128 } 129 130 struct pci_controller *pci_bus_to_hose(int bus) 131 { 132 struct pci_controller *hose; 133 134 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 135 if (bus >= hose->first_busno && bus <= hose->last_busno) 136 return hose; 137 } 138 139 printf("pci_bus_to_hose() failed\n"); 140 return NULL; 141 } 142 143 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) 144 { 145 struct pci_controller *hose; 146 147 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 148 if (hose->cfg_addr == cfg_addr) 149 return hose; 150 } 151 152 return NULL; 153 } 154 155 int pci_last_busno(void) 156 { 157 struct pci_controller *hose = pci_get_hose_head(); 158 159 if (!hose) 160 return -1; 161 162 while (hose->next) 163 hose = hose->next; 164 165 return hose->last_busno; 166 } 167 168 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) 169 { 170 struct pci_controller * hose; 171 pci_dev_t bdf; 172 int bus; 173 174 for (hose = pci_get_hose_head(); hose; hose = hose->next) { 175 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 176 for (bus = hose->last_busno; bus >= hose->first_busno; bus--) { 177 #else 178 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) { 179 #endif 180 bdf = pci_hose_find_devices(hose, bus, ids, &index); 181 if (bdf != -1) 182 return bdf; 183 } 184 } 185 186 return -1; 187 } 188 189 /* 190 * 191 */ 192 193 int __pci_hose_phys_to_bus(struct pci_controller *hose, 194 phys_addr_t phys_addr, 195 unsigned long flags, 196 unsigned long skip_mask, 197 pci_addr_t *ba) 198 { 199 struct pci_region *res; 200 pci_addr_t bus_addr; 201 int i; 202 203 for (i = 0; i < hose->region_count; i++) { 204 res = &hose->regions[i]; 205 206 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) 207 continue; 208 209 if (res->flags & skip_mask) 210 continue; 211 212 bus_addr = phys_addr - res->phys_start + res->bus_start; 213 214 if (bus_addr >= res->bus_start && 215 bus_addr < res->bus_start + res->size) { 216 *ba = bus_addr; 217 return 0; 218 } 219 } 220 221 return 1; 222 } 223 224 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose, 225 phys_addr_t phys_addr, 226 unsigned long flags) 227 { 228 pci_addr_t bus_addr = 0; 229 int ret; 230 231 if (!hose) { 232 puts("pci_hose_phys_to_bus: invalid hose\n"); 233 return bus_addr; 234 } 235 236 /* 237 * if PCI_REGION_MEM is set we do a two pass search with preference 238 * on matches that don't have PCI_REGION_SYS_MEMORY set 239 */ 240 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) { 241 ret = __pci_hose_phys_to_bus(hose, phys_addr, 242 flags, PCI_REGION_SYS_MEMORY, &bus_addr); 243 if (!ret) 244 return bus_addr; 245 } 246 247 ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr); 248 249 if (ret) 250 puts("pci_hose_phys_to_bus: invalid physical address\n"); 251 252 return bus_addr; 253 } 254 255 int pci_hose_config_device(struct pci_controller *hose, 256 pci_dev_t dev, 257 unsigned long io, 258 pci_addr_t mem, 259 unsigned long command) 260 { 261 u32 bar_response; 262 unsigned int old_command; 263 pci_addr_t bar_value; 264 pci_size_t bar_size; 265 unsigned char pin; 266 int bar, found_mem64; 267 268 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io, 269 (u64)mem, command); 270 271 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0); 272 273 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { 274 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); 275 pci_hose_read_config_dword(hose, dev, bar, &bar_response); 276 277 if (!bar_response) 278 continue; 279 280 found_mem64 = 0; 281 282 /* Check the BAR type and set our address mask */ 283 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 284 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; 285 /* round up region base address to a multiple of size */ 286 io = ((io - 1) | (bar_size - 1)) + 1; 287 bar_value = io; 288 /* compute new region base address */ 289 io = io + bar_size; 290 } else { 291 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 292 PCI_BASE_ADDRESS_MEM_TYPE_64) { 293 u32 bar_response_upper; 294 u64 bar64; 295 pci_hose_write_config_dword(hose, dev, bar + 4, 296 0xffffffff); 297 pci_hose_read_config_dword(hose, dev, bar + 4, 298 &bar_response_upper); 299 300 bar64 = ((u64)bar_response_upper << 32) | bar_response; 301 302 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; 303 found_mem64 = 1; 304 } else { 305 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); 306 } 307 308 /* round up region base address to multiple of size */ 309 mem = ((mem - 1) | (bar_size - 1)) + 1; 310 bar_value = mem; 311 /* compute new region base address */ 312 mem = mem + bar_size; 313 } 314 315 /* Write it out and update our limit */ 316 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value); 317 318 if (found_mem64) { 319 bar += 4; 320 #ifdef CONFIG_SYS_PCI_64BIT 321 pci_hose_write_config_dword(hose, dev, bar, 322 (u32)(bar_value >> 32)); 323 #else 324 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); 325 #endif 326 } 327 } 328 329 /* Configure Cache Line Size Register */ 330 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 331 332 /* Configure Latency Timer */ 333 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 334 335 /* Disable interrupt line, if device says it wants to use interrupts */ 336 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); 337 if (pin != 0) { 338 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff); 339 } 340 341 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command); 342 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 343 (old_command & 0xffff0000) | command); 344 345 return 0; 346 } 347 348 /* 349 * 350 */ 351 352 struct pci_config_table *pci_find_config(struct pci_controller *hose, 353 unsigned short class, 354 unsigned int vendor, 355 unsigned int device, 356 unsigned int bus, 357 unsigned int dev, 358 unsigned int func) 359 { 360 struct pci_config_table *table; 361 362 for (table = hose->config_table; table && table->vendor; table++) { 363 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && 364 (table->device == PCI_ANY_ID || table->device == device) && 365 (table->class == PCI_ANY_ID || table->class == class) && 366 (table->bus == PCI_ANY_ID || table->bus == bus) && 367 (table->dev == PCI_ANY_ID || table->dev == dev) && 368 (table->func == PCI_ANY_ID || table->func == func)) { 369 return table; 370 } 371 } 372 373 return NULL; 374 } 375 376 void pci_cfgfunc_config_device(struct pci_controller *hose, 377 pci_dev_t dev, 378 struct pci_config_table *entry) 379 { 380 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], 381 entry->priv[2]); 382 } 383 384 void pci_cfgfunc_do_nothing(struct pci_controller *hose, 385 pci_dev_t dev, struct pci_config_table *entry) 386 { 387 } 388 389 /* 390 * HJF: Changed this to return int. I think this is required 391 * to get the correct result when scanning bridges 392 */ 393 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 394 395 #ifdef CONFIG_PCI_SCAN_SHOW 396 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) 397 { 398 if (dev == PCI_BDF(hose->first_busno, 0, 0)) 399 return 0; 400 401 return 1; 402 } 403 #endif /* CONFIG_PCI_SCAN_SHOW */ 404 405 int pci_hose_scan_bus(struct pci_controller *hose, int bus) 406 { 407 unsigned int sub_bus, found_multi = 0; 408 unsigned short vendor, device, class; 409 unsigned char header_type; 410 #ifndef CONFIG_PCI_PNP 411 struct pci_config_table *cfg; 412 #endif 413 pci_dev_t dev; 414 #ifdef CONFIG_PCI_SCAN_SHOW 415 static int indent = 0; 416 #endif 417 418 sub_bus = bus; 419 420 for (dev = PCI_BDF(bus,0,0); 421 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, 422 PCI_MAX_PCI_FUNCTIONS - 1); 423 dev += PCI_BDF(0, 0, 1)) { 424 425 if (pci_skip_dev(hose, dev)) 426 continue; 427 428 if (PCI_FUNC(dev) && !found_multi) 429 continue; 430 431 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); 432 433 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); 434 435 if (vendor == 0xffff || vendor == 0x0000) 436 continue; 437 438 if (!PCI_FUNC(dev)) 439 found_multi = header_type & 0x80; 440 441 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n", 442 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 443 444 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); 445 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 446 447 #ifdef CONFIG_PCI_FIXUP_DEV 448 board_pci_fixup_dev(hose, dev, vendor, device, class); 449 #endif 450 451 #ifdef CONFIG_PCI_SCAN_SHOW 452 indent++; 453 454 /* Print leading space, including bus indentation */ 455 printf("%*c", indent + 1, ' '); 456 457 if (pci_print_dev(hose, dev)) { 458 printf("%02x:%02x.%-*x - %04x:%04x - %s\n", 459 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev), 460 vendor, device, pci_class_str(class >> 8)); 461 } 462 #endif 463 464 #ifdef CONFIG_PCI_PNP 465 sub_bus = max((unsigned int)pciauto_config_device(hose, dev), 466 sub_bus); 467 #else 468 cfg = pci_find_config(hose, class, vendor, device, 469 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); 470 if (cfg) { 471 cfg->config_device(hose, dev, cfg); 472 sub_bus = max(sub_bus, 473 (unsigned int)hose->current_busno); 474 } 475 #endif 476 477 #ifdef CONFIG_PCI_SCAN_SHOW 478 indent--; 479 #endif 480 481 if (hose->fixup_irq) 482 hose->fixup_irq(hose, dev); 483 } 484 485 return sub_bus; 486 } 487 488 int pci_hose_scan(struct pci_controller *hose) 489 { 490 #if defined(CONFIG_PCI_BOOTDELAY) 491 char *s; 492 int i; 493 494 if (!gd->pcidelay_done) { 495 /* wait "pcidelay" ms (if defined)... */ 496 s = getenv("pcidelay"); 497 if (s) { 498 int val = simple_strtoul(s, NULL, 10); 499 for (i = 0; i < val; i++) 500 udelay(1000); 501 } 502 gd->pcidelay_done = 1; 503 } 504 #endif /* CONFIG_PCI_BOOTDELAY */ 505 506 #ifdef CONFIG_PCI_SCAN_SHOW 507 puts("PCI:\n"); 508 #endif 509 510 /* 511 * Start scan at current_busno. 512 * PCIe will start scan at first_busno+1. 513 */ 514 /* For legacy support, ensure current >= first */ 515 if (hose->first_busno > hose->current_busno) 516 hose->current_busno = hose->first_busno; 517 #ifdef CONFIG_PCI_PNP 518 pciauto_config_init(hose); 519 #endif 520 return pci_hose_scan_bus(hose, hose->current_busno); 521 } 522 523 void pci_init(void) 524 { 525 hose_head = NULL; 526 527 /* now call board specific pci_init()... */ 528 pci_init_board(); 529 } 530 531 /* Returns the address of the requested capability structure within the 532 * device's PCI configuration space or 0 in case the device does not 533 * support it. 534 * */ 535 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 536 int cap) 537 { 538 int pos; 539 u8 hdr_type; 540 541 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); 542 543 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); 544 545 if (pos) 546 pos = pci_find_cap(hose, dev, pos, cap); 547 548 return pos; 549 } 550 551 /* Find the header pointer to the Capabilities*/ 552 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 553 u8 hdr_type) 554 { 555 u16 status; 556 557 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); 558 559 if (!(status & PCI_STATUS_CAP_LIST)) 560 return 0; 561 562 switch (hdr_type) { 563 case PCI_HEADER_TYPE_NORMAL: 564 case PCI_HEADER_TYPE_BRIDGE: 565 return PCI_CAPABILITY_LIST; 566 case PCI_HEADER_TYPE_CARDBUS: 567 return PCI_CB_CAPABILITY_LIST; 568 default: 569 return 0; 570 } 571 } 572 573 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) 574 { 575 int ttl = PCI_FIND_CAP_TTL; 576 u8 id; 577 u8 next_pos; 578 579 while (ttl--) { 580 pci_hose_read_config_byte(hose, dev, pos, &next_pos); 581 if (next_pos < CAP_START_POS) 582 break; 583 next_pos &= ~3; 584 pos = (int) next_pos; 585 pci_hose_read_config_byte(hose, dev, 586 pos + PCI_CAP_LIST_ID, &id); 587 if (id == 0xff) 588 break; 589 if (id == cap) 590 return pos; 591 pos += PCI_CAP_LIST_NEXT; 592 } 593 return 0; 594 } 595