1 /* 2 * Copyright (c) 2014 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <fdtdec.h> 12 #include <inttypes.h> 13 #include <pci.h> 14 #include <dm/lists.h> 15 #include <dm/root.h> 16 #include <dm/device-internal.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 struct pci_controller *pci_bus_to_hose(int busnum) 21 { 22 struct udevice *bus; 23 int ret; 24 25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus); 26 if (ret) { 27 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret); 28 return NULL; 29 } 30 return dev_get_uclass_priv(bus); 31 } 32 33 /** 34 * pci_get_bus_max() - returns the bus number of the last active bus 35 * 36 * @return last bus number, or -1 if no active buses 37 */ 38 static int pci_get_bus_max(void) 39 { 40 struct udevice *bus; 41 struct uclass *uc; 42 int ret = -1; 43 44 ret = uclass_get(UCLASS_PCI, &uc); 45 uclass_foreach_dev(bus, uc) { 46 if (bus->seq > ret) 47 ret = bus->seq; 48 } 49 50 debug("%s: ret=%d\n", __func__, ret); 51 52 return ret; 53 } 54 55 int pci_last_busno(void) 56 { 57 struct pci_controller *hose; 58 struct udevice *bus; 59 struct uclass *uc; 60 int ret; 61 62 debug("pci_last_busno\n"); 63 ret = uclass_get(UCLASS_PCI, &uc); 64 if (ret || list_empty(&uc->dev_head)) 65 return -1; 66 67 /* Probe the last bus */ 68 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node); 69 debug("bus = %p, %s\n", bus, bus->name); 70 assert(bus); 71 ret = device_probe(bus); 72 if (ret) 73 return ret; 74 75 /* If that bus has bridges, we may have new buses now. Get the last */ 76 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node); 77 hose = dev_get_uclass_priv(bus); 78 debug("bus = %s, hose = %p\n", bus->name, hose); 79 80 return hose->last_busno; 81 } 82 83 int pci_get_ff(enum pci_size_t size) 84 { 85 switch (size) { 86 case PCI_SIZE_8: 87 return 0xff; 88 case PCI_SIZE_16: 89 return 0xffff; 90 default: 91 return 0xffffffff; 92 } 93 } 94 95 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, 96 struct udevice **devp) 97 { 98 struct udevice *dev; 99 100 for (device_find_first_child(bus, &dev); 101 dev; 102 device_find_next_child(&dev)) { 103 struct pci_child_platdata *pplat; 104 105 pplat = dev_get_parent_platdata(dev); 106 if (pplat && pplat->devfn == find_devfn) { 107 *devp = dev; 108 return 0; 109 } 110 } 111 112 return -ENODEV; 113 } 114 115 int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp) 116 { 117 struct udevice *bus; 118 int ret; 119 120 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus); 121 if (ret) 122 return ret; 123 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp); 124 } 125 126 static int pci_device_matches_ids(struct udevice *dev, 127 struct pci_device_id *ids) 128 { 129 struct pci_child_platdata *pplat; 130 int i; 131 132 pplat = dev_get_parent_platdata(dev); 133 if (!pplat) 134 return -EINVAL; 135 for (i = 0; ids[i].vendor != 0; i++) { 136 if (pplat->vendor == ids[i].vendor && 137 pplat->device == ids[i].device) 138 return i; 139 } 140 141 return -EINVAL; 142 } 143 144 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, 145 int *indexp, struct udevice **devp) 146 { 147 struct udevice *dev; 148 149 /* Scan all devices on this bus */ 150 for (device_find_first_child(bus, &dev); 151 dev; 152 device_find_next_child(&dev)) { 153 if (pci_device_matches_ids(dev, ids) >= 0) { 154 if ((*indexp)-- <= 0) { 155 *devp = dev; 156 return 0; 157 } 158 } 159 } 160 161 return -ENODEV; 162 } 163 164 int pci_find_device_id(struct pci_device_id *ids, int index, 165 struct udevice **devp) 166 { 167 struct udevice *bus; 168 169 /* Scan all known buses */ 170 for (uclass_first_device(UCLASS_PCI, &bus); 171 bus; 172 uclass_next_device(&bus)) { 173 if (!pci_bus_find_devices(bus, ids, &index, devp)) 174 return 0; 175 } 176 *devp = NULL; 177 178 return -ENODEV; 179 } 180 181 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, 182 unsigned long value, enum pci_size_t size) 183 { 184 struct dm_pci_ops *ops; 185 186 ops = pci_get_ops(bus); 187 if (!ops->write_config) 188 return -ENOSYS; 189 return ops->write_config(bus, bdf, offset, value, size); 190 } 191 192 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value, 193 enum pci_size_t size) 194 { 195 struct udevice *bus; 196 int ret; 197 198 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus); 199 if (ret) 200 return ret; 201 202 return pci_bus_write_config(bus, PCI_MASK_BUS(bdf), offset, value, 203 size); 204 } 205 206 int pci_write_config32(pci_dev_t bdf, int offset, u32 value) 207 { 208 return pci_write_config(bdf, offset, value, PCI_SIZE_32); 209 } 210 211 int pci_write_config16(pci_dev_t bdf, int offset, u16 value) 212 { 213 return pci_write_config(bdf, offset, value, PCI_SIZE_16); 214 } 215 216 int pci_write_config8(pci_dev_t bdf, int offset, u8 value) 217 { 218 return pci_write_config(bdf, offset, value, PCI_SIZE_8); 219 } 220 221 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, 222 unsigned long *valuep, enum pci_size_t size) 223 { 224 struct dm_pci_ops *ops; 225 226 ops = pci_get_ops(bus); 227 if (!ops->read_config) 228 return -ENOSYS; 229 return ops->read_config(bus, bdf, offset, valuep, size); 230 } 231 232 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep, 233 enum pci_size_t size) 234 { 235 struct udevice *bus; 236 int ret; 237 238 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus); 239 if (ret) 240 return ret; 241 242 return pci_bus_read_config(bus, PCI_MASK_BUS(bdf), offset, valuep, 243 size); 244 } 245 246 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep) 247 { 248 unsigned long value; 249 int ret; 250 251 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32); 252 if (ret) 253 return ret; 254 *valuep = value; 255 256 return 0; 257 } 258 259 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep) 260 { 261 unsigned long value; 262 int ret; 263 264 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16); 265 if (ret) 266 return ret; 267 *valuep = value; 268 269 return 0; 270 } 271 272 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep) 273 { 274 unsigned long value; 275 int ret; 276 277 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8); 278 if (ret) 279 return ret; 280 *valuep = value; 281 282 return 0; 283 } 284 285 int pci_auto_config_devices(struct udevice *bus) 286 { 287 struct pci_controller *hose = bus->uclass_priv; 288 unsigned int sub_bus; 289 struct udevice *dev; 290 int ret; 291 292 sub_bus = bus->seq; 293 debug("%s: start\n", __func__); 294 pciauto_config_init(hose); 295 for (ret = device_find_first_child(bus, &dev); 296 !ret && dev; 297 ret = device_find_next_child(&dev)) { 298 struct pci_child_platdata *pplat; 299 struct pci_controller *ctlr_hose; 300 301 pplat = dev_get_parent_platdata(dev); 302 unsigned int max_bus; 303 pci_dev_t bdf; 304 305 bdf = PCI_ADD_BUS(bus->seq, pplat->devfn); 306 debug("%s: device %s\n", __func__, dev->name); 307 308 /* The root controller has the region information */ 309 ctlr_hose = hose->ctlr->uclass_priv; 310 max_bus = pciauto_config_device(ctlr_hose, bdf); 311 sub_bus = max(sub_bus, max_bus); 312 } 313 debug("%s: done\n", __func__); 314 315 return sub_bus; 316 } 317 318 int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf) 319 { 320 struct udevice *parent, *bus; 321 int sub_bus; 322 int ret; 323 324 debug("%s\n", __func__); 325 parent = hose->bus; 326 327 /* Find the bus within the parent */ 328 ret = pci_bus_find_devfn(parent, bdf, &bus); 329 if (ret) { 330 debug("%s: Cannot find device %x on bus %s: %d\n", __func__, 331 bdf, parent->name, ret); 332 return ret; 333 } 334 335 sub_bus = pci_get_bus_max() + 1; 336 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name); 337 pciauto_prescan_setup_bridge(hose, bdf, sub_bus); 338 339 ret = device_probe(bus); 340 if (ret) { 341 debug("%s: Cannot probe bus bus %s: %d\n", __func__, bus->name, 342 ret); 343 return ret; 344 } 345 if (sub_bus != bus->seq) { 346 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n", 347 __func__, bus->name, bus->seq, sub_bus); 348 return -EPIPE; 349 } 350 sub_bus = pci_get_bus_max(); 351 pciauto_postscan_setup_bridge(hose, bdf, sub_bus); 352 353 return sub_bus; 354 } 355 356 int pci_bind_bus_devices(struct udevice *bus) 357 { 358 ulong vendor, device; 359 ulong header_type; 360 pci_dev_t devfn, end; 361 bool found_multi; 362 int ret; 363 364 found_multi = false; 365 end = PCI_DEVFN(PCI_MAX_PCI_DEVICES - 1, PCI_MAX_PCI_FUNCTIONS - 1); 366 for (devfn = PCI_DEVFN(0, 0); devfn < end; devfn += PCI_DEVFN(0, 1)) { 367 struct pci_child_platdata *pplat; 368 struct udevice *dev; 369 ulong class; 370 371 if (PCI_FUNC(devfn) && !found_multi) 372 continue; 373 /* Check only the first access, we don't expect problems */ 374 ret = pci_bus_read_config(bus, devfn, PCI_HEADER_TYPE, 375 &header_type, PCI_SIZE_8); 376 if (ret) 377 goto error; 378 pci_bus_read_config(bus, devfn, PCI_VENDOR_ID, &vendor, 379 PCI_SIZE_16); 380 if (vendor == 0xffff || vendor == 0x0000) 381 continue; 382 383 if (!PCI_FUNC(devfn)) 384 found_multi = header_type & 0x80; 385 386 debug("%s: bus %d/%s: found device %x, function %d\n", __func__, 387 bus->seq, bus->name, PCI_DEV(devfn), PCI_FUNC(devfn)); 388 pci_bus_read_config(bus, devfn, PCI_DEVICE_ID, &device, 389 PCI_SIZE_16); 390 pci_bus_read_config(bus, devfn, PCI_CLASS_DEVICE, &class, 391 PCI_SIZE_16); 392 393 /* Find this device in the device tree */ 394 ret = pci_bus_find_devfn(bus, devfn, &dev); 395 396 /* If nothing in the device tree, bind a generic device */ 397 if (ret == -ENODEV) { 398 char name[30], *str; 399 const char *drv; 400 401 sprintf(name, "pci_%x:%x.%x", bus->seq, 402 PCI_DEV(devfn), PCI_FUNC(devfn)); 403 str = strdup(name); 404 if (!str) 405 return -ENOMEM; 406 drv = class == PCI_CLASS_BRIDGE_PCI ? 407 "pci_bridge_drv" : "pci_generic_drv"; 408 ret = device_bind_driver(bus, drv, str, &dev); 409 } 410 if (ret) 411 return ret; 412 413 /* Update the platform data */ 414 pplat = dev_get_parent_platdata(dev); 415 pplat->devfn = devfn; 416 pplat->vendor = vendor; 417 pplat->device = device; 418 pplat->class = class; 419 } 420 421 return 0; 422 error: 423 printf("Cannot read bus configuration: %d\n", ret); 424 425 return ret; 426 } 427 428 static int pci_uclass_post_bind(struct udevice *bus) 429 { 430 /* 431 * Scan the device tree for devices. This does not probe the PCI bus, 432 * as this is not permitted while binding. It just finds devices 433 * mentioned in the device tree. 434 * 435 * Before relocation, only bind devices marked for pre-relocation 436 * use. 437 */ 438 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, 439 gd->flags & GD_FLG_RELOC ? false : true); 440 } 441 442 static int decode_regions(struct pci_controller *hose, const void *blob, 443 int parent_node, int node) 444 { 445 int pci_addr_cells, addr_cells, size_cells; 446 int cells_per_record; 447 const u32 *prop; 448 int len; 449 int i; 450 451 prop = fdt_getprop(blob, node, "ranges", &len); 452 if (!prop) 453 return -EINVAL; 454 pci_addr_cells = fdt_address_cells(blob, node); 455 addr_cells = fdt_address_cells(blob, parent_node); 456 size_cells = fdt_size_cells(blob, node); 457 458 /* PCI addresses are always 3-cells */ 459 len /= sizeof(u32); 460 cells_per_record = pci_addr_cells + addr_cells + size_cells; 461 hose->region_count = 0; 462 debug("%s: len=%d, cells_per_record=%d\n", __func__, len, 463 cells_per_record); 464 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) { 465 u64 pci_addr, addr, size; 466 int space_code; 467 u32 flags; 468 int type; 469 470 if (len < cells_per_record) 471 break; 472 flags = fdt32_to_cpu(prop[0]); 473 space_code = (flags >> 24) & 3; 474 pci_addr = fdtdec_get_number(prop + 1, 2); 475 prop += pci_addr_cells; 476 addr = fdtdec_get_number(prop, addr_cells); 477 prop += addr_cells; 478 size = fdtdec_get_number(prop, size_cells); 479 prop += size_cells; 480 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64 481 ", size=%" PRIx64 ", space_code=%d\n", __func__, 482 hose->region_count, pci_addr, addr, size, space_code); 483 if (space_code & 2) { 484 type = flags & (1U << 30) ? PCI_REGION_PREFETCH : 485 PCI_REGION_MEM; 486 } else if (space_code & 1) { 487 type = PCI_REGION_IO; 488 } else { 489 continue; 490 } 491 debug(" - type=%d\n", type); 492 pci_set_region(hose->regions + hose->region_count++, pci_addr, 493 addr, size, type); 494 } 495 496 /* Add a region for our local memory */ 497 pci_set_region(hose->regions + hose->region_count++, 0, 0, 498 gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 499 500 return 0; 501 } 502 503 static int pci_uclass_pre_probe(struct udevice *bus) 504 { 505 struct pci_controller *hose; 506 int ret; 507 508 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name, 509 bus->parent->name); 510 hose = bus->uclass_priv; 511 512 /* For bridges, use the top-level PCI controller */ 513 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) { 514 hose->ctlr = bus; 515 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset, 516 bus->of_offset); 517 if (ret) { 518 debug("%s: Cannot decode regions\n", __func__); 519 return ret; 520 } 521 } else { 522 struct pci_controller *parent_hose; 523 524 parent_hose = dev_get_uclass_priv(bus->parent); 525 hose->ctlr = parent_hose->bus; 526 } 527 hose->bus = bus; 528 hose->first_busno = bus->seq; 529 hose->last_busno = bus->seq; 530 531 return 0; 532 } 533 534 static int pci_uclass_post_probe(struct udevice *bus) 535 { 536 int ret; 537 538 /* Don't scan buses before relocation */ 539 if (!(gd->flags & GD_FLG_RELOC)) 540 return 0; 541 542 debug("%s: probing bus %d\n", __func__, bus->seq); 543 ret = pci_bind_bus_devices(bus); 544 if (ret) 545 return ret; 546 547 #ifdef CONFIG_PCI_PNP 548 ret = pci_auto_config_devices(bus); 549 #endif 550 551 return ret < 0 ? ret : 0; 552 } 553 554 static int pci_uclass_child_post_bind(struct udevice *dev) 555 { 556 struct pci_child_platdata *pplat; 557 struct fdt_pci_addr addr; 558 int ret; 559 560 if (dev->of_offset == -1) 561 return 0; 562 563 /* 564 * We could read vendor, device, class if available. But for now we 565 * just check the address. 566 */ 567 pplat = dev_get_parent_platdata(dev); 568 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset, 569 FDT_PCI_SPACE_CONFIG, "reg", &addr); 570 571 if (ret) { 572 if (ret != -ENOENT) 573 return -EINVAL; 574 } else { 575 /* extract the bdf from fdt_pci_addr */ 576 pplat->devfn = addr.phys_hi & 0xffff00; 577 } 578 579 return 0; 580 } 581 582 int pci_bridge_read_config(struct udevice *bus, pci_dev_t devfn, uint offset, 583 ulong *valuep, enum pci_size_t size) 584 { 585 struct pci_controller *hose = bus->uclass_priv; 586 pci_dev_t bdf = PCI_ADD_BUS(bus->seq, devfn); 587 588 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size); 589 } 590 591 int pci_bridge_write_config(struct udevice *bus, pci_dev_t devfn, uint offset, 592 ulong value, enum pci_size_t size) 593 { 594 struct pci_controller *hose = bus->uclass_priv; 595 pci_dev_t bdf = PCI_ADD_BUS(bus->seq, devfn); 596 597 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size); 598 } 599 600 UCLASS_DRIVER(pci) = { 601 .id = UCLASS_PCI, 602 .name = "pci", 603 .flags = DM_UC_FLAG_SEQ_ALIAS, 604 .post_bind = pci_uclass_post_bind, 605 .pre_probe = pci_uclass_pre_probe, 606 .post_probe = pci_uclass_post_probe, 607 .child_post_bind = pci_uclass_child_post_bind, 608 .per_device_auto_alloc_size = sizeof(struct pci_controller), 609 .per_child_platdata_auto_alloc_size = 610 sizeof(struct pci_child_platdata), 611 }; 612 613 static const struct dm_pci_ops pci_bridge_ops = { 614 .read_config = pci_bridge_read_config, 615 .write_config = pci_bridge_write_config, 616 }; 617 618 static const struct udevice_id pci_bridge_ids[] = { 619 { .compatible = "pci-bridge" }, 620 { } 621 }; 622 623 U_BOOT_DRIVER(pci_bridge_drv) = { 624 .name = "pci_bridge_drv", 625 .id = UCLASS_PCI, 626 .of_match = pci_bridge_ids, 627 .ops = &pci_bridge_ops, 628 }; 629 630 UCLASS_DRIVER(pci_generic) = { 631 .id = UCLASS_PCI_GENERIC, 632 .name = "pci_generic", 633 }; 634 635 static const struct udevice_id pci_generic_ids[] = { 636 { .compatible = "pci-generic" }, 637 { } 638 }; 639 640 U_BOOT_DRIVER(pci_generic_drv) = { 641 .name = "pci_generic_drv", 642 .id = UCLASS_PCI_GENERIC, 643 .of_match = pci_generic_ids, 644 }; 645