1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RCar Gen2 PCIEC driver 4 * 5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <clk.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <pci.h> 14 15 /* AHB-PCI Bridge PCI communication registers */ 16 #define RCAR_AHBPCI_PCICOM_OFFSET 0x800 17 18 #define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00) 19 #define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04) 20 #define RCAR_PCIAHB_PREFETCH0 0x0 21 #define RCAR_PCIAHB_PREFETCH4 0x1 22 #define RCAR_PCIAHB_PREFETCH8 0x2 23 #define RCAR_PCIAHB_PREFETCH16 0x3 24 25 #define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10) 26 #define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14) 27 #define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1) 28 #define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1) 29 #define RCAR_AHBPCI_WIN1_HOST BIT(30) 30 #define RCAR_AHBPCI_WIN1_DEVICE BIT(31) 31 32 #define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20) 33 #define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24) 34 #define RCAR_PCI_INT_SIGTABORT BIT(0) 35 #define RCAR_PCI_INT_SIGRETABORT BIT(1) 36 #define RCAR_PCI_INT_REMABORT BIT(2) 37 #define RCAR_PCI_INT_PERR BIT(3) 38 #define RCAR_PCI_INT_SIGSERR BIT(4) 39 #define RCAR_PCI_INT_RESERR BIT(5) 40 #define RCAR_PCI_INT_WIN1ERR BIT(12) 41 #define RCAR_PCI_INT_WIN2ERR BIT(13) 42 #define RCAR_PCI_INT_A BIT(16) 43 #define RCAR_PCI_INT_B BIT(17) 44 #define RCAR_PCI_INT_PME BIT(19) 45 #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \ 46 RCAR_PCI_INT_SIGRETABORT | \ 47 RCAR_PCI_INT_SIGRETABORT | \ 48 RCAR_PCI_INT_REMABORT | \ 49 RCAR_PCI_INT_PERR | \ 50 RCAR_PCI_INT_SIGSERR | \ 51 RCAR_PCI_INT_RESERR | \ 52 RCAR_PCI_INT_WIN1ERR | \ 53 RCAR_PCI_INT_WIN2ERR) 54 55 #define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30) 56 #define RCAR_AHB_BUS_MMODE_HTRANS BIT(0) 57 #define RCAR_AHB_BUS_MMODE_BYTE_BURST BIT(1) 58 #define RCAR_AHB_BUS_MMODE_WR_INCR BIT(2) 59 #define RCAR_AHB_BUS_MMODE_HBUS_REQ BIT(7) 60 #define RCAR_AHB_BUS_SMODE_READYCTR BIT(17) 61 #define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \ 62 RCAR_AHB_BUS_MMODE_BYTE_BURST | \ 63 RCAR_AHB_BUS_MMODE_WR_INCR | \ 64 RCAR_AHB_BUS_MMODE_HBUS_REQ | \ 65 RCAR_AHB_BUS_SMODE_READYCTR) 66 67 #define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34) 68 #define RCAR_USBCTR_USBH_RST BIT(0) 69 #define RCAR_USBCTR_PCICLK_MASK BIT(1) 70 #define RCAR_USBCTR_PLL_RST BIT(2) 71 #define RCAR_USBCTR_DIRPD BIT(8) 72 #define RCAR_USBCTR_PCIAHB_WIN2_EN BIT(9) 73 #define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10) 74 #define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10) 75 #define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10) 76 #define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10) 77 #define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10) 78 79 #define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40) 80 #define RCAR_PCI_ARBITER_PCIREQ0 BIT(0) 81 #define RCAR_PCI_ARBITER_PCIREQ1 BIT(1) 82 #define RCAR_PCI_ARBITER_PCIBP_MODE BIT(12) 83 84 #define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48) 85 86 struct rcar_gen2_pci_priv { 87 fdt_addr_t cfg_base; 88 fdt_addr_t mem_base; 89 }; 90 91 static int rcar_gen2_pci_addr_valid(pci_dev_t d, uint offset) 92 { 93 u32 slot; 94 95 if (PCI_FUNC(d)) 96 return -EINVAL; 97 98 /* Only one EHCI/OHCI device built-in */ 99 slot = PCI_DEV(d); 100 if (slot != 1 && slot != 2) 101 return -EINVAL; 102 103 /* bridge logic only has registers to 0x40 */ 104 if (slot == 0x0 && offset >= 0x40) 105 return -EINVAL; 106 107 return 0; 108 } 109 110 static u32 get_bus_address(struct udevice *dev, pci_dev_t bdf, u32 offset) 111 { 112 struct rcar_gen2_pci_priv *priv = dev_get_priv(dev); 113 114 return priv->cfg_base + (PCI_DEV(bdf) >> 1) * 0x100 + (offset & ~3); 115 } 116 117 static u32 setup_bus_address(struct udevice *dev, pci_dev_t bdf, u32 offset) 118 { 119 struct rcar_gen2_pci_priv *priv = dev_get_priv(dev); 120 u32 reg; 121 122 reg = PCI_DEV(bdf) ? RCAR_AHBPCI_WIN1_DEVICE : RCAR_AHBPCI_WIN1_HOST; 123 reg |= RCAR_AHBPCI_WIN_CTR_CFG; 124 writel(reg, priv->cfg_base + RCAR_AHBPCI_WIN1_CTR_REG); 125 126 return get_bus_address(dev, bdf, offset); 127 } 128 129 static int rcar_gen2_pci_read_config(struct udevice *dev, pci_dev_t bdf, 130 uint offset, ulong *value, 131 enum pci_size_t size) 132 { 133 u32 addr, reg; 134 int ret; 135 136 ret = rcar_gen2_pci_addr_valid(bdf, offset); 137 if (ret) { 138 *value = pci_get_ff(size); 139 return 0; 140 } 141 142 addr = get_bus_address(dev, bdf, offset); 143 reg = readl(addr); 144 *value = pci_conv_32_to_size(reg, offset, size); 145 146 return 0; 147 } 148 149 static int rcar_gen2_pci_write_config(struct udevice *dev, pci_dev_t bdf, 150 uint offset, ulong value, 151 enum pci_size_t size) 152 { 153 u32 addr, reg, old; 154 int ret; 155 156 ret = rcar_gen2_pci_addr_valid(bdf, offset); 157 if (ret) 158 return ret; 159 160 addr = get_bus_address(dev, bdf, offset); 161 162 old = readl(addr); 163 reg = pci_conv_size_to_32(old, value, offset, size); 164 writel(reg, addr); 165 166 return 0; 167 } 168 169 static int rcar_gen2_pci_probe(struct udevice *dev) 170 { 171 struct rcar_gen2_pci_priv *priv = dev_get_priv(dev); 172 struct clk pci_clk; 173 u32 devad; 174 int ret; 175 176 ret = clk_get_by_index(dev, 0, &pci_clk); 177 if (ret) 178 return ret; 179 180 ret = clk_enable(&pci_clk); 181 if (ret) 182 return ret; 183 184 /* Clock & Reset & Direct Power Down */ 185 clrsetbits_le32(priv->cfg_base + RCAR_USBCTR_REG, 186 RCAR_USBCTR_DIRPD | RCAR_USBCTR_PCICLK_MASK | 187 RCAR_USBCTR_USBH_RST, 188 RCAR_USBCTR_PCIAHB_WIN1_1G); 189 clrbits_le32(priv->cfg_base + RCAR_USBCTR_REG, RCAR_USBCTR_PLL_RST); 190 191 /* AHB-PCI Bridge Communication Registers */ 192 writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG); 193 writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16, 194 priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG); 195 writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16, 196 priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG); 197 writel(priv->mem_base | RCAR_AHBPCI_WIN_CTR_MEM, 198 priv->cfg_base + RCAR_AHBPCI_WIN2_CTR_REG); 199 setbits_le32(priv->cfg_base + RCAR_PCI_ARBITER_CTR_REG, 200 RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 | 201 RCAR_PCI_ARBITER_PCIBP_MODE); 202 203 /* PCI Configuration Registers for AHBPCI */ 204 devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0); 205 writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0); 206 writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1); 207 writel(0xf0000000, devad + PCI_BASE_ADDRESS_2); 208 writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 209 PCI_COMMAND_PARITY | PCI_COMMAND_SERR, 210 devad + PCI_COMMAND); 211 212 /* PCI Configuration Registers for OHCI */ 213 devad = setup_bus_address(dev, PCI_BDF(0, 1, 0), 0); 214 writel(priv->mem_base + 0x0, devad + PCI_BASE_ADDRESS_0); 215 writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 216 PCI_COMMAND_PARITY | PCI_COMMAND_SERR, 217 devad + PCI_COMMAND); 218 219 /* PCI Configuration Registers for EHCI */ 220 devad = setup_bus_address(dev, PCI_BDF(0, 2, 0), 0); 221 writel(priv->mem_base + 0x1000, devad + PCI_BASE_ADDRESS_0); 222 writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 223 PCI_COMMAND_PARITY | PCI_COMMAND_SERR, 224 devad + PCI_COMMAND); 225 226 /* Enable PCI interrupt */ 227 setbits_le32(priv->cfg_base + RCAR_PCI_INT_ENABLE_REG, 228 RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME); 229 230 return 0; 231 } 232 233 static int rcar_gen2_pci_ofdata_to_platdata(struct udevice *dev) 234 { 235 struct rcar_gen2_pci_priv *priv = dev_get_priv(dev); 236 237 priv->cfg_base = devfdt_get_addr_index(dev, 0); 238 priv->mem_base = devfdt_get_addr_index(dev, 1); 239 if (!priv->cfg_base || !priv->mem_base) 240 return -EINVAL; 241 242 return 0; 243 } 244 245 static const struct dm_pci_ops rcar_gen2_pci_ops = { 246 .read_config = rcar_gen2_pci_read_config, 247 .write_config = rcar_gen2_pci_write_config, 248 }; 249 250 static const struct udevice_id rcar_gen2_pci_ids[] = { 251 { .compatible = "renesas,pci-rcar-gen2" }, 252 { } 253 }; 254 255 U_BOOT_DRIVER(rcar_gen2_pci) = { 256 .name = "rcar_gen2_pci", 257 .id = UCLASS_PCI, 258 .of_match = rcar_gen2_pci_ids, 259 .ops = &rcar_gen2_pci_ops, 260 .probe = rcar_gen2_pci_probe, 261 .ofdata_to_platdata = rcar_gen2_pci_ofdata_to_platdata, 262 .priv_auto_alloc_size = sizeof(struct rcar_gen2_pci_priv), 263 }; 264