1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 #ifdef CONFIG_FSL_PCI_INIT 22 23 /* 24 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 25 * 26 * Initialize controller and call the common driver/pci pci_hose_scan to 27 * scan for bridges and devices. 28 * 29 * Hose fields which need to be pre-initialized by board specific code: 30 * regions[] 31 * first_busno 32 * 33 * Fields updated: 34 * last_busno 35 */ 36 37 #include <pci.h> 38 #include <asm/immap_fsl_pci.h> 39 40 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 41 pci_dev_t dev, int sub_bus); 42 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 43 pci_dev_t dev, int sub_bus); 44 45 void pciauto_config_init(struct pci_controller *hose); 46 void 47 fsl_pci_init(struct pci_controller *hose) 48 { 49 u16 temp16; 50 u32 temp32; 51 int busno = hose->first_busno; 52 int enabled; 53 u16 ltssm; 54 u8 temp8; 55 int r; 56 int bridge; 57 int inbound = 0; 58 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; 59 pci_dev_t dev = PCI_BDF(busno,0,0); 60 61 /* Initialize ATMU registers based on hose regions and flags */ 62 volatile pot_t *po=&pci->pot[1]; /* skip 0 */ 63 volatile pit_t *pi=&pci->pit[0]; /* ranges from: 3 to 1 */ 64 65 #ifdef DEBUG 66 int neg_link_w; 67 #endif 68 69 for (r=0; r<hose->region_count; r++) { 70 if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */ 71 pi->pitar = (hose->regions[r].bus_start >> 12) & 0x000fffff; 72 pi->piwbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; 73 pi->piwbear = 0; 74 pi->piwar = PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | 75 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | 76 (__ilog2(hose->regions[r].size) - 1); 77 pi++; 78 inbound = hose->regions[r].size > 0; 79 } else { /* Outbound */ 80 po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; 81 po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff; 82 po->potear = 0; 83 if (hose->regions[r].flags & PCI_REGION_IO) 84 po->powar = POWAR_EN | POWAR_IO_READ | POWAR_IO_WRITE | 85 (__ilog2(hose->regions[r].size) - 1); 86 else 87 po->powar = POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE | 88 (__ilog2(hose->regions[r].size) - 1); 89 po++; 90 } 91 } 92 93 pci_register_hose(hose); 94 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 95 hose->current_busno = hose->first_busno; 96 97 pci->pedr = 0xffffffff; /* Clear any errors */ 98 pci->peer = ~0x20140; /* Enable All Error Interupts except 99 * - Master abort (pci) 100 * - Master PERR (pci) 101 * - ICCA (PCIe) 102 */ 103 pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32); 104 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 105 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); 106 107 pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8); 108 bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */ 109 110 if ( bridge ) { 111 112 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 113 enabled = ltssm >= PCI_LTSSM_L0; 114 115 if (!enabled) { 116 debug("....PCIE link error. Skipping scan." 117 "LTSSM=0x%02x\n", ltssm); 118 hose->last_busno = hose->first_busno; 119 return; 120 } 121 122 pci->pme_msg_det = 0xffffffff; 123 pci->pme_msg_int_en = 0xffffffff; 124 #ifdef DEBUG 125 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); 126 neg_link_w = (temp16 & 0x3f0 ) >> 4; 127 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", 128 ltssm, neg_link_w); 129 #endif 130 hose->current_busno++; /* Start scan with secondary */ 131 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 132 133 } 134 135 /* Use generic setup_device to initialize standard pci regs, 136 * but do not allocate any windows since any BAR found (such 137 * as PCSRBAR) is not in this cpu's memory space. 138 */ 139 140 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 141 hose->pci_prefetch, hose->pci_io); 142 143 if (inbound) { 144 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 145 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 146 temp16 | PCI_COMMAND_MEMORY); 147 } 148 149 #ifndef CONFIG_PCI_NOSCAN 150 printf (" Scanning PCI bus %02x\n", hose->current_busno); 151 hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); 152 153 if ( bridge ) { /* update limit regs and subordinate busno */ 154 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 155 } 156 #else 157 hose->last_busno = hose->current_busno; 158 #endif 159 160 /* Clear all error indications */ 161 162 pci->pme_msg_det = 0xffffffff; 163 pci->pedr = 0xffffffff; 164 165 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); 166 if (temp16) { 167 pci_hose_write_config_word(hose, dev, 168 PCI_DSR, 0xffff); 169 } 170 171 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 172 if (temp16) { 173 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 174 } 175 } 176 177 #endif /* CONFIG_FSL_PCI */ 178