1 /* 2 * Copyright 2007-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <asm/fsl_serdes.h> 10 11 DECLARE_GLOBAL_DATA_PTR; 12 13 /* 14 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 15 * 16 * Initialize controller and call the common driver/pci pci_hose_scan to 17 * scan for bridges and devices. 18 * 19 * Hose fields which need to be pre-initialized by board specific code: 20 * regions[] 21 * first_busno 22 * 23 * Fields updated: 24 * last_busno 25 */ 26 27 #include <pci.h> 28 #include <asm/io.h> 29 #include <asm/fsl_pci.h> 30 31 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 32 #define CONFIG_SYS_PCI_MEMORY_BUS 0 33 #endif 34 35 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 36 #define CONFIG_SYS_PCI_MEMORY_PHYS 0 37 #endif 38 39 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) 40 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) 41 #endif 42 43 /* Setup one inbound ATMU window. 44 * 45 * We let the caller decide what the window size should be 46 */ 47 static void set_inbound_window(volatile pit_t *pi, 48 struct pci_region *r, 49 u64 size) 50 { 51 u32 sz = (__ilog2_u64(size) - 1); 52 #ifdef CONFIG_SYS_FSL_ERRATUM_A005434 53 u32 flag = 0; 54 #else 55 u32 flag = PIWAR_LOCAL; 56 #endif 57 58 flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 59 60 out_be32(&pi->pitar, r->phys_start >> 12); 61 out_be32(&pi->piwbar, r->bus_start >> 12); 62 #ifdef CONFIG_SYS_PCI_64BIT 63 out_be32(&pi->piwbear, r->bus_start >> 44); 64 #else 65 out_be32(&pi->piwbear, 0); 66 #endif 67 if (r->flags & PCI_REGION_PREFETCH) 68 flag |= PIWAR_PF; 69 out_be32(&pi->piwar, flag | sz); 70 } 71 72 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) 73 { 74 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr; 75 76 /* Reset hose to make sure its in a clean state */ 77 memset(hose, 0, sizeof(struct pci_controller)); 78 79 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 80 81 return fsl_is_pci_agent(hose); 82 } 83 84 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, 85 u64 out_lo, u8 pcie_cap, 86 volatile pit_t *pi) 87 { 88 struct pci_region *r = hose->regions + hose->region_count; 89 u64 sz = min((u64)gd->ram_size, (1ull << 32)); 90 91 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; 92 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; 93 pci_size_t pci_sz; 94 95 /* we have no space available for inbound memory mapping */ 96 if (bus_start > out_lo) { 97 printf ("no space for inbound mapping of memory\n"); 98 return 0; 99 } 100 101 /* limit size */ 102 if ((bus_start + sz) > out_lo) { 103 sz = out_lo - bus_start; 104 debug ("limiting size to %llx\n", sz); 105 } 106 107 pci_sz = 1ull << __ilog2_u64(sz); 108 /* 109 * we can overlap inbound/outbound windows on PCI-E since RX & TX 110 * links a separate 111 */ 112 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) { 113 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 114 (u64)bus_start, (u64)phys_start, (u64)sz); 115 pci_set_region(r, bus_start, phys_start, sz, 116 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 117 PCI_REGION_PREFETCH); 118 119 /* if we aren't an exact power of two match, pci_sz is smaller 120 * round it up to the next power of two. We report the actual 121 * size to pci region tracking. 122 */ 123 if (pci_sz != sz) 124 sz = 2ull << __ilog2_u64(sz); 125 126 set_inbound_window(pi--, r++, sz); 127 sz = 0; /* make sure we dont set the R2 window */ 128 } else { 129 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 130 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 131 pci_set_region(r, bus_start, phys_start, pci_sz, 132 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 133 PCI_REGION_PREFETCH); 134 set_inbound_window(pi--, r++, pci_sz); 135 136 sz -= pci_sz; 137 bus_start += pci_sz; 138 phys_start += pci_sz; 139 140 pci_sz = 1ull << __ilog2_u64(sz); 141 if (sz) { 142 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", 143 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 144 pci_set_region(r, bus_start, phys_start, pci_sz, 145 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 146 PCI_REGION_PREFETCH); 147 set_inbound_window(pi--, r++, pci_sz); 148 sz -= pci_sz; 149 bus_start += pci_sz; 150 phys_start += pci_sz; 151 } 152 } 153 154 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) 155 /* 156 * On 64-bit capable systems, set up a mapping for all of DRAM 157 * in high pci address space. 158 */ 159 pci_sz = 1ull << __ilog2_u64(gd->ram_size); 160 /* round up to the next largest power of two */ 161 if (gd->ram_size > pci_sz) 162 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); 163 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", 164 (u64)CONFIG_SYS_PCI64_MEMORY_BUS, 165 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, 166 (u64)pci_sz); 167 pci_set_region(r, 168 CONFIG_SYS_PCI64_MEMORY_BUS, 169 CONFIG_SYS_PCI_MEMORY_PHYS, 170 pci_sz, 171 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 172 PCI_REGION_PREFETCH); 173 set_inbound_window(pi--, r++, pci_sz); 174 #else 175 pci_sz = 1ull << __ilog2_u64(sz); 176 if (sz) { 177 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", 178 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 179 pci_set_region(r, bus_start, phys_start, pci_sz, 180 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 181 PCI_REGION_PREFETCH); 182 sz -= pci_sz; 183 bus_start += pci_sz; 184 phys_start += pci_sz; 185 set_inbound_window(pi--, r++, pci_sz); 186 } 187 #endif 188 189 #ifdef CONFIG_PHYS_64BIT 190 if (sz && (((u64)gd->ram_size) < (1ull << 32))) 191 printf("Was not able to map all of memory via " 192 "inbound windows -- %lld remaining\n", sz); 193 #endif 194 195 hose->region_count = r - hose->regions; 196 197 return 1; 198 } 199 200 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 201 static void fsl_pcie_boot_master(pit_t *pi) 202 { 203 /* configure inbound window for slave's u-boot image */ 204 debug("PCIEBOOT - MASTER: Inbound window for slave's image; " 205 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", 206 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 207 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, 208 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 209 struct pci_region r_inbound; 210 u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE) 211 - 1; 212 pci_set_region(&r_inbound, 213 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, 214 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 215 sz_inbound, 216 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 217 218 set_inbound_window(pi--, &r_inbound, 219 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 220 221 /* configure inbound window for slave's u-boot image */ 222 debug("PCIEBOOT - MASTER: Inbound window for slave's image; " 223 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", 224 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 225 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, 226 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 227 pci_set_region(&r_inbound, 228 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, 229 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 230 sz_inbound, 231 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 232 233 set_inbound_window(pi--, &r_inbound, 234 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 235 236 /* configure inbound window for slave's ucode and ENV */ 237 debug("PCIEBOOT - MASTER: Inbound window for slave's " 238 "ucode and ENV; " 239 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", 240 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, 241 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, 242 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); 243 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE) 244 - 1; 245 pci_set_region(&r_inbound, 246 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, 247 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, 248 sz_inbound, 249 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 250 251 set_inbound_window(pi--, &r_inbound, 252 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); 253 } 254 255 static void fsl_pcie_boot_master_release_slave(int port) 256 { 257 unsigned long release_addr; 258 259 /* now release slave's core 0 */ 260 switch (port) { 261 case 1: 262 release_addr = CONFIG_SYS_PCIE1_MEM_VIRT 263 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; 264 break; 265 #ifdef CONFIG_SYS_PCIE2_MEM_VIRT 266 case 2: 267 release_addr = CONFIG_SYS_PCIE2_MEM_VIRT 268 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; 269 break; 270 #endif 271 #ifdef CONFIG_SYS_PCIE3_MEM_VIRT 272 case 3: 273 release_addr = CONFIG_SYS_PCIE3_MEM_VIRT 274 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; 275 break; 276 #endif 277 default: 278 release_addr = 0; 279 break; 280 } 281 if (release_addr != 0) { 282 out_be32((void *)release_addr, 283 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); 284 debug("PCIEBOOT - MASTER: " 285 "Release slave successfully! Now the slave should start up!\n"); 286 } else { 287 debug("PCIEBOOT - MASTER: " 288 "Release slave failed!\n"); 289 } 290 } 291 #endif 292 293 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) 294 { 295 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; 296 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; 297 u16 temp16; 298 u32 temp32; 299 u32 block_rev; 300 int enabled, r, inbound = 0; 301 u16 ltssm; 302 u8 temp8, pcie_cap; 303 int pcie_cap_pos; 304 int pci_dcr; 305 int pci_dsr; 306 int pci_lsr; 307 308 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) 309 int pci_lcr; 310 #endif 311 312 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; 313 struct pci_region *reg = hose->regions + hose->region_count; 314 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 315 316 /* Initialize ATMU registers based on hose regions and flags */ 317 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ 318 volatile pit_t *pi; 319 320 u64 out_hi = 0, out_lo = -1ULL; 321 u32 pcicsrbar, pcicsrbar_sz; 322 323 pci_setup_indirect(hose, cfg_addr, cfg_data); 324 325 block_rev = in_be32(&pci->block_rev1); 326 if (PEX_IP_BLK_REV_2_2 <= block_rev) { 327 pi = &pci->pit[2]; /* 0xDC0 */ 328 } else { 329 pi = &pci->pit[3]; /* 0xDE0 */ 330 } 331 332 /* Handle setup of outbound windows first */ 333 for (r = 0; r < hose->region_count; r++) { 334 unsigned long flags = hose->regions[r].flags; 335 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); 336 337 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE; 338 if (flags != PCI_REGION_SYS_MEMORY) { 339 u64 start = hose->regions[r].bus_start; 340 u64 end = start + hose->regions[r].size; 341 342 out_be32(&po->powbar, hose->regions[r].phys_start >> 12); 343 out_be32(&po->potar, start >> 12); 344 #ifdef CONFIG_SYS_PCI_64BIT 345 out_be32(&po->potear, start >> 44); 346 #else 347 out_be32(&po->potear, 0); 348 #endif 349 if (hose->regions[r].flags & PCI_REGION_IO) { 350 out_be32(&po->powar, POWAR_EN | sz | 351 POWAR_IO_READ | POWAR_IO_WRITE); 352 } else { 353 out_be32(&po->powar, POWAR_EN | sz | 354 POWAR_MEM_READ | POWAR_MEM_WRITE); 355 out_lo = min(start, out_lo); 356 out_hi = max(end, out_hi); 357 } 358 po++; 359 } 360 } 361 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi); 362 363 /* setup PCSRBAR/PEXCSRBAR */ 364 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); 365 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 366 pcicsrbar_sz = ~pcicsrbar_sz + 1; 367 368 if (out_hi < (0x100000000ull - pcicsrbar_sz) || 369 (out_lo > 0x100000000ull)) 370 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 371 else 372 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz; 373 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar); 374 375 out_lo = min(out_lo, (u64)pcicsrbar); 376 377 debug("PCICSRBAR @ 0x%x\n", pcicsrbar); 378 379 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS, 380 pcicsrbar_sz, PCI_REGION_SYS_MEMORY); 381 hose->region_count++; 382 383 /* see if we are a PCIe or PCI controller */ 384 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); 385 pci_dcr = pcie_cap_pos + 0x08; 386 pci_dsr = pcie_cap_pos + 0x0a; 387 pci_lsr = pcie_cap_pos + 0x12; 388 389 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); 390 391 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 392 /* boot from PCIE --master */ 393 char *s = env_get("bootmaster"); 394 char pcie[6]; 395 sprintf(pcie, "PCIE%d", pci_info->pci_num); 396 397 if (s && (strcmp(s, pcie) == 0)) { 398 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n", 399 pci_info->pci_num); 400 fsl_pcie_boot_master((pit_t *)pi); 401 } else { 402 /* inbound */ 403 inbound = fsl_pci_setup_inbound_windows(hose, 404 out_lo, pcie_cap, pi); 405 } 406 #else 407 /* inbound */ 408 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi); 409 #endif 410 411 for (r = 0; r < hose->region_count; r++) 412 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r, 413 (u64)hose->regions[r].phys_start, 414 (u64)hose->regions[r].bus_start, 415 (u64)hose->regions[r].size, 416 hose->regions[r].flags); 417 418 pci_register_hose(hose); 419 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 420 hose->current_busno = hose->first_busno; 421 422 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */ 423 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except 424 * - Master abort (pci) 425 * - Master PERR (pci) 426 * - ICCA (PCIe) 427 */ 428 pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32); 429 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 430 pci_hose_write_config_dword(hose, dev, pci_dcr, temp32); 431 432 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) 433 pci_lcr = pcie_cap_pos + 0x10; 434 temp32 = 0; 435 pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32); 436 temp32 &= ~0x03; /* Disable ASPM */ 437 pci_hose_write_config_dword(hose, dev, pci_lcr, temp32); 438 udelay(1); 439 #endif 440 if (pcie_cap == PCI_CAP_ID_EXP) { 441 if (block_rev >= PEX_IP_BLK_REV_3_0) { 442 #define PEX_CSR0_LTSSM_MASK 0xFC 443 #define PEX_CSR0_LTSSM_SHIFT 2 444 ltssm = (in_be32(&pci->pex_csr0) 445 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; 446 enabled = (ltssm == 0x11) ? 1 : 0; 447 #ifdef CONFIG_FSL_PCIE_RESET 448 int i; 449 /* assert PCIe reset */ 450 setbits_be32(&pci->pdb_stat, 0x08000000); 451 (void) in_be32(&pci->pdb_stat); 452 udelay(1000); 453 /* clear PCIe reset */ 454 clrbits_be32(&pci->pdb_stat, 0x08000000); 455 asm("sync;isync"); 456 for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { 457 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 458 <ssm); 459 udelay(1000); 460 } 461 #endif 462 } else { 463 /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */ 464 /* enabled = ltssm >= PCI_LTSSM_L0; */ 465 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 466 enabled = ltssm >= PCI_LTSSM_L0; 467 468 #ifdef CONFIG_FSL_PCIE_RESET 469 if (ltssm == 1) { 470 int i; 471 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm); 472 /* assert PCIe reset */ 473 setbits_be32(&pci->pdb_stat, 0x08000000); 474 (void) in_be32(&pci->pdb_stat); 475 udelay(100); 476 debug(" Asserting PCIe reset @%p = %x\n", 477 &pci->pdb_stat, in_be32(&pci->pdb_stat)); 478 /* clear PCIe reset */ 479 clrbits_be32(&pci->pdb_stat, 0x08000000); 480 asm("sync;isync"); 481 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { 482 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 483 <ssm); 484 udelay(1000); 485 debug("....PCIe link error. " 486 "LTSSM=0x%02x.\n", ltssm); 487 } 488 enabled = ltssm >= PCI_LTSSM_L0; 489 490 /* we need to re-write the bar0 since a reset will 491 * clear it 492 */ 493 pci_hose_write_config_dword(hose, dev, 494 PCI_BASE_ADDRESS_0, pcicsrbar); 495 } 496 #endif 497 } 498 499 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 500 if (enabled == 0) { 501 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 502 temp32 = in_be32(&srds_regs->srdspccr0); 503 504 if ((temp32 >> 28) == 3) { 505 int i; 506 507 out_be32(&srds_regs->srdspccr0, 2 << 28); 508 setbits_be32(&pci->pdb_stat, 0x08000000); 509 in_be32(&pci->pdb_stat); 510 udelay(100); 511 clrbits_be32(&pci->pdb_stat, 0x08000000); 512 asm("sync;isync"); 513 for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { 514 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 515 udelay(1000); 516 } 517 enabled = ltssm >= PCI_LTSSM_L0; 518 } 519 } 520 #endif 521 if (!enabled) { 522 /* Let the user know there's no PCIe link for root 523 * complex. for endpoint, the link may not setup, so 524 * print undetermined. 525 */ 526 if (fsl_is_pci_agent(hose)) 527 printf("undetermined, regs @ 0x%lx\n", pci_info->regs); 528 else 529 printf("no link, regs @ 0x%lx\n", pci_info->regs); 530 hose->last_busno = hose->first_busno; 531 return; 532 } 533 534 out_be32(&pci->pme_msg_det, 0xffffffff); 535 out_be32(&pci->pme_msg_int_en, 0xffffffff); 536 537 /* Print the negotiated PCIe link width */ 538 pci_hose_read_config_word(hose, dev, pci_lsr, &temp16); 539 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4, 540 (temp16 & 0xf), pci_info->regs); 541 542 hose->current_busno++; /* Start scan with secondary */ 543 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 544 } 545 546 #ifdef CONFIG_SYS_FSL_ERRATUM_A007815 547 /* The Read-Only Write Enable bit defaults to 1 instead of 0. 548 * Set to 0 to protect the read-only registers. 549 */ 550 clrbits_be32(&pci->dbi_ro_wr_en, 0x01); 551 #endif 552 553 /* Use generic setup_device to initialize standard pci regs, 554 * but do not allocate any windows since any BAR found (such 555 * as PCSRBAR) is not in this cpu's memory space. 556 */ 557 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 558 hose->pci_prefetch, hose->pci_io); 559 560 if (inbound) { 561 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 562 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 563 temp16 | PCI_COMMAND_MEMORY); 564 } 565 566 #ifndef CONFIG_PCI_NOSCAN 567 if (!fsl_is_pci_agent(hose)) { 568 debug(" Scanning PCI bus %02x\n", 569 hose->current_busno); 570 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); 571 } else { 572 debug(" Not scanning PCI bus %02x. PI=%x\n", 573 hose->current_busno, temp8); 574 hose->last_busno = hose->current_busno; 575 } 576 577 /* if we are PCIe - update limit regs and subordinate busno 578 * for the virtual P2P bridge 579 */ 580 if (pcie_cap == PCI_CAP_ID_EXP) { 581 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 582 } 583 #else 584 hose->last_busno = hose->current_busno; 585 #endif 586 587 /* Clear all error indications */ 588 if (pcie_cap == PCI_CAP_ID_EXP) 589 out_be32(&pci->pme_msg_det, 0xffffffff); 590 out_be32(&pci->pedr, 0xffffffff); 591 592 pci_hose_read_config_word(hose, dev, pci_dsr, &temp16); 593 if (temp16) { 594 pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff); 595 } 596 597 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 598 if (temp16) { 599 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 600 } 601 } 602 603 int fsl_is_pci_agent(struct pci_controller *hose) 604 { 605 int pcie_cap_pos; 606 u8 pcie_cap; 607 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 608 609 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); 610 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); 611 if (pcie_cap == PCI_CAP_ID_EXP) { 612 u8 header_type; 613 614 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, 615 &header_type); 616 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; 617 } else { 618 u8 prog_if; 619 620 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); 621 /* Programming Interface (PCI_CLASS_PROG) 622 * 0 == pci host or pcie root-complex, 623 * 1 == pci agent or pcie end-point 624 */ 625 return (prog_if == FSL_PROG_IF_AGENT); 626 } 627 } 628 629 int fsl_pci_init_port(struct fsl_pci_info *pci_info, 630 struct pci_controller *hose, int busno) 631 { 632 volatile ccsr_fsl_pci_t *pci; 633 struct pci_region *r; 634 pci_dev_t dev = PCI_BDF(busno,0,0); 635 int pcie_cap_pos; 636 u8 pcie_cap; 637 638 pci = (ccsr_fsl_pci_t *) pci_info->regs; 639 640 /* on non-PCIe controllers we don't have pme_msg_det so this code 641 * should do nothing since the read will return 0 642 */ 643 if (in_be32(&pci->pme_msg_det)) { 644 out_be32(&pci->pme_msg_det, 0xffffffff); 645 debug (" with errors. Clearing. Now 0x%08x", 646 pci->pme_msg_det); 647 } 648 649 r = hose->regions + hose->region_count; 650 651 /* outbound memory */ 652 pci_set_region(r++, 653 pci_info->mem_bus, 654 pci_info->mem_phys, 655 pci_info->mem_size, 656 PCI_REGION_MEM); 657 658 /* outbound io */ 659 pci_set_region(r++, 660 pci_info->io_bus, 661 pci_info->io_phys, 662 pci_info->io_size, 663 PCI_REGION_IO); 664 665 hose->region_count = r - hose->regions; 666 hose->first_busno = busno; 667 668 fsl_pci_init(hose, pci_info); 669 670 if (fsl_is_pci_agent(hose)) { 671 fsl_pci_config_unlock(hose); 672 hose->last_busno = hose->first_busno; 673 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 674 } else { 675 /* boot from PCIE --master releases slave's core 0 */ 676 char *s = env_get("bootmaster"); 677 char pcie[6]; 678 sprintf(pcie, "PCIE%d", pci_info->pci_num); 679 680 if (s && (strcmp(s, pcie) == 0)) 681 fsl_pcie_boot_master_release_slave(pci_info->pci_num); 682 #endif 683 } 684 685 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); 686 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); 687 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? 688 "e" : "", pci_info->pci_num, 689 hose->first_busno, hose->last_busno); 690 return(hose->last_busno + 1); 691 } 692 693 /* Enable inbound PCI config cycles for agent/endpoint interface */ 694 void fsl_pci_config_unlock(struct pci_controller *hose) 695 { 696 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); 697 int pcie_cap_pos; 698 u8 pcie_cap; 699 u16 pbfr; 700 701 if (!fsl_is_pci_agent(hose)) 702 return; 703 704 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); 705 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); 706 if (pcie_cap != 0x0) { 707 ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr; 708 u32 block_rev = in_be32(&pci->block_rev1); 709 /* PCIe - set CFG_READY bit of Configuration Ready Register */ 710 if (block_rev >= PEX_IP_BLK_REV_3_0) 711 setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY); 712 else 713 pci_hose_write_config_byte(hose, dev, 714 FSL_PCIE_CFG_RDY, 0x1); 715 } else { 716 /* PCI - clear ACL bit of PBFR */ 717 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); 718 pbfr &= ~0x20; 719 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr); 720 } 721 } 722 723 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \ 724 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4) 725 int fsl_configure_pcie(struct fsl_pci_info *info, 726 struct pci_controller *hose, 727 const char *connected, int busno) 728 { 729 int is_endpoint; 730 731 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); 732 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); 733 734 is_endpoint = fsl_setup_hose(hose, info->regs); 735 printf("PCIe%u: %s", info->pci_num, 736 is_endpoint ? "Endpoint" : "Root Complex"); 737 if (connected) 738 printf(" of %s", connected); 739 puts(", "); 740 741 return fsl_pci_init_port(info, hose, busno); 742 } 743 744 #if defined(CONFIG_FSL_CORENET) 745 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 746 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1 747 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2 748 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3 749 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4 750 #else 751 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1 752 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2 753 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3 754 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4 755 #endif 756 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 757 #elif defined(CONFIG_MPC85xx) 758 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE 759 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 760 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 761 #define _DEVDISR_PCIE4 0 762 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 763 #elif defined(CONFIG_MPC86xx) 764 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1 765 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2 766 #define _DEVDISR_PCIE3 0 767 #define _DEVDISR_PCIE4 0 768 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ 769 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) 770 #else 771 #error "No defines for DEVDISR_PCIE" 772 #endif 773 774 /* Implement a dummy function for those platforms w/o SERDES */ 775 static const char *__board_serdes_name(enum srds_prtcl device) 776 { 777 switch (device) { 778 #ifdef CONFIG_SYS_PCIE1_NAME 779 case PCIE1: 780 return CONFIG_SYS_PCIE1_NAME; 781 #endif 782 #ifdef CONFIG_SYS_PCIE2_NAME 783 case PCIE2: 784 return CONFIG_SYS_PCIE2_NAME; 785 #endif 786 #ifdef CONFIG_SYS_PCIE3_NAME 787 case PCIE3: 788 return CONFIG_SYS_PCIE3_NAME; 789 #endif 790 #ifdef CONFIG_SYS_PCIE4_NAME 791 case PCIE4: 792 return CONFIG_SYS_PCIE4_NAME; 793 #endif 794 default: 795 return NULL; 796 } 797 798 return NULL; 799 } 800 801 __attribute__((weak, alias("__board_serdes_name"))) const char * 802 board_serdes_name(enum srds_prtcl device); 803 804 static u32 devdisr_mask[] = { 805 _DEVDISR_PCIE1, 806 _DEVDISR_PCIE2, 807 _DEVDISR_PCIE3, 808 _DEVDISR_PCIE4, 809 }; 810 811 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 812 struct fsl_pci_info *pci_info) 813 { 814 struct pci_controller *hose; 815 int num = dev - PCIE1; 816 817 hose = calloc(1, sizeof(struct pci_controller)); 818 if (!hose) 819 return busno; 820 821 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) { 822 busno = fsl_configure_pcie(pci_info, hose, 823 board_serdes_name(dev), busno); 824 } else { 825 printf("PCIe%d: disabled\n", num + 1); 826 } 827 828 return busno; 829 } 830 831 int fsl_pcie_init_board(int busno) 832 { 833 struct fsl_pci_info pci_info; 834 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; 835 u32 devdisr; 836 u32 *addr; 837 838 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 839 addr = &gur->devdisr3; 840 #else 841 addr = &gur->devdisr; 842 #endif 843 devdisr = in_be32(addr); 844 845 #ifdef CONFIG_PCIE1 846 SET_STD_PCIE_INFO(pci_info, 1); 847 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); 848 #else 849 setbits_be32(addr, _DEVDISR_PCIE1); /* disable */ 850 #endif 851 852 #ifdef CONFIG_PCIE2 853 SET_STD_PCIE_INFO(pci_info, 2); 854 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info); 855 #else 856 setbits_be32(addr, _DEVDISR_PCIE2); /* disable */ 857 #endif 858 859 #ifdef CONFIG_PCIE3 860 SET_STD_PCIE_INFO(pci_info, 3); 861 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info); 862 #else 863 setbits_be32(addr, _DEVDISR_PCIE3); /* disable */ 864 #endif 865 866 #ifdef CONFIG_PCIE4 867 SET_STD_PCIE_INFO(pci_info, 4); 868 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info); 869 #else 870 setbits_be32(addr, _DEVDISR_PCIE4); /* disable */ 871 #endif 872 873 return busno; 874 } 875 #else 876 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 877 struct fsl_pci_info *pci_info) 878 { 879 return busno; 880 } 881 882 int fsl_pcie_init_board(int busno) 883 { 884 return busno; 885 } 886 #endif 887 888 #ifdef CONFIG_OF_BOARD_SETUP 889 #include <libfdt.h> 890 #include <fdt_support.h> 891 892 void ft_fsl_pci_setup(void *blob, const char *pci_compat, 893 unsigned long ctrl_addr) 894 { 895 int off; 896 u32 bus_range[2]; 897 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr; 898 struct pci_controller *hose; 899 900 hose = find_hose_by_cfg_addr((void *)(ctrl_addr)); 901 902 /* convert ctrl_addr to true physical address */ 903 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR; 904 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS; 905 906 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr); 907 908 if (off < 0) 909 return; 910 911 /* We assume a cfg_addr not being set means we didn't setup the controller */ 912 if ((hose == NULL) || (hose->cfg_addr == NULL)) { 913 fdt_del_node(blob, off); 914 } else { 915 bus_range[0] = 0; 916 bus_range[1] = hose->last_busno - hose->first_busno; 917 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); 918 fdt_pci_dma_ranges(blob, off, hose); 919 } 920 } 921 #endif 922