1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <malloc.h> 22 #include <asm/fsl_serdes.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* 27 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 28 * 29 * Initialize controller and call the common driver/pci pci_hose_scan to 30 * scan for bridges and devices. 31 * 32 * Hose fields which need to be pre-initialized by board specific code: 33 * regions[] 34 * first_busno 35 * 36 * Fields updated: 37 * last_busno 38 */ 39 40 #include <pci.h> 41 #include <asm/io.h> 42 #include <asm/fsl_pci.h> 43 44 /* Freescale-specific PCI config registers */ 45 #define FSL_PCI_PBFR 0x44 46 #define FSL_PCIE_CAP_ID 0x4c 47 #define FSL_PCIE_CFG_RDY 0x4b0 48 #define FSL_PROG_IF_AGENT 0x1 49 50 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 51 #define CONFIG_SYS_PCI_MEMORY_BUS 0 52 #endif 53 54 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 55 #define CONFIG_SYS_PCI_MEMORY_PHYS 0 56 #endif 57 58 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) 59 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) 60 #endif 61 62 /* Setup one inbound ATMU window. 63 * 64 * We let the caller decide what the window size should be 65 */ 66 static void set_inbound_window(volatile pit_t *pi, 67 struct pci_region *r, 68 u64 size) 69 { 70 u32 sz = (__ilog2_u64(size) - 1); 71 u32 flag = PIWAR_EN | PIWAR_LOCAL | 72 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 73 74 out_be32(&pi->pitar, r->phys_start >> 12); 75 out_be32(&pi->piwbar, r->bus_start >> 12); 76 #ifdef CONFIG_SYS_PCI_64BIT 77 out_be32(&pi->piwbear, r->bus_start >> 44); 78 #else 79 out_be32(&pi->piwbear, 0); 80 #endif 81 if (r->flags & PCI_REGION_PREFETCH) 82 flag |= PIWAR_PF; 83 out_be32(&pi->piwar, flag | sz); 84 } 85 86 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) 87 { 88 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr; 89 90 /* Reset hose to make sure its in a clean state */ 91 memset(hose, 0, sizeof(struct pci_controller)); 92 93 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 94 95 return fsl_is_pci_agent(hose); 96 } 97 98 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, 99 u64 out_lo, u8 pcie_cap, 100 volatile pit_t *pi) 101 { 102 struct pci_region *r = hose->regions + hose->region_count; 103 u64 sz = min((u64)gd->ram_size, (1ull << 32)); 104 105 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; 106 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; 107 pci_size_t pci_sz; 108 109 /* we have no space available for inbound memory mapping */ 110 if (bus_start > out_lo) { 111 printf ("no space for inbound mapping of memory\n"); 112 return 0; 113 } 114 115 /* limit size */ 116 if ((bus_start + sz) > out_lo) { 117 sz = out_lo - bus_start; 118 debug ("limiting size to %llx\n", sz); 119 } 120 121 pci_sz = 1ull << __ilog2_u64(sz); 122 /* 123 * we can overlap inbound/outbound windows on PCI-E since RX & TX 124 * links a separate 125 */ 126 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) { 127 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 128 (u64)bus_start, (u64)phys_start, (u64)sz); 129 pci_set_region(r, bus_start, phys_start, sz, 130 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 131 PCI_REGION_PREFETCH); 132 133 /* if we aren't an exact power of two match, pci_sz is smaller 134 * round it up to the next power of two. We report the actual 135 * size to pci region tracking. 136 */ 137 if (pci_sz != sz) 138 sz = 2ull << __ilog2_u64(sz); 139 140 set_inbound_window(pi--, r++, sz); 141 sz = 0; /* make sure we dont set the R2 window */ 142 } else { 143 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 144 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 145 pci_set_region(r, bus_start, phys_start, pci_sz, 146 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 147 PCI_REGION_PREFETCH); 148 set_inbound_window(pi--, r++, pci_sz); 149 150 sz -= pci_sz; 151 bus_start += pci_sz; 152 phys_start += pci_sz; 153 154 pci_sz = 1ull << __ilog2_u64(sz); 155 if (sz) { 156 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", 157 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 158 pci_set_region(r, bus_start, phys_start, pci_sz, 159 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 160 PCI_REGION_PREFETCH); 161 set_inbound_window(pi--, r++, pci_sz); 162 sz -= pci_sz; 163 bus_start += pci_sz; 164 phys_start += pci_sz; 165 } 166 } 167 168 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) 169 /* 170 * On 64-bit capable systems, set up a mapping for all of DRAM 171 * in high pci address space. 172 */ 173 pci_sz = 1ull << __ilog2_u64(gd->ram_size); 174 /* round up to the next largest power of two */ 175 if (gd->ram_size > pci_sz) 176 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); 177 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", 178 (u64)CONFIG_SYS_PCI64_MEMORY_BUS, 179 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, 180 (u64)pci_sz); 181 pci_set_region(r, 182 CONFIG_SYS_PCI64_MEMORY_BUS, 183 CONFIG_SYS_PCI_MEMORY_PHYS, 184 pci_sz, 185 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 186 PCI_REGION_PREFETCH); 187 set_inbound_window(pi--, r++, pci_sz); 188 #else 189 pci_sz = 1ull << __ilog2_u64(sz); 190 if (sz) { 191 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", 192 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 193 pci_set_region(r, bus_start, phys_start, pci_sz, 194 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 195 PCI_REGION_PREFETCH); 196 sz -= pci_sz; 197 bus_start += pci_sz; 198 phys_start += pci_sz; 199 set_inbound_window(pi--, r++, pci_sz); 200 } 201 #endif 202 203 #ifdef CONFIG_PHYS_64BIT 204 if (sz && (((u64)gd->ram_size) < (1ull << 32))) 205 printf("Was not able to map all of memory via " 206 "inbound windows -- %lld remaining\n", sz); 207 #endif 208 209 hose->region_count = r - hose->regions; 210 211 return 1; 212 } 213 214 #ifdef CONFIG_FSL_CORENET 215 static void fsl_pcie_boot_master(pit_t *pi) 216 { 217 /* configure inbound window for slave's u-boot image */ 218 debug("PCIEBOOT - MASTER: Inbound window for slave's image; " 219 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", 220 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 221 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, 222 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 223 struct pci_region r_inbound; 224 u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE) 225 - 1; 226 pci_set_region(&r_inbound, 227 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, 228 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 229 sz_inbound, 230 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 231 232 set_inbound_window(pi--, &r_inbound, 233 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 234 235 /* configure inbound window for slave's u-boot image */ 236 debug("PCIEBOOT - MASTER: Inbound window for slave's image; " 237 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", 238 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 239 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, 240 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 241 pci_set_region(&r_inbound, 242 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, 243 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 244 sz_inbound, 245 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 246 247 set_inbound_window(pi--, &r_inbound, 248 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 249 250 /* configure inbound window for slave's ucode and ENV */ 251 debug("PCIEBOOT - MASTER: Inbound window for slave's " 252 "ucode and ENV; " 253 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", 254 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, 255 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, 256 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); 257 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE) 258 - 1; 259 pci_set_region(&r_inbound, 260 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, 261 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, 262 sz_inbound, 263 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 264 265 set_inbound_window(pi--, &r_inbound, 266 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); 267 } 268 269 static void fsl_pcie_boot_master_release_slave(int port) 270 { 271 unsigned long release_addr; 272 273 /* now release slave's core 0 */ 274 switch (port) { 275 case 1: 276 release_addr = CONFIG_SYS_PCIE1_MEM_VIRT 277 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; 278 break; 279 case 2: 280 release_addr = CONFIG_SYS_PCIE2_MEM_VIRT 281 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; 282 break; 283 case 3: 284 release_addr = CONFIG_SYS_PCIE3_MEM_VIRT 285 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; 286 break; 287 default: 288 release_addr = 0; 289 break; 290 } 291 if (release_addr != 0) { 292 out_be32((void *)release_addr, 293 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); 294 debug("PCIEBOOT - MASTER: " 295 "Release slave successfully! Now the slave should start up!\n"); 296 } else { 297 debug("PCIEBOOT - MASTER: " 298 "Release slave failed!\n"); 299 } 300 } 301 #endif 302 303 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) 304 { 305 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; 306 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; 307 u16 temp16; 308 u32 temp32; 309 u32 block_rev; 310 int enabled, r, inbound = 0; 311 u16 ltssm; 312 u8 temp8, pcie_cap; 313 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; 314 struct pci_region *reg = hose->regions + hose->region_count; 315 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 316 317 /* Initialize ATMU registers based on hose regions and flags */ 318 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ 319 volatile pit_t *pi; 320 321 u64 out_hi = 0, out_lo = -1ULL; 322 u32 pcicsrbar, pcicsrbar_sz; 323 324 pci_setup_indirect(hose, cfg_addr, cfg_data); 325 326 block_rev = in_be32(&pci->block_rev1); 327 if (PEX_IP_BLK_REV_2_2 <= block_rev) { 328 pi = &pci->pit[2]; /* 0xDC0 */ 329 } else { 330 pi = &pci->pit[3]; /* 0xDE0 */ 331 } 332 333 /* Handle setup of outbound windows first */ 334 for (r = 0; r < hose->region_count; r++) { 335 unsigned long flags = hose->regions[r].flags; 336 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); 337 338 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE; 339 if (flags != PCI_REGION_SYS_MEMORY) { 340 u64 start = hose->regions[r].bus_start; 341 u64 end = start + hose->regions[r].size; 342 343 out_be32(&po->powbar, hose->regions[r].phys_start >> 12); 344 out_be32(&po->potar, start >> 12); 345 #ifdef CONFIG_SYS_PCI_64BIT 346 out_be32(&po->potear, start >> 44); 347 #else 348 out_be32(&po->potear, 0); 349 #endif 350 if (hose->regions[r].flags & PCI_REGION_IO) { 351 out_be32(&po->powar, POWAR_EN | sz | 352 POWAR_IO_READ | POWAR_IO_WRITE); 353 } else { 354 out_be32(&po->powar, POWAR_EN | sz | 355 POWAR_MEM_READ | POWAR_MEM_WRITE); 356 out_lo = min(start, out_lo); 357 out_hi = max(end, out_hi); 358 } 359 po++; 360 } 361 } 362 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi); 363 364 /* setup PCSRBAR/PEXCSRBAR */ 365 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); 366 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 367 pcicsrbar_sz = ~pcicsrbar_sz + 1; 368 369 if (out_hi < (0x100000000ull - pcicsrbar_sz) || 370 (out_lo > 0x100000000ull)) 371 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 372 else 373 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz; 374 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar); 375 376 out_lo = min(out_lo, (u64)pcicsrbar); 377 378 debug("PCICSRBAR @ 0x%x\n", pcicsrbar); 379 380 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS, 381 pcicsrbar_sz, PCI_REGION_SYS_MEMORY); 382 hose->region_count++; 383 384 /* see if we are a PCIe or PCI controller */ 385 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 386 387 #ifdef CONFIG_FSL_CORENET 388 /* boot from PCIE --master */ 389 char *s = getenv("bootmaster"); 390 char pcie[6]; 391 sprintf(pcie, "PCIE%d", pci_info->pci_num); 392 393 if (s && (strcmp(s, pcie) == 0)) { 394 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n", 395 pci_info->pci_num); 396 fsl_pcie_boot_master((pit_t *)pi); 397 } else { 398 /* inbound */ 399 inbound = fsl_pci_setup_inbound_windows(hose, 400 out_lo, pcie_cap, pi); 401 } 402 #else 403 /* inbound */ 404 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi); 405 #endif 406 407 for (r = 0; r < hose->region_count; r++) 408 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r, 409 (u64)hose->regions[r].phys_start, 410 (u64)hose->regions[r].bus_start, 411 (u64)hose->regions[r].size, 412 hose->regions[r].flags); 413 414 pci_register_hose(hose); 415 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 416 hose->current_busno = hose->first_busno; 417 418 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */ 419 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except 420 * - Master abort (pci) 421 * - Master PERR (pci) 422 * - ICCA (PCIe) 423 */ 424 pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32); 425 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 426 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); 427 428 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) 429 temp32 = 0; 430 pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32); 431 temp32 &= ~0x03; /* Disable ASPM */ 432 pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32); 433 udelay(1); 434 #endif 435 if (pcie_cap == PCI_CAP_ID_EXP) { 436 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 437 enabled = ltssm >= PCI_LTSSM_L0; 438 439 #ifdef CONFIG_FSL_PCIE_RESET 440 if (ltssm == 1) { 441 int i; 442 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm); 443 /* assert PCIe reset */ 444 setbits_be32(&pci->pdb_stat, 0x08000000); 445 (void) in_be32(&pci->pdb_stat); 446 udelay(100); 447 debug(" Asserting PCIe reset @%p = %x\n", 448 &pci->pdb_stat, in_be32(&pci->pdb_stat)); 449 /* clear PCIe reset */ 450 clrbits_be32(&pci->pdb_stat, 0x08000000); 451 asm("sync;isync"); 452 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { 453 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 454 <ssm); 455 udelay(1000); 456 debug("....PCIe link error. " 457 "LTSSM=0x%02x.\n", ltssm); 458 } 459 enabled = ltssm >= PCI_LTSSM_L0; 460 461 /* we need to re-write the bar0 since a reset will 462 * clear it 463 */ 464 pci_hose_write_config_dword(hose, dev, 465 PCI_BASE_ADDRESS_0, pcicsrbar); 466 } 467 #endif 468 469 if (!enabled) { 470 /* Let the user know there's no PCIe link */ 471 printf("no link, regs @ 0x%lx\n", pci_info->regs); 472 hose->last_busno = hose->first_busno; 473 return; 474 } 475 476 out_be32(&pci->pme_msg_det, 0xffffffff); 477 out_be32(&pci->pme_msg_int_en, 0xffffffff); 478 479 /* Print the negotiated PCIe link width */ 480 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); 481 printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, 482 pci_info->regs); 483 484 hose->current_busno++; /* Start scan with secondary */ 485 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 486 } 487 488 /* Use generic setup_device to initialize standard pci regs, 489 * but do not allocate any windows since any BAR found (such 490 * as PCSRBAR) is not in this cpu's memory space. 491 */ 492 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 493 hose->pci_prefetch, hose->pci_io); 494 495 if (inbound) { 496 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 497 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 498 temp16 | PCI_COMMAND_MEMORY); 499 } 500 501 #ifndef CONFIG_PCI_NOSCAN 502 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); 503 504 /* Programming Interface (PCI_CLASS_PROG) 505 * 0 == pci host or pcie root-complex, 506 * 1 == pci agent or pcie end-point 507 */ 508 if (!temp8) { 509 debug(" Scanning PCI bus %02x\n", 510 hose->current_busno); 511 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); 512 } else { 513 debug(" Not scanning PCI bus %02x. PI=%x\n", 514 hose->current_busno, temp8); 515 hose->last_busno = hose->current_busno; 516 } 517 518 /* if we are PCIe - update limit regs and subordinate busno 519 * for the virtual P2P bridge 520 */ 521 if (pcie_cap == PCI_CAP_ID_EXP) { 522 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 523 } 524 #else 525 hose->last_busno = hose->current_busno; 526 #endif 527 528 /* Clear all error indications */ 529 if (pcie_cap == PCI_CAP_ID_EXP) 530 out_be32(&pci->pme_msg_det, 0xffffffff); 531 out_be32(&pci->pedr, 0xffffffff); 532 533 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); 534 if (temp16) { 535 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff); 536 } 537 538 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 539 if (temp16) { 540 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 541 } 542 } 543 544 int fsl_is_pci_agent(struct pci_controller *hose) 545 { 546 u8 prog_if; 547 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 548 549 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); 550 551 return (prog_if == FSL_PROG_IF_AGENT); 552 } 553 554 int fsl_pci_init_port(struct fsl_pci_info *pci_info, 555 struct pci_controller *hose, int busno) 556 { 557 volatile ccsr_fsl_pci_t *pci; 558 struct pci_region *r; 559 pci_dev_t dev = PCI_BDF(busno,0,0); 560 u8 pcie_cap; 561 562 pci = (ccsr_fsl_pci_t *) pci_info->regs; 563 564 /* on non-PCIe controllers we don't have pme_msg_det so this code 565 * should do nothing since the read will return 0 566 */ 567 if (in_be32(&pci->pme_msg_det)) { 568 out_be32(&pci->pme_msg_det, 0xffffffff); 569 debug (" with errors. Clearing. Now 0x%08x", 570 pci->pme_msg_det); 571 } 572 573 r = hose->regions + hose->region_count; 574 575 /* outbound memory */ 576 pci_set_region(r++, 577 pci_info->mem_bus, 578 pci_info->mem_phys, 579 pci_info->mem_size, 580 PCI_REGION_MEM); 581 582 /* outbound io */ 583 pci_set_region(r++, 584 pci_info->io_bus, 585 pci_info->io_phys, 586 pci_info->io_size, 587 PCI_REGION_IO); 588 589 hose->region_count = r - hose->regions; 590 hose->first_busno = busno; 591 592 fsl_pci_init(hose, pci_info); 593 594 if (fsl_is_pci_agent(hose)) { 595 fsl_pci_config_unlock(hose); 596 hose->last_busno = hose->first_busno; 597 #ifdef CONFIG_FSL_CORENET 598 } else { 599 /* boot from PCIE --master releases slave's core 0 */ 600 char *s = getenv("bootmaster"); 601 char pcie[6]; 602 sprintf(pcie, "PCIE%d", pci_info->pci_num); 603 604 if (s && (strcmp(s, pcie) == 0)) 605 fsl_pcie_boot_master_release_slave(pci_info->pci_num); 606 #endif 607 } 608 609 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 610 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? 611 "e" : "", pci_info->pci_num, 612 hose->first_busno, hose->last_busno); 613 614 return(hose->last_busno + 1); 615 } 616 617 /* Enable inbound PCI config cycles for agent/endpoint interface */ 618 void fsl_pci_config_unlock(struct pci_controller *hose) 619 { 620 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); 621 u8 agent; 622 u8 pcie_cap; 623 u16 pbfr; 624 625 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent); 626 if (!agent) 627 return; 628 629 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 630 if (pcie_cap != 0x0) { 631 /* PCIe - set CFG_READY bit of Configuration Ready Register */ 632 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); 633 } else { 634 /* PCI - clear ACL bit of PBFR */ 635 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); 636 pbfr &= ~0x20; 637 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr); 638 } 639 } 640 641 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \ 642 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4) 643 int fsl_configure_pcie(struct fsl_pci_info *info, 644 struct pci_controller *hose, 645 const char *connected, int busno) 646 { 647 int is_endpoint; 648 649 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); 650 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); 651 652 is_endpoint = fsl_setup_hose(hose, info->regs); 653 printf("PCIe%u: %s", info->pci_num, 654 is_endpoint ? "Endpoint" : "Root Complex"); 655 if (connected) 656 printf(" of %s", connected); 657 puts(", "); 658 659 return fsl_pci_init_port(info, hose, busno); 660 } 661 662 #if defined(CONFIG_FSL_CORENET) 663 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1 664 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2 665 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3 666 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4 667 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 668 #elif defined(CONFIG_MPC85xx) 669 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE 670 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 671 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 672 #define _DEVDISR_PCIE4 0 673 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 674 #elif defined(CONFIG_MPC86xx) 675 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1 676 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2 677 #define _DEVDISR_PCIE3 0 678 #define _DEVDISR_PCIE4 0 679 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ 680 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) 681 #else 682 #error "No defines for DEVDISR_PCIE" 683 #endif 684 685 /* Implement a dummy function for those platforms w/o SERDES */ 686 static const char *__board_serdes_name(enum srds_prtcl device) 687 { 688 switch (device) { 689 #ifdef CONFIG_SYS_PCIE1_NAME 690 case PCIE1: 691 return CONFIG_SYS_PCIE1_NAME; 692 #endif 693 #ifdef CONFIG_SYS_PCIE2_NAME 694 case PCIE2: 695 return CONFIG_SYS_PCIE2_NAME; 696 #endif 697 #ifdef CONFIG_SYS_PCIE3_NAME 698 case PCIE3: 699 return CONFIG_SYS_PCIE3_NAME; 700 #endif 701 #ifdef CONFIG_SYS_PCIE4_NAME 702 case PCIE4: 703 return CONFIG_SYS_PCIE4_NAME; 704 #endif 705 default: 706 return NULL; 707 } 708 709 return NULL; 710 } 711 712 __attribute__((weak, alias("__board_serdes_name"))) const char * 713 board_serdes_name(enum srds_prtcl device); 714 715 static u32 devdisr_mask[] = { 716 _DEVDISR_PCIE1, 717 _DEVDISR_PCIE2, 718 _DEVDISR_PCIE3, 719 _DEVDISR_PCIE4, 720 }; 721 722 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 723 struct fsl_pci_info *pci_info) 724 { 725 struct pci_controller *hose; 726 int num = dev - PCIE1; 727 728 hose = calloc(1, sizeof(struct pci_controller)); 729 if (!hose) 730 return busno; 731 732 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) { 733 busno = fsl_configure_pcie(pci_info, hose, 734 board_serdes_name(dev), busno); 735 } else { 736 printf("PCIe%d: disabled\n", num + 1); 737 } 738 739 return busno; 740 } 741 742 int fsl_pcie_init_board(int busno) 743 { 744 struct fsl_pci_info pci_info; 745 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; 746 u32 devdisr = in_be32(&gur->devdisr); 747 748 #ifdef CONFIG_PCIE1 749 SET_STD_PCIE_INFO(pci_info, 1); 750 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); 751 #else 752 setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ 753 #endif 754 755 #ifdef CONFIG_PCIE2 756 SET_STD_PCIE_INFO(pci_info, 2); 757 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info); 758 #else 759 setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ 760 #endif 761 762 #ifdef CONFIG_PCIE3 763 SET_STD_PCIE_INFO(pci_info, 3); 764 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info); 765 #else 766 setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */ 767 #endif 768 769 #ifdef CONFIG_PCIE4 770 SET_STD_PCIE_INFO(pci_info, 4); 771 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info); 772 #else 773 setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */ 774 #endif 775 776 return busno; 777 } 778 #else 779 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 780 struct fsl_pci_info *pci_info) 781 { 782 return busno; 783 } 784 785 int fsl_pcie_init_board(int busno) 786 { 787 return busno; 788 } 789 #endif 790 791 #ifdef CONFIG_OF_BOARD_SETUP 792 #include <libfdt.h> 793 #include <fdt_support.h> 794 795 void ft_fsl_pci_setup(void *blob, const char *pci_compat, 796 unsigned long ctrl_addr) 797 { 798 int off; 799 u32 bus_range[2]; 800 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr; 801 struct pci_controller *hose; 802 803 hose = find_hose_by_cfg_addr((void *)(ctrl_addr)); 804 805 /* convert ctrl_addr to true physical address */ 806 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR; 807 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS; 808 809 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr); 810 811 if (off < 0) 812 return; 813 814 /* We assume a cfg_addr not being set means we didn't setup the controller */ 815 if ((hose == NULL) || (hose->cfg_addr == NULL)) { 816 fdt_del_node(blob, off); 817 } else { 818 bus_range[0] = 0; 819 bus_range[1] = hose->last_busno - hose->first_busno; 820 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); 821 fdt_pci_dma_ranges(blob, off, hose); 822 } 823 } 824 #endif 825