1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 /* 24 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 25 * 26 * Initialize controller and call the common driver/pci pci_hose_scan to 27 * scan for bridges and devices. 28 * 29 * Hose fields which need to be pre-initialized by board specific code: 30 * regions[] 31 * first_busno 32 * 33 * Fields updated: 34 * last_busno 35 */ 36 37 #include <pci.h> 38 #include <asm/io.h> 39 #include <asm/fsl_pci.h> 40 41 /* Freescale-specific PCI config registers */ 42 #define FSL_PCI_PBFR 0x44 43 #define FSL_PCIE_CAP_ID 0x4c 44 #define FSL_PCIE_CFG_RDY 0x4b0 45 46 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 47 pci_dev_t dev, int sub_bus); 48 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 49 pci_dev_t dev, int sub_bus); 50 void pciauto_config_init(struct pci_controller *hose); 51 52 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 53 #define CONFIG_SYS_PCI_MEMORY_BUS 0 54 #endif 55 56 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 57 #define CONFIG_SYS_PCI_MEMORY_PHYS 0 58 #endif 59 60 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) 61 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) 62 #endif 63 64 /* Setup one inbound ATMU window. 65 * 66 * We let the caller decide what the window size should be 67 */ 68 static void set_inbound_window(volatile pit_t *pi, 69 struct pci_region *r, 70 u64 size) 71 { 72 u32 sz = (__ilog2_u64(size) - 1); 73 u32 flag = PIWAR_EN | PIWAR_LOCAL | 74 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 75 76 out_be32(&pi->pitar, r->phys_start >> 12); 77 out_be32(&pi->piwbar, r->bus_start >> 12); 78 #ifdef CONFIG_SYS_PCI_64BIT 79 out_be32(&pi->piwbear, r->bus_start >> 44); 80 #else 81 out_be32(&pi->piwbear, 0); 82 #endif 83 if (r->flags & PCI_REGION_PREFETCH) 84 flag |= PIWAR_PF; 85 out_be32(&pi->piwar, flag | sz); 86 } 87 88 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, 89 u64 out_lo, u8 pcie_cap, 90 volatile pit_t *pi) 91 { 92 struct pci_region *r = hose->regions + hose->region_count; 93 u64 sz = min((u64)gd->ram_size, (1ull << 32)); 94 95 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; 96 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; 97 pci_size_t pci_sz; 98 99 /* we have no space available for inbound memory mapping */ 100 if (bus_start > out_lo) { 101 printf ("no space for inbound mapping of memory\n"); 102 return 0; 103 } 104 105 /* limit size */ 106 if ((bus_start + sz) > out_lo) { 107 sz = out_lo - bus_start; 108 debug ("limiting size to %llx\n", sz); 109 } 110 111 pci_sz = 1ull << __ilog2_u64(sz); 112 /* 113 * we can overlap inbound/outbound windows on PCI-E since RX & TX 114 * links a separate 115 */ 116 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) { 117 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 118 (u64)bus_start, (u64)phys_start, (u64)sz); 119 pci_set_region(r, bus_start, phys_start, sz, 120 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 121 PCI_REGION_PREFETCH); 122 123 /* if we aren't an exact power of two match, pci_sz is smaller 124 * round it up to the next power of two. We report the actual 125 * size to pci region tracking. 126 */ 127 if (pci_sz != sz) 128 sz = 2ull << __ilog2_u64(sz); 129 130 set_inbound_window(pi--, r++, sz); 131 sz = 0; /* make sure we dont set the R2 window */ 132 } else { 133 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 134 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 135 pci_set_region(r, bus_start, phys_start, pci_sz, 136 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 137 PCI_REGION_PREFETCH); 138 set_inbound_window(pi--, r++, pci_sz); 139 140 sz -= pci_sz; 141 bus_start += pci_sz; 142 phys_start += pci_sz; 143 144 pci_sz = 1ull << __ilog2_u64(sz); 145 if (sz) { 146 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", 147 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 148 pci_set_region(r, bus_start, phys_start, pci_sz, 149 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 150 PCI_REGION_PREFETCH); 151 set_inbound_window(pi--, r++, pci_sz); 152 sz -= pci_sz; 153 bus_start += pci_sz; 154 phys_start += pci_sz; 155 } 156 } 157 158 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) 159 /* 160 * On 64-bit capable systems, set up a mapping for all of DRAM 161 * in high pci address space. 162 */ 163 pci_sz = 1ull << __ilog2_u64(gd->ram_size); 164 /* round up to the next largest power of two */ 165 if (gd->ram_size > pci_sz) 166 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); 167 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", 168 (u64)CONFIG_SYS_PCI64_MEMORY_BUS, 169 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, 170 (u64)pci_sz); 171 pci_set_region(r, 172 CONFIG_SYS_PCI64_MEMORY_BUS, 173 CONFIG_SYS_PCI_MEMORY_PHYS, 174 pci_sz, 175 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 176 PCI_REGION_PREFETCH); 177 set_inbound_window(pi--, r++, pci_sz); 178 #else 179 pci_sz = 1ull << __ilog2_u64(sz); 180 if (sz) { 181 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", 182 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 183 pci_set_region(r, bus_start, phys_start, pci_sz, 184 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 185 PCI_REGION_PREFETCH); 186 sz -= pci_sz; 187 bus_start += pci_sz; 188 phys_start += pci_sz; 189 set_inbound_window(pi--, r++, pci_sz); 190 } 191 #endif 192 193 #ifdef CONFIG_PHYS_64BIT 194 if (sz && (((u64)gd->ram_size) < (1ull << 32))) 195 printf("Was not able to map all of memory via " 196 "inbound windows -- %lld remaining\n", sz); 197 #endif 198 199 hose->region_count = r - hose->regions; 200 201 return 1; 202 } 203 204 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) 205 { 206 u16 temp16; 207 u32 temp32; 208 int enabled, r, inbound = 0; 209 u16 ltssm; 210 u8 temp8, pcie_cap; 211 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; 212 struct pci_region *reg = hose->regions + hose->region_count; 213 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 214 215 /* Initialize ATMU registers based on hose regions and flags */ 216 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ 217 volatile pit_t *pi = &pci->pit[2]; /* ranges from: 3 to 1 */ 218 219 u64 out_hi = 0, out_lo = -1ULL; 220 u32 pcicsrbar, pcicsrbar_sz; 221 222 #ifdef DEBUG 223 int neg_link_w; 224 #endif 225 226 pci_setup_indirect(hose, cfg_addr, cfg_data); 227 228 /* Handle setup of outbound windows first */ 229 for (r = 0; r < hose->region_count; r++) { 230 unsigned long flags = hose->regions[r].flags; 231 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); 232 233 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE; 234 if (flags != PCI_REGION_SYS_MEMORY) { 235 u64 start = hose->regions[r].bus_start; 236 u64 end = start + hose->regions[r].size; 237 238 out_be32(&po->powbar, hose->regions[r].phys_start >> 12); 239 out_be32(&po->potar, start >> 12); 240 #ifdef CONFIG_SYS_PCI_64BIT 241 out_be32(&po->potear, start >> 44); 242 #else 243 out_be32(&po->potear, 0); 244 #endif 245 if (hose->regions[r].flags & PCI_REGION_IO) { 246 out_be32(&po->powar, POWAR_EN | sz | 247 POWAR_IO_READ | POWAR_IO_WRITE); 248 } else { 249 out_be32(&po->powar, POWAR_EN | sz | 250 POWAR_MEM_READ | POWAR_MEM_WRITE); 251 out_lo = min(start, out_lo); 252 out_hi = max(end, out_hi); 253 } 254 po++; 255 } 256 } 257 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi); 258 259 /* setup PCSRBAR/PEXCSRBAR */ 260 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); 261 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 262 pcicsrbar_sz = ~pcicsrbar_sz + 1; 263 264 if (out_hi < (0x100000000ull - pcicsrbar_sz) || 265 (out_lo > 0x100000000ull)) 266 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 267 else 268 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz; 269 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar); 270 271 out_lo = min(out_lo, (u64)pcicsrbar); 272 273 debug("PCICSRBAR @ 0x%x\n", pcicsrbar); 274 275 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS, 276 pcicsrbar_sz, PCI_REGION_SYS_MEMORY); 277 hose->region_count++; 278 279 /* see if we are a PCIe or PCI controller */ 280 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 281 282 /* inbound */ 283 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi); 284 285 for (r = 0; r < hose->region_count; r++) 286 debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r, 287 (u64)hose->regions[r].phys_start, 288 hose->regions[r].bus_start, 289 hose->regions[r].size, 290 hose->regions[r].flags); 291 292 pci_register_hose(hose); 293 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 294 hose->current_busno = hose->first_busno; 295 296 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */ 297 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except 298 * - Master abort (pci) 299 * - Master PERR (pci) 300 * - ICCA (PCIe) 301 */ 302 pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32); 303 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 304 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); 305 306 if (pcie_cap == PCI_CAP_ID_EXP) { 307 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 308 enabled = ltssm >= PCI_LTSSM_L0; 309 310 #ifdef CONFIG_FSL_PCIE_RESET 311 if (ltssm == 1) { 312 int i; 313 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm); 314 /* assert PCIe reset */ 315 setbits_be32(&pci->pdb_stat, 0x08000000); 316 (void) in_be32(&pci->pdb_stat); 317 udelay(100); 318 debug(" Asserting PCIe reset @%x = %x\n", 319 &pci->pdb_stat, in_be32(&pci->pdb_stat)); 320 /* clear PCIe reset */ 321 clrbits_be32(&pci->pdb_stat, 0x08000000); 322 asm("sync;isync"); 323 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { 324 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 325 <ssm); 326 udelay(1000); 327 debug("....PCIe link error. " 328 "LTSSM=0x%02x.\n", ltssm); 329 } 330 enabled = ltssm >= PCI_LTSSM_L0; 331 332 /* we need to re-write the bar0 since a reset will 333 * clear it 334 */ 335 pci_hose_write_config_dword(hose, dev, 336 PCI_BASE_ADDRESS_0, pcicsrbar); 337 } 338 #endif 339 340 if (!enabled) { 341 debug("....PCIE link error. Skipping scan." 342 "LTSSM=0x%02x\n", ltssm); 343 hose->last_busno = hose->first_busno; 344 return; 345 } 346 347 out_be32(&pci->pme_msg_det, 0xffffffff); 348 out_be32(&pci->pme_msg_int_en, 0xffffffff); 349 #ifdef DEBUG 350 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); 351 neg_link_w = (temp16 & 0x3f0 ) >> 4; 352 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", 353 ltssm, neg_link_w); 354 #endif 355 hose->current_busno++; /* Start scan with secondary */ 356 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 357 } 358 359 /* Use generic setup_device to initialize standard pci regs, 360 * but do not allocate any windows since any BAR found (such 361 * as PCSRBAR) is not in this cpu's memory space. 362 */ 363 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 364 hose->pci_prefetch, hose->pci_io); 365 366 if (inbound) { 367 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 368 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 369 temp16 | PCI_COMMAND_MEMORY); 370 } 371 372 #ifndef CONFIG_PCI_NOSCAN 373 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); 374 375 /* Programming Interface (PCI_CLASS_PROG) 376 * 0 == pci host or pcie root-complex, 377 * 1 == pci agent or pcie end-point 378 */ 379 if (!temp8) { 380 printf(" Scanning PCI bus %02x\n", 381 hose->current_busno); 382 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); 383 } else { 384 debug(" Not scanning PCI bus %02x. PI=%x\n", 385 hose->current_busno, temp8); 386 hose->last_busno = hose->current_busno; 387 } 388 389 /* if we are PCIe - update limit regs and subordinate busno 390 * for the virtual P2P bridge 391 */ 392 if (pcie_cap == PCI_CAP_ID_EXP) { 393 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 394 } 395 #else 396 hose->last_busno = hose->current_busno; 397 #endif 398 399 /* Clear all error indications */ 400 if (pcie_cap == PCI_CAP_ID_EXP) 401 out_be32(&pci->pme_msg_det, 0xffffffff); 402 out_be32(&pci->pedr, 0xffffffff); 403 404 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); 405 if (temp16) { 406 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff); 407 } 408 409 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 410 if (temp16) { 411 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 412 } 413 } 414 415 int fsl_pci_init_port(struct fsl_pci_info *pci_info, 416 struct pci_controller *hose, int busno) 417 { 418 volatile ccsr_fsl_pci_t *pci; 419 struct pci_region *r; 420 421 pci = (ccsr_fsl_pci_t *) pci_info->regs; 422 423 /* on non-PCIe controllers we don't have pme_msg_det so this code 424 * should do nothing since the read will return 0 425 */ 426 if (in_be32(&pci->pme_msg_det)) { 427 out_be32(&pci->pme_msg_det, 0xffffffff); 428 debug (" with errors. Clearing. Now 0x%08x", 429 pci->pme_msg_det); 430 } 431 432 r = hose->regions + hose->region_count; 433 434 /* outbound memory */ 435 pci_set_region(r++, 436 pci_info->mem_bus, 437 pci_info->mem_phys, 438 pci_info->mem_size, 439 PCI_REGION_MEM); 440 441 /* outbound io */ 442 pci_set_region(r++, 443 pci_info->io_bus, 444 pci_info->io_phys, 445 pci_info->io_size, 446 PCI_REGION_IO); 447 448 hose->region_count = r - hose->regions; 449 hose->first_busno = busno; 450 451 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 452 453 printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num, 454 hose->first_busno, hose->last_busno); 455 456 return(hose->last_busno + 1); 457 } 458 459 /* Enable inbound PCI config cycles for agent/endpoint interface */ 460 void fsl_pci_config_unlock(struct pci_controller *hose) 461 { 462 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); 463 u8 agent; 464 u8 pcie_cap; 465 u16 pbfr; 466 467 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent); 468 if (!agent) 469 return; 470 471 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 472 if (pcie_cap != 0x0) { 473 /* PCIe - set CFG_READY bit of Configuration Ready Register */ 474 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); 475 } else { 476 /* PCI - clear ACL bit of PBFR */ 477 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); 478 pbfr &= ~0x20; 479 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr); 480 } 481 } 482 483 #ifdef CONFIG_OF_BOARD_SETUP 484 #include <libfdt.h> 485 #include <fdt_support.h> 486 487 void ft_fsl_pci_setup(void *blob, const char *pci_alias, 488 struct pci_controller *hose) 489 { 490 int off = fdt_path_offset(blob, pci_alias); 491 492 if (off >= 0) { 493 u32 bus_range[2]; 494 495 bus_range[0] = 0; 496 bus_range[1] = hose->last_busno - hose->first_busno; 497 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); 498 fdt_pci_dma_ranges(blob, off, hose); 499 } 500 } 501 #endif 502