1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 /* 24 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 25 * 26 * Initialize controller and call the common driver/pci pci_hose_scan to 27 * scan for bridges and devices. 28 * 29 * Hose fields which need to be pre-initialized by board specific code: 30 * regions[] 31 * first_busno 32 * 33 * Fields updated: 34 * last_busno 35 */ 36 37 #include <pci.h> 38 #include <asm/immap_fsl_pci.h> 39 40 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 41 pci_dev_t dev, int sub_bus); 42 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 43 pci_dev_t dev, int sub_bus); 44 void pciauto_config_init(struct pci_controller *hose); 45 46 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 47 #define CONFIG_SYS_PCI_MEMORY_BUS 0 48 #endif 49 50 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 51 #define CONFIG_SYS_PCI_MEMORY_PHYS 0 52 #endif 53 54 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) 55 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) 56 #endif 57 58 int fsl_pci_setup_inbound_windows(struct pci_region *r) 59 { 60 struct pci_region *rgn_base = r; 61 u64 sz = min((u64)gd->ram_size, 1ull << 32); 62 63 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; 64 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; 65 pci_size_t pci_sz = 1ull << __ilog2_u64(sz); 66 67 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 68 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 69 pci_set_region(r++, bus_start, phys_start, pci_sz, 70 PCI_REGION_MEM | PCI_REGION_MEMORY | 71 PCI_REGION_PREFETCH); 72 73 sz -= pci_sz; 74 bus_start += pci_sz; 75 phys_start += pci_sz; 76 77 pci_sz = 1ull << __ilog2_u64(sz); 78 if (sz) { 79 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", 80 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 81 pci_set_region(r++, bus_start, phys_start, pci_sz, 82 PCI_REGION_MEM | PCI_REGION_MEMORY | 83 PCI_REGION_PREFETCH); 84 sz -= pci_sz; 85 bus_start += pci_sz; 86 phys_start += pci_sz; 87 } 88 89 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) 90 /* 91 * On 64-bit capable systems, set up a mapping for all of DRAM 92 * in high pci address space. 93 */ 94 pci_sz = 1ull << __ilog2_u64(gd->ram_size); 95 /* round up to the next largest power of two */ 96 if (gd->ram_size > pci_sz) 97 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); 98 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", 99 (u64)CONFIG_SYS_PCI64_MEMORY_BUS, 100 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, 101 (u64)pci_sz); 102 pci_set_region(r++, 103 CONFIG_SYS_PCI64_MEMORY_BUS, 104 CONFIG_SYS_PCI_MEMORY_PHYS, 105 pci_sz, 106 PCI_REGION_MEM | PCI_REGION_MEMORY | 107 PCI_REGION_PREFETCH); 108 #else 109 pci_sz = 1ull << __ilog2_u64(sz); 110 if (sz) { 111 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", 112 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 113 pci_set_region(r++, bus_start, phys_start, pci_sz, 114 PCI_REGION_MEM | PCI_REGION_MEMORY | 115 PCI_REGION_PREFETCH); 116 sz -= pci_sz; 117 bus_start += pci_sz; 118 phys_start += pci_sz; 119 } 120 #endif 121 122 if (sz && (((u64)gd->ram_size) < (1ull << 32))) 123 printf("Was not able to map all of memory via " 124 "inbound windows -- %lld remaining\n", sz); 125 126 return r - rgn_base; 127 } 128 129 void fsl_pci_init(struct pci_controller *hose) 130 { 131 u16 temp16; 132 u32 temp32; 133 int busno = hose->first_busno; 134 int enabled; 135 u16 ltssm; 136 u8 temp8; 137 int r; 138 int bridge; 139 int inbound = 0; 140 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; 141 pci_dev_t dev = PCI_BDF(busno,0,0); 142 143 /* Initialize ATMU registers based on hose regions and flags */ 144 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ 145 volatile pit_t *pi = &pci->pit[0]; /* ranges from: 3 to 1 */ 146 147 #ifdef DEBUG 148 int neg_link_w; 149 #endif 150 151 for (r=0; r<hose->region_count; r++) { 152 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); 153 if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */ 154 u32 flag = PIWAR_EN | PIWAR_LOCAL | 155 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 156 pi->pitar = (hose->regions[r].phys_start >> 12); 157 pi->piwbar = (hose->regions[r].bus_start >> 12); 158 #ifdef CONFIG_SYS_PCI_64BIT 159 pi->piwbear = (hose->regions[r].bus_start >> 44); 160 #else 161 pi->piwbear = 0; 162 #endif 163 if (hose->regions[r].flags & PCI_REGION_PREFETCH) 164 flag |= PIWAR_PF; 165 pi->piwar = flag | sz; 166 pi++; 167 inbound = hose->regions[r].size > 0; 168 } else { /* Outbound */ 169 po->powbar = (hose->regions[r].phys_start >> 12); 170 po->potar = (hose->regions[r].bus_start >> 12); 171 #ifdef CONFIG_SYS_PCI_64BIT 172 po->potear = (hose->regions[r].bus_start >> 44); 173 #else 174 po->potear = 0; 175 #endif 176 if (hose->regions[r].flags & PCI_REGION_IO) 177 po->powar = POWAR_EN | sz | 178 POWAR_IO_READ | POWAR_IO_WRITE; 179 else 180 po->powar = POWAR_EN | sz | 181 POWAR_MEM_READ | POWAR_MEM_WRITE; 182 po++; 183 } 184 } 185 186 pci_register_hose(hose); 187 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 188 hose->current_busno = hose->first_busno; 189 190 pci->pedr = 0xffffffff; /* Clear any errors */ 191 pci->peer = ~0x20140; /* Enable All Error Interupts except 192 * - Master abort (pci) 193 * - Master PERR (pci) 194 * - ICCA (PCIe) 195 */ 196 pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32); 197 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 198 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); 199 200 pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8); 201 bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */ 202 203 if ( bridge ) { 204 205 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 206 enabled = ltssm >= PCI_LTSSM_L0; 207 208 #ifdef CONFIG_FSL_PCIE_RESET 209 if (ltssm == 1) { 210 int i; 211 debug("....PCIe link error. " 212 "LTSSM=0x%02x.", ltssm); 213 pci->pdb_stat |= 0x08000000; /* assert PCIe reset */ 214 temp32 = pci->pdb_stat; 215 udelay(100); 216 debug(" Asserting PCIe reset @%x = %x\n", 217 &pci->pdb_stat, pci->pdb_stat); 218 pci->pdb_stat &= ~0x08000000; /* clear reset */ 219 asm("sync;isync"); 220 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { 221 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 222 <ssm); 223 udelay(1000); 224 debug("....PCIe link error. " 225 "LTSSM=0x%02x.\n", ltssm); 226 } 227 enabled = ltssm >= PCI_LTSSM_L0; 228 } 229 #endif 230 231 if (!enabled) { 232 debug("....PCIE link error. Skipping scan." 233 "LTSSM=0x%02x\n", ltssm); 234 hose->last_busno = hose->first_busno; 235 return; 236 } 237 238 pci->pme_msg_det = 0xffffffff; 239 pci->pme_msg_int_en = 0xffffffff; 240 #ifdef DEBUG 241 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); 242 neg_link_w = (temp16 & 0x3f0 ) >> 4; 243 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", 244 ltssm, neg_link_w); 245 #endif 246 hose->current_busno++; /* Start scan with secondary */ 247 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 248 249 } 250 251 /* Use generic setup_device to initialize standard pci regs, 252 * but do not allocate any windows since any BAR found (such 253 * as PCSRBAR) is not in this cpu's memory space. 254 */ 255 256 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 257 hose->pci_prefetch, hose->pci_io); 258 259 if (inbound) { 260 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 261 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 262 temp16 | PCI_COMMAND_MEMORY); 263 } 264 265 #ifndef CONFIG_PCI_NOSCAN 266 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); 267 268 /* Programming Interface (PCI_CLASS_PROG) 269 * 0 == pci host or pcie root-complex, 270 * 1 == pci agent or pcie end-point 271 */ 272 if (!temp8) { 273 printf(" Scanning PCI bus %02x\n", 274 hose->current_busno); 275 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); 276 } else { 277 debug(" Not scanning PCI bus %02x. PI=%x\n", 278 hose->current_busno, temp8); 279 hose->last_busno = hose->current_busno; 280 } 281 282 if ( bridge ) { /* update limit regs and subordinate busno */ 283 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 284 } 285 #else 286 hose->last_busno = hose->current_busno; 287 #endif 288 289 /* Clear all error indications */ 290 291 if (bridge) 292 pci->pme_msg_det = 0xffffffff; 293 pci->pedr = 0xffffffff; 294 295 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); 296 if (temp16) { 297 pci_hose_write_config_word(hose, dev, 298 PCI_DSR, 0xffff); 299 } 300 301 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 302 if (temp16) { 303 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 304 } 305 } 306 307 #ifdef CONFIG_OF_BOARD_SETUP 308 #include <libfdt.h> 309 #include <fdt_support.h> 310 311 void ft_fsl_pci_setup(void *blob, const char *pci_alias, 312 struct pci_controller *hose) 313 { 314 int off = fdt_path_offset(blob, pci_alias); 315 316 if (off >= 0) { 317 u32 bus_range[2]; 318 319 bus_range[0] = 0; 320 bus_range[1] = hose->last_busno - hose->first_busno; 321 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); 322 fdt_pci_dma_ranges(blob, off, hose); 323 } 324 } 325 #endif 326