1 /* 2 * Copyright 2007-2012 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <malloc.h> 22 #include <asm/fsl_serdes.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* 27 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 28 * 29 * Initialize controller and call the common driver/pci pci_hose_scan to 30 * scan for bridges and devices. 31 * 32 * Hose fields which need to be pre-initialized by board specific code: 33 * regions[] 34 * first_busno 35 * 36 * Fields updated: 37 * last_busno 38 */ 39 40 #include <pci.h> 41 #include <asm/io.h> 42 #include <asm/fsl_pci.h> 43 44 /* Freescale-specific PCI config registers */ 45 #define FSL_PCI_PBFR 0x44 46 #define FSL_PCIE_CAP_ID 0x4c 47 #define FSL_PCIE_CFG_RDY 0x4b0 48 #define FSL_PROG_IF_AGENT 0x1 49 50 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 51 #define CONFIG_SYS_PCI_MEMORY_BUS 0 52 #endif 53 54 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 55 #define CONFIG_SYS_PCI_MEMORY_PHYS 0 56 #endif 57 58 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) 59 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) 60 #endif 61 62 /* Setup one inbound ATMU window. 63 * 64 * We let the caller decide what the window size should be 65 */ 66 static void set_inbound_window(volatile pit_t *pi, 67 struct pci_region *r, 68 u64 size) 69 { 70 u32 sz = (__ilog2_u64(size) - 1); 71 u32 flag = PIWAR_EN | PIWAR_LOCAL | 72 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 73 74 out_be32(&pi->pitar, r->phys_start >> 12); 75 out_be32(&pi->piwbar, r->bus_start >> 12); 76 #ifdef CONFIG_SYS_PCI_64BIT 77 out_be32(&pi->piwbear, r->bus_start >> 44); 78 #else 79 out_be32(&pi->piwbear, 0); 80 #endif 81 if (r->flags & PCI_REGION_PREFETCH) 82 flag |= PIWAR_PF; 83 out_be32(&pi->piwar, flag | sz); 84 } 85 86 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) 87 { 88 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr; 89 90 /* Reset hose to make sure its in a clean state */ 91 memset(hose, 0, sizeof(struct pci_controller)); 92 93 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 94 95 return fsl_is_pci_agent(hose); 96 } 97 98 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, 99 u64 out_lo, u8 pcie_cap, 100 volatile pit_t *pi) 101 { 102 struct pci_region *r = hose->regions + hose->region_count; 103 u64 sz = min((u64)gd->ram_size, (1ull << 32)); 104 105 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; 106 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; 107 pci_size_t pci_sz; 108 109 /* we have no space available for inbound memory mapping */ 110 if (bus_start > out_lo) { 111 printf ("no space for inbound mapping of memory\n"); 112 return 0; 113 } 114 115 /* limit size */ 116 if ((bus_start + sz) > out_lo) { 117 sz = out_lo - bus_start; 118 debug ("limiting size to %llx\n", sz); 119 } 120 121 pci_sz = 1ull << __ilog2_u64(sz); 122 /* 123 * we can overlap inbound/outbound windows on PCI-E since RX & TX 124 * links a separate 125 */ 126 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) { 127 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 128 (u64)bus_start, (u64)phys_start, (u64)sz); 129 pci_set_region(r, bus_start, phys_start, sz, 130 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 131 PCI_REGION_PREFETCH); 132 133 /* if we aren't an exact power of two match, pci_sz is smaller 134 * round it up to the next power of two. We report the actual 135 * size to pci region tracking. 136 */ 137 if (pci_sz != sz) 138 sz = 2ull << __ilog2_u64(sz); 139 140 set_inbound_window(pi--, r++, sz); 141 sz = 0; /* make sure we dont set the R2 window */ 142 } else { 143 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 144 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 145 pci_set_region(r, bus_start, phys_start, pci_sz, 146 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 147 PCI_REGION_PREFETCH); 148 set_inbound_window(pi--, r++, pci_sz); 149 150 sz -= pci_sz; 151 bus_start += pci_sz; 152 phys_start += pci_sz; 153 154 pci_sz = 1ull << __ilog2_u64(sz); 155 if (sz) { 156 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", 157 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 158 pci_set_region(r, bus_start, phys_start, pci_sz, 159 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 160 PCI_REGION_PREFETCH); 161 set_inbound_window(pi--, r++, pci_sz); 162 sz -= pci_sz; 163 bus_start += pci_sz; 164 phys_start += pci_sz; 165 } 166 } 167 168 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) 169 /* 170 * On 64-bit capable systems, set up a mapping for all of DRAM 171 * in high pci address space. 172 */ 173 pci_sz = 1ull << __ilog2_u64(gd->ram_size); 174 /* round up to the next largest power of two */ 175 if (gd->ram_size > pci_sz) 176 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); 177 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", 178 (u64)CONFIG_SYS_PCI64_MEMORY_BUS, 179 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, 180 (u64)pci_sz); 181 pci_set_region(r, 182 CONFIG_SYS_PCI64_MEMORY_BUS, 183 CONFIG_SYS_PCI_MEMORY_PHYS, 184 pci_sz, 185 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 186 PCI_REGION_PREFETCH); 187 set_inbound_window(pi--, r++, pci_sz); 188 #else 189 pci_sz = 1ull << __ilog2_u64(sz); 190 if (sz) { 191 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", 192 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 193 pci_set_region(r, bus_start, phys_start, pci_sz, 194 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 195 PCI_REGION_PREFETCH); 196 sz -= pci_sz; 197 bus_start += pci_sz; 198 phys_start += pci_sz; 199 set_inbound_window(pi--, r++, pci_sz); 200 } 201 #endif 202 203 #ifdef CONFIG_PHYS_64BIT 204 if (sz && (((u64)gd->ram_size) < (1ull << 32))) 205 printf("Was not able to map all of memory via " 206 "inbound windows -- %lld remaining\n", sz); 207 #endif 208 209 hose->region_count = r - hose->regions; 210 211 return 1; 212 } 213 214 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 215 static void fsl_pcie_boot_master(pit_t *pi) 216 { 217 /* configure inbound window for slave's u-boot image */ 218 debug("PCIEBOOT - MASTER: Inbound window for slave's image; " 219 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", 220 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 221 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, 222 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 223 struct pci_region r_inbound; 224 u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE) 225 - 1; 226 pci_set_region(&r_inbound, 227 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, 228 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 229 sz_inbound, 230 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 231 232 set_inbound_window(pi--, &r_inbound, 233 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 234 235 /* configure inbound window for slave's u-boot image */ 236 debug("PCIEBOOT - MASTER: Inbound window for slave's image; " 237 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", 238 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 239 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, 240 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 241 pci_set_region(&r_inbound, 242 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, 243 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 244 sz_inbound, 245 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 246 247 set_inbound_window(pi--, &r_inbound, 248 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 249 250 /* configure inbound window for slave's ucode and ENV */ 251 debug("PCIEBOOT - MASTER: Inbound window for slave's " 252 "ucode and ENV; " 253 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", 254 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, 255 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, 256 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); 257 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE) 258 - 1; 259 pci_set_region(&r_inbound, 260 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, 261 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, 262 sz_inbound, 263 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 264 265 set_inbound_window(pi--, &r_inbound, 266 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); 267 } 268 269 static void fsl_pcie_boot_master_release_slave(int port) 270 { 271 unsigned long release_addr; 272 273 /* now release slave's core 0 */ 274 switch (port) { 275 case 1: 276 release_addr = CONFIG_SYS_PCIE1_MEM_VIRT 277 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; 278 break; 279 #ifdef CONFIG_SYS_PCIE2_MEM_VIRT 280 case 2: 281 release_addr = CONFIG_SYS_PCIE2_MEM_VIRT 282 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; 283 break; 284 #endif 285 #ifdef CONFIG_SYS_PCIE3_MEM_VIRT 286 case 3: 287 release_addr = CONFIG_SYS_PCIE3_MEM_VIRT 288 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; 289 break; 290 #endif 291 default: 292 release_addr = 0; 293 break; 294 } 295 if (release_addr != 0) { 296 out_be32((void *)release_addr, 297 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); 298 debug("PCIEBOOT - MASTER: " 299 "Release slave successfully! Now the slave should start up!\n"); 300 } else { 301 debug("PCIEBOOT - MASTER: " 302 "Release slave failed!\n"); 303 } 304 } 305 #endif 306 307 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) 308 { 309 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; 310 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; 311 u16 temp16; 312 u32 temp32; 313 u32 block_rev; 314 int enabled, r, inbound = 0; 315 u16 ltssm; 316 u8 temp8, pcie_cap; 317 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; 318 struct pci_region *reg = hose->regions + hose->region_count; 319 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 320 321 /* Initialize ATMU registers based on hose regions and flags */ 322 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ 323 volatile pit_t *pi; 324 325 u64 out_hi = 0, out_lo = -1ULL; 326 u32 pcicsrbar, pcicsrbar_sz; 327 328 pci_setup_indirect(hose, cfg_addr, cfg_data); 329 330 block_rev = in_be32(&pci->block_rev1); 331 if (PEX_IP_BLK_REV_2_2 <= block_rev) { 332 pi = &pci->pit[2]; /* 0xDC0 */ 333 } else { 334 pi = &pci->pit[3]; /* 0xDE0 */ 335 } 336 337 /* Handle setup of outbound windows first */ 338 for (r = 0; r < hose->region_count; r++) { 339 unsigned long flags = hose->regions[r].flags; 340 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); 341 342 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE; 343 if (flags != PCI_REGION_SYS_MEMORY) { 344 u64 start = hose->regions[r].bus_start; 345 u64 end = start + hose->regions[r].size; 346 347 out_be32(&po->powbar, hose->regions[r].phys_start >> 12); 348 out_be32(&po->potar, start >> 12); 349 #ifdef CONFIG_SYS_PCI_64BIT 350 out_be32(&po->potear, start >> 44); 351 #else 352 out_be32(&po->potear, 0); 353 #endif 354 if (hose->regions[r].flags & PCI_REGION_IO) { 355 out_be32(&po->powar, POWAR_EN | sz | 356 POWAR_IO_READ | POWAR_IO_WRITE); 357 } else { 358 out_be32(&po->powar, POWAR_EN | sz | 359 POWAR_MEM_READ | POWAR_MEM_WRITE); 360 out_lo = min(start, out_lo); 361 out_hi = max(end, out_hi); 362 } 363 po++; 364 } 365 } 366 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi); 367 368 /* setup PCSRBAR/PEXCSRBAR */ 369 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); 370 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 371 pcicsrbar_sz = ~pcicsrbar_sz + 1; 372 373 if (out_hi < (0x100000000ull - pcicsrbar_sz) || 374 (out_lo > 0x100000000ull)) 375 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 376 else 377 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz; 378 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar); 379 380 out_lo = min(out_lo, (u64)pcicsrbar); 381 382 debug("PCICSRBAR @ 0x%x\n", pcicsrbar); 383 384 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS, 385 pcicsrbar_sz, PCI_REGION_SYS_MEMORY); 386 hose->region_count++; 387 388 /* see if we are a PCIe or PCI controller */ 389 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 390 391 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 392 /* boot from PCIE --master */ 393 char *s = getenv("bootmaster"); 394 char pcie[6]; 395 sprintf(pcie, "PCIE%d", pci_info->pci_num); 396 397 if (s && (strcmp(s, pcie) == 0)) { 398 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n", 399 pci_info->pci_num); 400 fsl_pcie_boot_master((pit_t *)pi); 401 } else { 402 /* inbound */ 403 inbound = fsl_pci_setup_inbound_windows(hose, 404 out_lo, pcie_cap, pi); 405 } 406 #else 407 /* inbound */ 408 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi); 409 #endif 410 411 for (r = 0; r < hose->region_count; r++) 412 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r, 413 (u64)hose->regions[r].phys_start, 414 (u64)hose->regions[r].bus_start, 415 (u64)hose->regions[r].size, 416 hose->regions[r].flags); 417 418 pci_register_hose(hose); 419 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 420 hose->current_busno = hose->first_busno; 421 422 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */ 423 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except 424 * - Master abort (pci) 425 * - Master PERR (pci) 426 * - ICCA (PCIe) 427 */ 428 pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32); 429 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 430 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); 431 432 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) 433 temp32 = 0; 434 pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32); 435 temp32 &= ~0x03; /* Disable ASPM */ 436 pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32); 437 udelay(1); 438 #endif 439 if (pcie_cap == PCI_CAP_ID_EXP) { 440 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 441 enabled = ltssm >= PCI_LTSSM_L0; 442 443 #ifdef CONFIG_FSL_PCIE_RESET 444 if (ltssm == 1) { 445 int i; 446 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm); 447 /* assert PCIe reset */ 448 setbits_be32(&pci->pdb_stat, 0x08000000); 449 (void) in_be32(&pci->pdb_stat); 450 udelay(100); 451 debug(" Asserting PCIe reset @%p = %x\n", 452 &pci->pdb_stat, in_be32(&pci->pdb_stat)); 453 /* clear PCIe reset */ 454 clrbits_be32(&pci->pdb_stat, 0x08000000); 455 asm("sync;isync"); 456 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { 457 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 458 <ssm); 459 udelay(1000); 460 debug("....PCIe link error. " 461 "LTSSM=0x%02x.\n", ltssm); 462 } 463 enabled = ltssm >= PCI_LTSSM_L0; 464 465 /* we need to re-write the bar0 since a reset will 466 * clear it 467 */ 468 pci_hose_write_config_dword(hose, dev, 469 PCI_BASE_ADDRESS_0, pcicsrbar); 470 } 471 #endif 472 473 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 474 if (enabled == 0) { 475 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 476 temp32 = in_be32(&srds_regs->srdspccr0); 477 478 if ((temp32 >> 28) == 3) { 479 int i; 480 481 out_be32(&srds_regs->srdspccr0, 2 << 28); 482 setbits_be32(&pci->pdb_stat, 0x08000000); 483 in_be32(&pci->pdb_stat); 484 udelay(100); 485 clrbits_be32(&pci->pdb_stat, 0x08000000); 486 asm("sync;isync"); 487 for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { 488 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 489 udelay(1000); 490 } 491 enabled = ltssm >= PCI_LTSSM_L0; 492 } 493 } 494 #endif 495 if (!enabled) { 496 /* Let the user know there's no PCIe link */ 497 printf("no link, regs @ 0x%lx\n", pci_info->regs); 498 hose->last_busno = hose->first_busno; 499 return; 500 } 501 502 out_be32(&pci->pme_msg_det, 0xffffffff); 503 out_be32(&pci->pme_msg_int_en, 0xffffffff); 504 505 /* Print the negotiated PCIe link width */ 506 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); 507 printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, 508 pci_info->regs); 509 510 hose->current_busno++; /* Start scan with secondary */ 511 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 512 } 513 514 /* Use generic setup_device to initialize standard pci regs, 515 * but do not allocate any windows since any BAR found (such 516 * as PCSRBAR) is not in this cpu's memory space. 517 */ 518 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 519 hose->pci_prefetch, hose->pci_io); 520 521 if (inbound) { 522 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 523 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 524 temp16 | PCI_COMMAND_MEMORY); 525 } 526 527 #ifndef CONFIG_PCI_NOSCAN 528 if (!fsl_is_pci_agent(hose)) { 529 debug(" Scanning PCI bus %02x\n", 530 hose->current_busno); 531 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); 532 } else { 533 debug(" Not scanning PCI bus %02x. PI=%x\n", 534 hose->current_busno, temp8); 535 hose->last_busno = hose->current_busno; 536 } 537 538 /* if we are PCIe - update limit regs and subordinate busno 539 * for the virtual P2P bridge 540 */ 541 if (pcie_cap == PCI_CAP_ID_EXP) { 542 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 543 } 544 #else 545 hose->last_busno = hose->current_busno; 546 #endif 547 548 /* Clear all error indications */ 549 if (pcie_cap == PCI_CAP_ID_EXP) 550 out_be32(&pci->pme_msg_det, 0xffffffff); 551 out_be32(&pci->pedr, 0xffffffff); 552 553 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); 554 if (temp16) { 555 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff); 556 } 557 558 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 559 if (temp16) { 560 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 561 } 562 } 563 564 int fsl_is_pci_agent(struct pci_controller *hose) 565 { 566 u8 pcie_cap; 567 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 568 569 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 570 if (pcie_cap == PCI_CAP_ID_EXP) { 571 u8 header_type; 572 573 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, 574 &header_type); 575 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; 576 } else { 577 u8 prog_if; 578 579 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); 580 return (prog_if == FSL_PROG_IF_AGENT); 581 } 582 } 583 584 int fsl_pci_init_port(struct fsl_pci_info *pci_info, 585 struct pci_controller *hose, int busno) 586 { 587 volatile ccsr_fsl_pci_t *pci; 588 struct pci_region *r; 589 pci_dev_t dev = PCI_BDF(busno,0,0); 590 u8 pcie_cap; 591 592 pci = (ccsr_fsl_pci_t *) pci_info->regs; 593 594 /* on non-PCIe controllers we don't have pme_msg_det so this code 595 * should do nothing since the read will return 0 596 */ 597 if (in_be32(&pci->pme_msg_det)) { 598 out_be32(&pci->pme_msg_det, 0xffffffff); 599 debug (" with errors. Clearing. Now 0x%08x", 600 pci->pme_msg_det); 601 } 602 603 r = hose->regions + hose->region_count; 604 605 /* outbound memory */ 606 pci_set_region(r++, 607 pci_info->mem_bus, 608 pci_info->mem_phys, 609 pci_info->mem_size, 610 PCI_REGION_MEM); 611 612 /* outbound io */ 613 pci_set_region(r++, 614 pci_info->io_bus, 615 pci_info->io_phys, 616 pci_info->io_size, 617 PCI_REGION_IO); 618 619 hose->region_count = r - hose->regions; 620 hose->first_busno = busno; 621 622 fsl_pci_init(hose, pci_info); 623 624 if (fsl_is_pci_agent(hose)) { 625 fsl_pci_config_unlock(hose); 626 hose->last_busno = hose->first_busno; 627 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 628 } else { 629 /* boot from PCIE --master releases slave's core 0 */ 630 char *s = getenv("bootmaster"); 631 char pcie[6]; 632 sprintf(pcie, "PCIE%d", pci_info->pci_num); 633 634 if (s && (strcmp(s, pcie) == 0)) 635 fsl_pcie_boot_master_release_slave(pci_info->pci_num); 636 #endif 637 } 638 639 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 640 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? 641 "e" : "", pci_info->pci_num, 642 hose->first_busno, hose->last_busno); 643 644 return(hose->last_busno + 1); 645 } 646 647 /* Enable inbound PCI config cycles for agent/endpoint interface */ 648 void fsl_pci_config_unlock(struct pci_controller *hose) 649 { 650 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); 651 u8 pcie_cap; 652 u16 pbfr; 653 654 if (!fsl_is_pci_agent(hose)) 655 return; 656 657 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 658 if (pcie_cap != 0x0) { 659 /* PCIe - set CFG_READY bit of Configuration Ready Register */ 660 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); 661 } else { 662 /* PCI - clear ACL bit of PBFR */ 663 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); 664 pbfr &= ~0x20; 665 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr); 666 } 667 } 668 669 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \ 670 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4) 671 int fsl_configure_pcie(struct fsl_pci_info *info, 672 struct pci_controller *hose, 673 const char *connected, int busno) 674 { 675 int is_endpoint; 676 677 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); 678 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); 679 680 is_endpoint = fsl_setup_hose(hose, info->regs); 681 printf("PCIe%u: %s", info->pci_num, 682 is_endpoint ? "Endpoint" : "Root Complex"); 683 if (connected) 684 printf(" of %s", connected); 685 puts(", "); 686 687 return fsl_pci_init_port(info, hose, busno); 688 } 689 690 #if defined(CONFIG_FSL_CORENET) 691 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 692 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1 693 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2 694 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3 695 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4 696 #else 697 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1 698 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2 699 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3 700 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4 701 #endif 702 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 703 #elif defined(CONFIG_MPC85xx) 704 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE 705 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 706 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 707 #define _DEVDISR_PCIE4 0 708 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 709 #elif defined(CONFIG_MPC86xx) 710 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1 711 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2 712 #define _DEVDISR_PCIE3 0 713 #define _DEVDISR_PCIE4 0 714 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ 715 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) 716 #else 717 #error "No defines for DEVDISR_PCIE" 718 #endif 719 720 /* Implement a dummy function for those platforms w/o SERDES */ 721 static const char *__board_serdes_name(enum srds_prtcl device) 722 { 723 switch (device) { 724 #ifdef CONFIG_SYS_PCIE1_NAME 725 case PCIE1: 726 return CONFIG_SYS_PCIE1_NAME; 727 #endif 728 #ifdef CONFIG_SYS_PCIE2_NAME 729 case PCIE2: 730 return CONFIG_SYS_PCIE2_NAME; 731 #endif 732 #ifdef CONFIG_SYS_PCIE3_NAME 733 case PCIE3: 734 return CONFIG_SYS_PCIE3_NAME; 735 #endif 736 #ifdef CONFIG_SYS_PCIE4_NAME 737 case PCIE4: 738 return CONFIG_SYS_PCIE4_NAME; 739 #endif 740 default: 741 return NULL; 742 } 743 744 return NULL; 745 } 746 747 __attribute__((weak, alias("__board_serdes_name"))) const char * 748 board_serdes_name(enum srds_prtcl device); 749 750 static u32 devdisr_mask[] = { 751 _DEVDISR_PCIE1, 752 _DEVDISR_PCIE2, 753 _DEVDISR_PCIE3, 754 _DEVDISR_PCIE4, 755 }; 756 757 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 758 struct fsl_pci_info *pci_info) 759 { 760 struct pci_controller *hose; 761 int num = dev - PCIE1; 762 763 hose = calloc(1, sizeof(struct pci_controller)); 764 if (!hose) 765 return busno; 766 767 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) { 768 busno = fsl_configure_pcie(pci_info, hose, 769 board_serdes_name(dev), busno); 770 } else { 771 printf("PCIe%d: disabled\n", num + 1); 772 } 773 774 return busno; 775 } 776 777 int fsl_pcie_init_board(int busno) 778 { 779 struct fsl_pci_info pci_info; 780 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; 781 u32 devdisr; 782 u32 *addr; 783 784 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 785 addr = &gur->devdisr3; 786 #else 787 addr = &gur->devdisr; 788 #endif 789 devdisr = in_be32(addr); 790 791 #ifdef CONFIG_PCIE1 792 SET_STD_PCIE_INFO(pci_info, 1); 793 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); 794 #else 795 setbits_be32(addr, _DEVDISR_PCIE1); /* disable */ 796 #endif 797 798 #ifdef CONFIG_PCIE2 799 SET_STD_PCIE_INFO(pci_info, 2); 800 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info); 801 #else 802 setbits_be32(addr, _DEVDISR_PCIE2); /* disable */ 803 #endif 804 805 #ifdef CONFIG_PCIE3 806 SET_STD_PCIE_INFO(pci_info, 3); 807 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info); 808 #else 809 setbits_be32(addr, _DEVDISR_PCIE3); /* disable */ 810 #endif 811 812 #ifdef CONFIG_PCIE4 813 SET_STD_PCIE_INFO(pci_info, 4); 814 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info); 815 #else 816 setbits_be32(addr, _DEVDISR_PCIE4); /* disable */ 817 #endif 818 819 return busno; 820 } 821 #else 822 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 823 struct fsl_pci_info *pci_info) 824 { 825 return busno; 826 } 827 828 int fsl_pcie_init_board(int busno) 829 { 830 return busno; 831 } 832 #endif 833 834 #ifdef CONFIG_OF_BOARD_SETUP 835 #include <libfdt.h> 836 #include <fdt_support.h> 837 838 void ft_fsl_pci_setup(void *blob, const char *pci_compat, 839 unsigned long ctrl_addr) 840 { 841 int off; 842 u32 bus_range[2]; 843 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr; 844 struct pci_controller *hose; 845 846 hose = find_hose_by_cfg_addr((void *)(ctrl_addr)); 847 848 /* convert ctrl_addr to true physical address */ 849 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR; 850 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS; 851 852 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr); 853 854 if (off < 0) 855 return; 856 857 /* We assume a cfg_addr not being set means we didn't setup the controller */ 858 if ((hose == NULL) || (hose->cfg_addr == NULL)) { 859 fdt_del_node(blob, off); 860 } else { 861 bus_range[0] = 0; 862 bus_range[1] = hose->last_busno - hose->first_busno; 863 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); 864 fdt_pci_dma_ranges(blob, off, hose); 865 } 866 } 867 #endif 868