1 /* 2 * Copyright 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 /* 25 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 26 * 27 * Initialize controller and call the common driver/pci pci_hose_scan to 28 * scan for bridges and devices. 29 * 30 * Hose fields which need to be pre-initialized by board specific code: 31 * regions[] 32 * first_busno 33 * 34 * Fields updated: 35 * last_busno 36 */ 37 38 #include <pci.h> 39 #include <asm/io.h> 40 #include <asm/fsl_pci.h> 41 42 /* Freescale-specific PCI config registers */ 43 #define FSL_PCI_PBFR 0x44 44 #define FSL_PCIE_CAP_ID 0x4c 45 #define FSL_PCIE_CFG_RDY 0x4b0 46 #define FSL_PROG_IF_AGENT 0x1 47 48 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 49 pci_dev_t dev, int sub_bus); 50 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 51 pci_dev_t dev, int sub_bus); 52 void pciauto_config_init(struct pci_controller *hose); 53 54 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 55 #define CONFIG_SYS_PCI_MEMORY_BUS 0 56 #endif 57 58 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 59 #define CONFIG_SYS_PCI_MEMORY_PHYS 0 60 #endif 61 62 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) 63 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) 64 #endif 65 66 /* Setup one inbound ATMU window. 67 * 68 * We let the caller decide what the window size should be 69 */ 70 static void set_inbound_window(volatile pit_t *pi, 71 struct pci_region *r, 72 u64 size) 73 { 74 u32 sz = (__ilog2_u64(size) - 1); 75 u32 flag = PIWAR_EN | PIWAR_LOCAL | 76 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 77 78 out_be32(&pi->pitar, r->phys_start >> 12); 79 out_be32(&pi->piwbar, r->bus_start >> 12); 80 #ifdef CONFIG_SYS_PCI_64BIT 81 out_be32(&pi->piwbear, r->bus_start >> 44); 82 #else 83 out_be32(&pi->piwbear, 0); 84 #endif 85 if (r->flags & PCI_REGION_PREFETCH) 86 flag |= PIWAR_PF; 87 out_be32(&pi->piwar, flag | sz); 88 } 89 90 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) 91 { 92 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr; 93 94 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 95 96 return fsl_is_pci_agent(hose); 97 } 98 99 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, 100 u64 out_lo, u8 pcie_cap, 101 volatile pit_t *pi) 102 { 103 struct pci_region *r = hose->regions + hose->region_count; 104 u64 sz = min((u64)gd->ram_size, (1ull << 32)); 105 106 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; 107 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; 108 pci_size_t pci_sz; 109 110 /* we have no space available for inbound memory mapping */ 111 if (bus_start > out_lo) { 112 printf ("no space for inbound mapping of memory\n"); 113 return 0; 114 } 115 116 /* limit size */ 117 if ((bus_start + sz) > out_lo) { 118 sz = out_lo - bus_start; 119 debug ("limiting size to %llx\n", sz); 120 } 121 122 pci_sz = 1ull << __ilog2_u64(sz); 123 /* 124 * we can overlap inbound/outbound windows on PCI-E since RX & TX 125 * links a separate 126 */ 127 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) { 128 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 129 (u64)bus_start, (u64)phys_start, (u64)sz); 130 pci_set_region(r, bus_start, phys_start, sz, 131 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 132 PCI_REGION_PREFETCH); 133 134 /* if we aren't an exact power of two match, pci_sz is smaller 135 * round it up to the next power of two. We report the actual 136 * size to pci region tracking. 137 */ 138 if (pci_sz != sz) 139 sz = 2ull << __ilog2_u64(sz); 140 141 set_inbound_window(pi--, r++, sz); 142 sz = 0; /* make sure we dont set the R2 window */ 143 } else { 144 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 145 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 146 pci_set_region(r, bus_start, phys_start, pci_sz, 147 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 148 PCI_REGION_PREFETCH); 149 set_inbound_window(pi--, r++, pci_sz); 150 151 sz -= pci_sz; 152 bus_start += pci_sz; 153 phys_start += pci_sz; 154 155 pci_sz = 1ull << __ilog2_u64(sz); 156 if (sz) { 157 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", 158 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 159 pci_set_region(r, bus_start, phys_start, pci_sz, 160 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 161 PCI_REGION_PREFETCH); 162 set_inbound_window(pi--, r++, pci_sz); 163 sz -= pci_sz; 164 bus_start += pci_sz; 165 phys_start += pci_sz; 166 } 167 } 168 169 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) 170 /* 171 * On 64-bit capable systems, set up a mapping for all of DRAM 172 * in high pci address space. 173 */ 174 pci_sz = 1ull << __ilog2_u64(gd->ram_size); 175 /* round up to the next largest power of two */ 176 if (gd->ram_size > pci_sz) 177 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); 178 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", 179 (u64)CONFIG_SYS_PCI64_MEMORY_BUS, 180 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, 181 (u64)pci_sz); 182 pci_set_region(r, 183 CONFIG_SYS_PCI64_MEMORY_BUS, 184 CONFIG_SYS_PCI_MEMORY_PHYS, 185 pci_sz, 186 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 187 PCI_REGION_PREFETCH); 188 set_inbound_window(pi--, r++, pci_sz); 189 #else 190 pci_sz = 1ull << __ilog2_u64(sz); 191 if (sz) { 192 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", 193 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 194 pci_set_region(r, bus_start, phys_start, pci_sz, 195 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 196 PCI_REGION_PREFETCH); 197 sz -= pci_sz; 198 bus_start += pci_sz; 199 phys_start += pci_sz; 200 set_inbound_window(pi--, r++, pci_sz); 201 } 202 #endif 203 204 #ifdef CONFIG_PHYS_64BIT 205 if (sz && (((u64)gd->ram_size) < (1ull << 32))) 206 printf("Was not able to map all of memory via " 207 "inbound windows -- %lld remaining\n", sz); 208 #endif 209 210 hose->region_count = r - hose->regions; 211 212 return 1; 213 } 214 215 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) 216 { 217 u16 temp16; 218 u32 temp32; 219 int enabled, r, inbound = 0; 220 u16 ltssm; 221 u8 temp8, pcie_cap; 222 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; 223 struct pci_region *reg = hose->regions + hose->region_count; 224 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 225 226 /* Initialize ATMU registers based on hose regions and flags */ 227 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ 228 volatile pit_t *pi = &pci->pit[2]; /* ranges from: 3 to 1 */ 229 230 u64 out_hi = 0, out_lo = -1ULL; 231 u32 pcicsrbar, pcicsrbar_sz; 232 233 #ifdef DEBUG 234 int neg_link_w; 235 #endif 236 237 pci_setup_indirect(hose, cfg_addr, cfg_data); 238 239 /* Handle setup of outbound windows first */ 240 for (r = 0; r < hose->region_count; r++) { 241 unsigned long flags = hose->regions[r].flags; 242 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); 243 244 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE; 245 if (flags != PCI_REGION_SYS_MEMORY) { 246 u64 start = hose->regions[r].bus_start; 247 u64 end = start + hose->regions[r].size; 248 249 out_be32(&po->powbar, hose->regions[r].phys_start >> 12); 250 out_be32(&po->potar, start >> 12); 251 #ifdef CONFIG_SYS_PCI_64BIT 252 out_be32(&po->potear, start >> 44); 253 #else 254 out_be32(&po->potear, 0); 255 #endif 256 if (hose->regions[r].flags & PCI_REGION_IO) { 257 out_be32(&po->powar, POWAR_EN | sz | 258 POWAR_IO_READ | POWAR_IO_WRITE); 259 } else { 260 out_be32(&po->powar, POWAR_EN | sz | 261 POWAR_MEM_READ | POWAR_MEM_WRITE); 262 out_lo = min(start, out_lo); 263 out_hi = max(end, out_hi); 264 } 265 po++; 266 } 267 } 268 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi); 269 270 /* setup PCSRBAR/PEXCSRBAR */ 271 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); 272 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 273 pcicsrbar_sz = ~pcicsrbar_sz + 1; 274 275 if (out_hi < (0x100000000ull - pcicsrbar_sz) || 276 (out_lo > 0x100000000ull)) 277 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 278 else 279 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz; 280 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar); 281 282 out_lo = min(out_lo, (u64)pcicsrbar); 283 284 debug("PCICSRBAR @ 0x%x\n", pcicsrbar); 285 286 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS, 287 pcicsrbar_sz, PCI_REGION_SYS_MEMORY); 288 hose->region_count++; 289 290 /* see if we are a PCIe or PCI controller */ 291 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 292 293 /* inbound */ 294 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi); 295 296 for (r = 0; r < hose->region_count; r++) 297 debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r, 298 (u64)hose->regions[r].phys_start, 299 hose->regions[r].bus_start, 300 hose->regions[r].size, 301 hose->regions[r].flags); 302 303 pci_register_hose(hose); 304 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 305 hose->current_busno = hose->first_busno; 306 307 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */ 308 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except 309 * - Master abort (pci) 310 * - Master PERR (pci) 311 * - ICCA (PCIe) 312 */ 313 pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32); 314 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 315 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); 316 317 if (pcie_cap == PCI_CAP_ID_EXP) { 318 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 319 enabled = ltssm >= PCI_LTSSM_L0; 320 321 #ifdef CONFIG_FSL_PCIE_RESET 322 if (ltssm == 1) { 323 int i; 324 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm); 325 /* assert PCIe reset */ 326 setbits_be32(&pci->pdb_stat, 0x08000000); 327 (void) in_be32(&pci->pdb_stat); 328 udelay(100); 329 debug(" Asserting PCIe reset @%x = %x\n", 330 &pci->pdb_stat, in_be32(&pci->pdb_stat)); 331 /* clear PCIe reset */ 332 clrbits_be32(&pci->pdb_stat, 0x08000000); 333 asm("sync;isync"); 334 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { 335 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 336 <ssm); 337 udelay(1000); 338 debug("....PCIe link error. " 339 "LTSSM=0x%02x.\n", ltssm); 340 } 341 enabled = ltssm >= PCI_LTSSM_L0; 342 343 /* we need to re-write the bar0 since a reset will 344 * clear it 345 */ 346 pci_hose_write_config_dword(hose, dev, 347 PCI_BASE_ADDRESS_0, pcicsrbar); 348 } 349 #endif 350 351 if (!enabled) { 352 debug("....PCIE link error. Skipping scan." 353 "LTSSM=0x%02x\n", ltssm); 354 hose->last_busno = hose->first_busno; 355 return; 356 } 357 358 out_be32(&pci->pme_msg_det, 0xffffffff); 359 out_be32(&pci->pme_msg_int_en, 0xffffffff); 360 #ifdef DEBUG 361 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); 362 neg_link_w = (temp16 & 0x3f0 ) >> 4; 363 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", 364 ltssm, neg_link_w); 365 #endif 366 hose->current_busno++; /* Start scan with secondary */ 367 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 368 } 369 370 /* Use generic setup_device to initialize standard pci regs, 371 * but do not allocate any windows since any BAR found (such 372 * as PCSRBAR) is not in this cpu's memory space. 373 */ 374 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 375 hose->pci_prefetch, hose->pci_io); 376 377 if (inbound) { 378 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 379 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 380 temp16 | PCI_COMMAND_MEMORY); 381 } 382 383 #ifndef CONFIG_PCI_NOSCAN 384 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); 385 386 /* Programming Interface (PCI_CLASS_PROG) 387 * 0 == pci host or pcie root-complex, 388 * 1 == pci agent or pcie end-point 389 */ 390 if (!temp8) { 391 printf(" Scanning PCI bus %02x\n", 392 hose->current_busno); 393 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); 394 } else { 395 debug(" Not scanning PCI bus %02x. PI=%x\n", 396 hose->current_busno, temp8); 397 hose->last_busno = hose->current_busno; 398 } 399 400 /* if we are PCIe - update limit regs and subordinate busno 401 * for the virtual P2P bridge 402 */ 403 if (pcie_cap == PCI_CAP_ID_EXP) { 404 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 405 } 406 #else 407 hose->last_busno = hose->current_busno; 408 #endif 409 410 /* Clear all error indications */ 411 if (pcie_cap == PCI_CAP_ID_EXP) 412 out_be32(&pci->pme_msg_det, 0xffffffff); 413 out_be32(&pci->pedr, 0xffffffff); 414 415 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); 416 if (temp16) { 417 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff); 418 } 419 420 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 421 if (temp16) { 422 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 423 } 424 } 425 426 int fsl_is_pci_agent(struct pci_controller *hose) 427 { 428 u8 prog_if; 429 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 430 431 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); 432 433 return (prog_if == FSL_PROG_IF_AGENT); 434 } 435 436 int fsl_pci_init_port(struct fsl_pci_info *pci_info, 437 struct pci_controller *hose, int busno) 438 { 439 volatile ccsr_fsl_pci_t *pci; 440 struct pci_region *r; 441 442 pci = (ccsr_fsl_pci_t *) pci_info->regs; 443 444 /* on non-PCIe controllers we don't have pme_msg_det so this code 445 * should do nothing since the read will return 0 446 */ 447 if (in_be32(&pci->pme_msg_det)) { 448 out_be32(&pci->pme_msg_det, 0xffffffff); 449 debug (" with errors. Clearing. Now 0x%08x", 450 pci->pme_msg_det); 451 } 452 453 r = hose->regions + hose->region_count; 454 455 /* outbound memory */ 456 pci_set_region(r++, 457 pci_info->mem_bus, 458 pci_info->mem_phys, 459 pci_info->mem_size, 460 PCI_REGION_MEM); 461 462 /* outbound io */ 463 pci_set_region(r++, 464 pci_info->io_bus, 465 pci_info->io_phys, 466 pci_info->io_size, 467 PCI_REGION_IO); 468 469 hose->region_count = r - hose->regions; 470 hose->first_busno = busno; 471 472 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 473 474 if (fsl_is_pci_agent(hose)) { 475 fsl_pci_config_unlock(hose); 476 hose->last_busno = hose->first_busno; 477 } 478 479 printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num, 480 hose->first_busno, hose->last_busno); 481 482 return(hose->last_busno + 1); 483 } 484 485 /* Enable inbound PCI config cycles for agent/endpoint interface */ 486 void fsl_pci_config_unlock(struct pci_controller *hose) 487 { 488 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); 489 u8 agent; 490 u8 pcie_cap; 491 u16 pbfr; 492 493 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent); 494 if (!agent) 495 return; 496 497 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 498 if (pcie_cap != 0x0) { 499 /* PCIe - set CFG_READY bit of Configuration Ready Register */ 500 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); 501 } else { 502 /* PCI - clear ACL bit of PBFR */ 503 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); 504 pbfr &= ~0x20; 505 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr); 506 } 507 } 508 509 #ifdef CONFIG_OF_BOARD_SETUP 510 #include <libfdt.h> 511 #include <fdt_support.h> 512 513 void ft_fsl_pci_setup(void *blob, const char *pci_compat, 514 struct pci_controller *hose, unsigned long ctrl_addr) 515 { 516 int off; 517 u32 bus_range[2]; 518 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr; 519 520 /* convert ctrl_addr to true physical address */ 521 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR; 522 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS; 523 524 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr); 525 526 if (off < 0) 527 return; 528 529 /* We assume a cfg_addr not being set means we didn't setup the controller */ 530 if ((hose == NULL) || (hose->cfg_addr == NULL)) { 531 fdt_del_node(blob, off); 532 } else { 533 bus_range[0] = 0; 534 bus_range[1] = hose->last_busno - hose->first_busno; 535 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); 536 fdt_pci_dma_ranges(blob, off, hose); 537 } 538 } 539 #endif 540