1 /* 2 * Copyright 2007-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <asm/fsl_serdes.h> 10 11 DECLARE_GLOBAL_DATA_PTR; 12 13 /* 14 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 15 * 16 * Initialize controller and call the common driver/pci pci_hose_scan to 17 * scan for bridges and devices. 18 * 19 * Hose fields which need to be pre-initialized by board specific code: 20 * regions[] 21 * first_busno 22 * 23 * Fields updated: 24 * last_busno 25 */ 26 27 #include <pci.h> 28 #include <asm/io.h> 29 #include <asm/fsl_pci.h> 30 31 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 32 #define CONFIG_SYS_PCI_MEMORY_BUS 0 33 #endif 34 35 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 36 #define CONFIG_SYS_PCI_MEMORY_PHYS 0 37 #endif 38 39 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) 40 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) 41 #endif 42 43 /* Setup one inbound ATMU window. 44 * 45 * We let the caller decide what the window size should be 46 */ 47 static void set_inbound_window(volatile pit_t *pi, 48 struct pci_region *r, 49 u64 size) 50 { 51 u32 sz = (__ilog2_u64(size) - 1); 52 u32 flag = PIWAR_EN | PIWAR_LOCAL | 53 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 54 55 out_be32(&pi->pitar, r->phys_start >> 12); 56 out_be32(&pi->piwbar, r->bus_start >> 12); 57 #ifdef CONFIG_SYS_PCI_64BIT 58 out_be32(&pi->piwbear, r->bus_start >> 44); 59 #else 60 out_be32(&pi->piwbear, 0); 61 #endif 62 if (r->flags & PCI_REGION_PREFETCH) 63 flag |= PIWAR_PF; 64 out_be32(&pi->piwar, flag | sz); 65 } 66 67 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) 68 { 69 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr; 70 71 /* Reset hose to make sure its in a clean state */ 72 memset(hose, 0, sizeof(struct pci_controller)); 73 74 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 75 76 return fsl_is_pci_agent(hose); 77 } 78 79 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, 80 u64 out_lo, u8 pcie_cap, 81 volatile pit_t *pi) 82 { 83 struct pci_region *r = hose->regions + hose->region_count; 84 u64 sz = min((u64)gd->ram_size, (1ull << 32)); 85 86 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; 87 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; 88 pci_size_t pci_sz; 89 90 /* we have no space available for inbound memory mapping */ 91 if (bus_start > out_lo) { 92 printf ("no space for inbound mapping of memory\n"); 93 return 0; 94 } 95 96 /* limit size */ 97 if ((bus_start + sz) > out_lo) { 98 sz = out_lo - bus_start; 99 debug ("limiting size to %llx\n", sz); 100 } 101 102 pci_sz = 1ull << __ilog2_u64(sz); 103 /* 104 * we can overlap inbound/outbound windows on PCI-E since RX & TX 105 * links a separate 106 */ 107 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) { 108 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 109 (u64)bus_start, (u64)phys_start, (u64)sz); 110 pci_set_region(r, bus_start, phys_start, sz, 111 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 112 PCI_REGION_PREFETCH); 113 114 /* if we aren't an exact power of two match, pci_sz is smaller 115 * round it up to the next power of two. We report the actual 116 * size to pci region tracking. 117 */ 118 if (pci_sz != sz) 119 sz = 2ull << __ilog2_u64(sz); 120 121 set_inbound_window(pi--, r++, sz); 122 sz = 0; /* make sure we dont set the R2 window */ 123 } else { 124 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 125 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 126 pci_set_region(r, bus_start, phys_start, pci_sz, 127 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 128 PCI_REGION_PREFETCH); 129 set_inbound_window(pi--, r++, pci_sz); 130 131 sz -= pci_sz; 132 bus_start += pci_sz; 133 phys_start += pci_sz; 134 135 pci_sz = 1ull << __ilog2_u64(sz); 136 if (sz) { 137 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", 138 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 139 pci_set_region(r, bus_start, phys_start, pci_sz, 140 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 141 PCI_REGION_PREFETCH); 142 set_inbound_window(pi--, r++, pci_sz); 143 sz -= pci_sz; 144 bus_start += pci_sz; 145 phys_start += pci_sz; 146 } 147 } 148 149 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) 150 /* 151 * On 64-bit capable systems, set up a mapping for all of DRAM 152 * in high pci address space. 153 */ 154 pci_sz = 1ull << __ilog2_u64(gd->ram_size); 155 /* round up to the next largest power of two */ 156 if (gd->ram_size > pci_sz) 157 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); 158 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", 159 (u64)CONFIG_SYS_PCI64_MEMORY_BUS, 160 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, 161 (u64)pci_sz); 162 pci_set_region(r, 163 CONFIG_SYS_PCI64_MEMORY_BUS, 164 CONFIG_SYS_PCI_MEMORY_PHYS, 165 pci_sz, 166 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 167 PCI_REGION_PREFETCH); 168 set_inbound_window(pi--, r++, pci_sz); 169 #else 170 pci_sz = 1ull << __ilog2_u64(sz); 171 if (sz) { 172 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", 173 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 174 pci_set_region(r, bus_start, phys_start, pci_sz, 175 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 176 PCI_REGION_PREFETCH); 177 sz -= pci_sz; 178 bus_start += pci_sz; 179 phys_start += pci_sz; 180 set_inbound_window(pi--, r++, pci_sz); 181 } 182 #endif 183 184 #ifdef CONFIG_PHYS_64BIT 185 if (sz && (((u64)gd->ram_size) < (1ull << 32))) 186 printf("Was not able to map all of memory via " 187 "inbound windows -- %lld remaining\n", sz); 188 #endif 189 190 hose->region_count = r - hose->regions; 191 192 return 1; 193 } 194 195 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 196 static void fsl_pcie_boot_master(pit_t *pi) 197 { 198 /* configure inbound window for slave's u-boot image */ 199 debug("PCIEBOOT - MASTER: Inbound window for slave's image; " 200 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", 201 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 202 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, 203 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 204 struct pci_region r_inbound; 205 u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE) 206 - 1; 207 pci_set_region(&r_inbound, 208 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, 209 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 210 sz_inbound, 211 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 212 213 set_inbound_window(pi--, &r_inbound, 214 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 215 216 /* configure inbound window for slave's u-boot image */ 217 debug("PCIEBOOT - MASTER: Inbound window for slave's image; " 218 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", 219 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 220 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, 221 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 222 pci_set_region(&r_inbound, 223 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, 224 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 225 sz_inbound, 226 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 227 228 set_inbound_window(pi--, &r_inbound, 229 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 230 231 /* configure inbound window for slave's ucode and ENV */ 232 debug("PCIEBOOT - MASTER: Inbound window for slave's " 233 "ucode and ENV; " 234 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", 235 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, 236 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, 237 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); 238 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE) 239 - 1; 240 pci_set_region(&r_inbound, 241 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, 242 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, 243 sz_inbound, 244 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 245 246 set_inbound_window(pi--, &r_inbound, 247 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); 248 } 249 250 static void fsl_pcie_boot_master_release_slave(int port) 251 { 252 unsigned long release_addr; 253 254 /* now release slave's core 0 */ 255 switch (port) { 256 case 1: 257 release_addr = CONFIG_SYS_PCIE1_MEM_VIRT 258 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; 259 break; 260 #ifdef CONFIG_SYS_PCIE2_MEM_VIRT 261 case 2: 262 release_addr = CONFIG_SYS_PCIE2_MEM_VIRT 263 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; 264 break; 265 #endif 266 #ifdef CONFIG_SYS_PCIE3_MEM_VIRT 267 case 3: 268 release_addr = CONFIG_SYS_PCIE3_MEM_VIRT 269 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; 270 break; 271 #endif 272 default: 273 release_addr = 0; 274 break; 275 } 276 if (release_addr != 0) { 277 out_be32((void *)release_addr, 278 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); 279 debug("PCIEBOOT - MASTER: " 280 "Release slave successfully! Now the slave should start up!\n"); 281 } else { 282 debug("PCIEBOOT - MASTER: " 283 "Release slave failed!\n"); 284 } 285 } 286 #endif 287 288 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) 289 { 290 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; 291 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; 292 u16 temp16; 293 u32 temp32; 294 u32 block_rev; 295 int enabled, r, inbound = 0; 296 u16 ltssm; 297 u8 temp8, pcie_cap; 298 int pcie_cap_pos; 299 int pci_dcr; 300 int pci_dsr; 301 int pci_lsr; 302 303 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) 304 int pci_lcr; 305 #endif 306 307 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; 308 struct pci_region *reg = hose->regions + hose->region_count; 309 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 310 311 /* Initialize ATMU registers based on hose regions and flags */ 312 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ 313 volatile pit_t *pi; 314 315 u64 out_hi = 0, out_lo = -1ULL; 316 u32 pcicsrbar, pcicsrbar_sz; 317 318 pci_setup_indirect(hose, cfg_addr, cfg_data); 319 320 block_rev = in_be32(&pci->block_rev1); 321 if (PEX_IP_BLK_REV_2_2 <= block_rev) { 322 pi = &pci->pit[2]; /* 0xDC0 */ 323 } else { 324 pi = &pci->pit[3]; /* 0xDE0 */ 325 } 326 327 /* Handle setup of outbound windows first */ 328 for (r = 0; r < hose->region_count; r++) { 329 unsigned long flags = hose->regions[r].flags; 330 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); 331 332 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE; 333 if (flags != PCI_REGION_SYS_MEMORY) { 334 u64 start = hose->regions[r].bus_start; 335 u64 end = start + hose->regions[r].size; 336 337 out_be32(&po->powbar, hose->regions[r].phys_start >> 12); 338 out_be32(&po->potar, start >> 12); 339 #ifdef CONFIG_SYS_PCI_64BIT 340 out_be32(&po->potear, start >> 44); 341 #else 342 out_be32(&po->potear, 0); 343 #endif 344 if (hose->regions[r].flags & PCI_REGION_IO) { 345 out_be32(&po->powar, POWAR_EN | sz | 346 POWAR_IO_READ | POWAR_IO_WRITE); 347 } else { 348 out_be32(&po->powar, POWAR_EN | sz | 349 POWAR_MEM_READ | POWAR_MEM_WRITE); 350 out_lo = min(start, out_lo); 351 out_hi = max(end, out_hi); 352 } 353 po++; 354 } 355 } 356 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi); 357 358 /* setup PCSRBAR/PEXCSRBAR */ 359 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); 360 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 361 pcicsrbar_sz = ~pcicsrbar_sz + 1; 362 363 if (out_hi < (0x100000000ull - pcicsrbar_sz) || 364 (out_lo > 0x100000000ull)) 365 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 366 else 367 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz; 368 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar); 369 370 out_lo = min(out_lo, (u64)pcicsrbar); 371 372 debug("PCICSRBAR @ 0x%x\n", pcicsrbar); 373 374 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS, 375 pcicsrbar_sz, PCI_REGION_SYS_MEMORY); 376 hose->region_count++; 377 378 /* see if we are a PCIe or PCI controller */ 379 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); 380 pci_dcr = pcie_cap_pos + 0x08; 381 pci_dsr = pcie_cap_pos + 0x0a; 382 pci_lsr = pcie_cap_pos + 0x12; 383 384 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); 385 386 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 387 /* boot from PCIE --master */ 388 char *s = getenv("bootmaster"); 389 char pcie[6]; 390 sprintf(pcie, "PCIE%d", pci_info->pci_num); 391 392 if (s && (strcmp(s, pcie) == 0)) { 393 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n", 394 pci_info->pci_num); 395 fsl_pcie_boot_master((pit_t *)pi); 396 } else { 397 /* inbound */ 398 inbound = fsl_pci_setup_inbound_windows(hose, 399 out_lo, pcie_cap, pi); 400 } 401 #else 402 /* inbound */ 403 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi); 404 #endif 405 406 for (r = 0; r < hose->region_count; r++) 407 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r, 408 (u64)hose->regions[r].phys_start, 409 (u64)hose->regions[r].bus_start, 410 (u64)hose->regions[r].size, 411 hose->regions[r].flags); 412 413 pci_register_hose(hose); 414 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 415 hose->current_busno = hose->first_busno; 416 417 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */ 418 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except 419 * - Master abort (pci) 420 * - Master PERR (pci) 421 * - ICCA (PCIe) 422 */ 423 pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32); 424 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 425 pci_hose_write_config_dword(hose, dev, pci_dcr, temp32); 426 427 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) 428 pci_lcr = pcie_cap_pos + 0x10; 429 temp32 = 0; 430 pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32); 431 temp32 &= ~0x03; /* Disable ASPM */ 432 pci_hose_write_config_dword(hose, dev, pci_lcr, temp32); 433 udelay(1); 434 #endif 435 if (pcie_cap == PCI_CAP_ID_EXP) { 436 if (block_rev >= PEX_IP_BLK_REV_3_0) { 437 #define PEX_CSR0_LTSSM_MASK 0xFC 438 #define PEX_CSR0_LTSSM_SHIFT 2 439 ltssm = (in_be32(&pci->pex_csr0) 440 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; 441 enabled = (ltssm == 0x11) ? 1 : 0; 442 } else { 443 /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */ 444 /* enabled = ltssm >= PCI_LTSSM_L0; */ 445 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 446 enabled = ltssm >= PCI_LTSSM_L0; 447 448 #ifdef CONFIG_FSL_PCIE_RESET 449 if (ltssm == 1) { 450 int i; 451 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm); 452 /* assert PCIe reset */ 453 setbits_be32(&pci->pdb_stat, 0x08000000); 454 (void) in_be32(&pci->pdb_stat); 455 udelay(100); 456 debug(" Asserting PCIe reset @%p = %x\n", 457 &pci->pdb_stat, in_be32(&pci->pdb_stat)); 458 /* clear PCIe reset */ 459 clrbits_be32(&pci->pdb_stat, 0x08000000); 460 asm("sync;isync"); 461 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { 462 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 463 <ssm); 464 udelay(1000); 465 debug("....PCIe link error. " 466 "LTSSM=0x%02x.\n", ltssm); 467 } 468 enabled = ltssm >= PCI_LTSSM_L0; 469 470 /* we need to re-write the bar0 since a reset will 471 * clear it 472 */ 473 pci_hose_write_config_dword(hose, dev, 474 PCI_BASE_ADDRESS_0, pcicsrbar); 475 } 476 #endif 477 } 478 479 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 480 if (enabled == 0) { 481 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 482 temp32 = in_be32(&srds_regs->srdspccr0); 483 484 if ((temp32 >> 28) == 3) { 485 int i; 486 487 out_be32(&srds_regs->srdspccr0, 2 << 28); 488 setbits_be32(&pci->pdb_stat, 0x08000000); 489 in_be32(&pci->pdb_stat); 490 udelay(100); 491 clrbits_be32(&pci->pdb_stat, 0x08000000); 492 asm("sync;isync"); 493 for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { 494 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 495 udelay(1000); 496 } 497 enabled = ltssm >= PCI_LTSSM_L0; 498 } 499 } 500 #endif 501 if (!enabled) { 502 /* Let the user know there's no PCIe link */ 503 printf("no link, regs @ 0x%lx\n", pci_info->regs); 504 hose->last_busno = hose->first_busno; 505 return; 506 } 507 508 out_be32(&pci->pme_msg_det, 0xffffffff); 509 out_be32(&pci->pme_msg_int_en, 0xffffffff); 510 511 /* Print the negotiated PCIe link width */ 512 pci_hose_read_config_word(hose, dev, pci_lsr, &temp16); 513 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4, 514 (temp16 & 0xf), pci_info->regs); 515 516 hose->current_busno++; /* Start scan with secondary */ 517 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 518 } 519 520 /* Use generic setup_device to initialize standard pci regs, 521 * but do not allocate any windows since any BAR found (such 522 * as PCSRBAR) is not in this cpu's memory space. 523 */ 524 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 525 hose->pci_prefetch, hose->pci_io); 526 527 if (inbound) { 528 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 529 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 530 temp16 | PCI_COMMAND_MEMORY); 531 } 532 533 #ifndef CONFIG_PCI_NOSCAN 534 if (!fsl_is_pci_agent(hose)) { 535 debug(" Scanning PCI bus %02x\n", 536 hose->current_busno); 537 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); 538 } else { 539 debug(" Not scanning PCI bus %02x. PI=%x\n", 540 hose->current_busno, temp8); 541 hose->last_busno = hose->current_busno; 542 } 543 544 /* if we are PCIe - update limit regs and subordinate busno 545 * for the virtual P2P bridge 546 */ 547 if (pcie_cap == PCI_CAP_ID_EXP) { 548 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 549 } 550 #else 551 hose->last_busno = hose->current_busno; 552 #endif 553 554 /* Clear all error indications */ 555 if (pcie_cap == PCI_CAP_ID_EXP) 556 out_be32(&pci->pme_msg_det, 0xffffffff); 557 out_be32(&pci->pedr, 0xffffffff); 558 559 pci_hose_read_config_word(hose, dev, pci_dsr, &temp16); 560 if (temp16) { 561 pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff); 562 } 563 564 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 565 if (temp16) { 566 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 567 } 568 } 569 570 int fsl_is_pci_agent(struct pci_controller *hose) 571 { 572 int pcie_cap_pos; 573 u8 pcie_cap; 574 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 575 576 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); 577 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); 578 if (pcie_cap == PCI_CAP_ID_EXP) { 579 u8 header_type; 580 581 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, 582 &header_type); 583 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; 584 } else { 585 u8 prog_if; 586 587 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); 588 /* Programming Interface (PCI_CLASS_PROG) 589 * 0 == pci host or pcie root-complex, 590 * 1 == pci agent or pcie end-point 591 */ 592 return (prog_if == FSL_PROG_IF_AGENT); 593 } 594 } 595 596 int fsl_pci_init_port(struct fsl_pci_info *pci_info, 597 struct pci_controller *hose, int busno) 598 { 599 volatile ccsr_fsl_pci_t *pci; 600 struct pci_region *r; 601 pci_dev_t dev = PCI_BDF(busno,0,0); 602 int pcie_cap_pos; 603 u8 pcie_cap; 604 605 pci = (ccsr_fsl_pci_t *) pci_info->regs; 606 607 /* on non-PCIe controllers we don't have pme_msg_det so this code 608 * should do nothing since the read will return 0 609 */ 610 if (in_be32(&pci->pme_msg_det)) { 611 out_be32(&pci->pme_msg_det, 0xffffffff); 612 debug (" with errors. Clearing. Now 0x%08x", 613 pci->pme_msg_det); 614 } 615 616 r = hose->regions + hose->region_count; 617 618 /* outbound memory */ 619 pci_set_region(r++, 620 pci_info->mem_bus, 621 pci_info->mem_phys, 622 pci_info->mem_size, 623 PCI_REGION_MEM); 624 625 /* outbound io */ 626 pci_set_region(r++, 627 pci_info->io_bus, 628 pci_info->io_phys, 629 pci_info->io_size, 630 PCI_REGION_IO); 631 632 hose->region_count = r - hose->regions; 633 hose->first_busno = busno; 634 635 fsl_pci_init(hose, pci_info); 636 637 if (fsl_is_pci_agent(hose)) { 638 fsl_pci_config_unlock(hose); 639 hose->last_busno = hose->first_busno; 640 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 641 } else { 642 /* boot from PCIE --master releases slave's core 0 */ 643 char *s = getenv("bootmaster"); 644 char pcie[6]; 645 sprintf(pcie, "PCIE%d", pci_info->pci_num); 646 647 if (s && (strcmp(s, pcie) == 0)) 648 fsl_pcie_boot_master_release_slave(pci_info->pci_num); 649 #endif 650 } 651 652 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); 653 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); 654 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? 655 "e" : "", pci_info->pci_num, 656 hose->first_busno, hose->last_busno); 657 return(hose->last_busno + 1); 658 } 659 660 /* Enable inbound PCI config cycles for agent/endpoint interface */ 661 void fsl_pci_config_unlock(struct pci_controller *hose) 662 { 663 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); 664 int pcie_cap_pos; 665 u8 pcie_cap; 666 u16 pbfr; 667 668 if (!fsl_is_pci_agent(hose)) 669 return; 670 671 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); 672 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); 673 if (pcie_cap != 0x0) { 674 /* PCIe - set CFG_READY bit of Configuration Ready Register */ 675 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); 676 } else { 677 /* PCI - clear ACL bit of PBFR */ 678 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); 679 pbfr &= ~0x20; 680 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr); 681 } 682 } 683 684 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \ 685 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4) 686 int fsl_configure_pcie(struct fsl_pci_info *info, 687 struct pci_controller *hose, 688 const char *connected, int busno) 689 { 690 int is_endpoint; 691 692 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); 693 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); 694 695 is_endpoint = fsl_setup_hose(hose, info->regs); 696 printf("PCIe%u: %s", info->pci_num, 697 is_endpoint ? "Endpoint" : "Root Complex"); 698 if (connected) 699 printf(" of %s", connected); 700 puts(", "); 701 702 return fsl_pci_init_port(info, hose, busno); 703 } 704 705 #if defined(CONFIG_FSL_CORENET) 706 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 707 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1 708 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2 709 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3 710 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4 711 #else 712 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1 713 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2 714 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3 715 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4 716 #endif 717 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 718 #elif defined(CONFIG_MPC85xx) 719 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE 720 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 721 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 722 #define _DEVDISR_PCIE4 0 723 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 724 #elif defined(CONFIG_MPC86xx) 725 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1 726 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2 727 #define _DEVDISR_PCIE3 0 728 #define _DEVDISR_PCIE4 0 729 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ 730 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) 731 #else 732 #error "No defines for DEVDISR_PCIE" 733 #endif 734 735 /* Implement a dummy function for those platforms w/o SERDES */ 736 static const char *__board_serdes_name(enum srds_prtcl device) 737 { 738 switch (device) { 739 #ifdef CONFIG_SYS_PCIE1_NAME 740 case PCIE1: 741 return CONFIG_SYS_PCIE1_NAME; 742 #endif 743 #ifdef CONFIG_SYS_PCIE2_NAME 744 case PCIE2: 745 return CONFIG_SYS_PCIE2_NAME; 746 #endif 747 #ifdef CONFIG_SYS_PCIE3_NAME 748 case PCIE3: 749 return CONFIG_SYS_PCIE3_NAME; 750 #endif 751 #ifdef CONFIG_SYS_PCIE4_NAME 752 case PCIE4: 753 return CONFIG_SYS_PCIE4_NAME; 754 #endif 755 default: 756 return NULL; 757 } 758 759 return NULL; 760 } 761 762 __attribute__((weak, alias("__board_serdes_name"))) const char * 763 board_serdes_name(enum srds_prtcl device); 764 765 static u32 devdisr_mask[] = { 766 _DEVDISR_PCIE1, 767 _DEVDISR_PCIE2, 768 _DEVDISR_PCIE3, 769 _DEVDISR_PCIE4, 770 }; 771 772 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 773 struct fsl_pci_info *pci_info) 774 { 775 struct pci_controller *hose; 776 int num = dev - PCIE1; 777 778 hose = calloc(1, sizeof(struct pci_controller)); 779 if (!hose) 780 return busno; 781 782 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) { 783 busno = fsl_configure_pcie(pci_info, hose, 784 board_serdes_name(dev), busno); 785 } else { 786 printf("PCIe%d: disabled\n", num + 1); 787 } 788 789 return busno; 790 } 791 792 int fsl_pcie_init_board(int busno) 793 { 794 struct fsl_pci_info pci_info; 795 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; 796 u32 devdisr; 797 u32 *addr; 798 799 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 800 addr = &gur->devdisr3; 801 #else 802 addr = &gur->devdisr; 803 #endif 804 devdisr = in_be32(addr); 805 806 #ifdef CONFIG_PCIE1 807 SET_STD_PCIE_INFO(pci_info, 1); 808 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); 809 #else 810 setbits_be32(addr, _DEVDISR_PCIE1); /* disable */ 811 #endif 812 813 #ifdef CONFIG_PCIE2 814 SET_STD_PCIE_INFO(pci_info, 2); 815 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info); 816 #else 817 setbits_be32(addr, _DEVDISR_PCIE2); /* disable */ 818 #endif 819 820 #ifdef CONFIG_PCIE3 821 SET_STD_PCIE_INFO(pci_info, 3); 822 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info); 823 #else 824 setbits_be32(addr, _DEVDISR_PCIE3); /* disable */ 825 #endif 826 827 #ifdef CONFIG_PCIE4 828 SET_STD_PCIE_INFO(pci_info, 4); 829 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info); 830 #else 831 setbits_be32(addr, _DEVDISR_PCIE4); /* disable */ 832 #endif 833 834 return busno; 835 } 836 #else 837 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 838 struct fsl_pci_info *pci_info) 839 { 840 return busno; 841 } 842 843 int fsl_pcie_init_board(int busno) 844 { 845 return busno; 846 } 847 #endif 848 849 #ifdef CONFIG_OF_BOARD_SETUP 850 #include <libfdt.h> 851 #include <fdt_support.h> 852 853 void ft_fsl_pci_setup(void *blob, const char *pci_compat, 854 unsigned long ctrl_addr) 855 { 856 int off; 857 u32 bus_range[2]; 858 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr; 859 struct pci_controller *hose; 860 861 hose = find_hose_by_cfg_addr((void *)(ctrl_addr)); 862 863 /* convert ctrl_addr to true physical address */ 864 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR; 865 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS; 866 867 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr); 868 869 if (off < 0) 870 return; 871 872 /* We assume a cfg_addr not being set means we didn't setup the controller */ 873 if ((hose == NULL) || (hose->cfg_addr == NULL)) { 874 fdt_del_node(blob, off); 875 } else { 876 bus_range[0] = 0; 877 bus_range[1] = hose->last_busno - hose->first_busno; 878 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); 879 fdt_pci_dma_ranges(blob, off, hose); 880 } 881 } 882 #endif 883