1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <malloc.h> 22 #include <asm/fsl_serdes.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* 27 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 28 * 29 * Initialize controller and call the common driver/pci pci_hose_scan to 30 * scan for bridges and devices. 31 * 32 * Hose fields which need to be pre-initialized by board specific code: 33 * regions[] 34 * first_busno 35 * 36 * Fields updated: 37 * last_busno 38 */ 39 40 #include <pci.h> 41 #include <asm/io.h> 42 #include <asm/fsl_pci.h> 43 44 /* Freescale-specific PCI config registers */ 45 #define FSL_PCI_PBFR 0x44 46 #define FSL_PCIE_CAP_ID 0x4c 47 #define FSL_PCIE_CFG_RDY 0x4b0 48 #define FSL_PROG_IF_AGENT 0x1 49 50 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 51 pci_dev_t dev, int sub_bus); 52 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 53 pci_dev_t dev, int sub_bus); 54 55 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 56 #define CONFIG_SYS_PCI_MEMORY_BUS 0 57 #endif 58 59 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 60 #define CONFIG_SYS_PCI_MEMORY_PHYS 0 61 #endif 62 63 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) 64 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) 65 #endif 66 67 /* Setup one inbound ATMU window. 68 * 69 * We let the caller decide what the window size should be 70 */ 71 static void set_inbound_window(volatile pit_t *pi, 72 struct pci_region *r, 73 u64 size) 74 { 75 u32 sz = (__ilog2_u64(size) - 1); 76 u32 flag = PIWAR_EN | PIWAR_LOCAL | 77 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 78 79 out_be32(&pi->pitar, r->phys_start >> 12); 80 out_be32(&pi->piwbar, r->bus_start >> 12); 81 #ifdef CONFIG_SYS_PCI_64BIT 82 out_be32(&pi->piwbear, r->bus_start >> 44); 83 #else 84 out_be32(&pi->piwbear, 0); 85 #endif 86 if (r->flags & PCI_REGION_PREFETCH) 87 flag |= PIWAR_PF; 88 out_be32(&pi->piwar, flag | sz); 89 } 90 91 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) 92 { 93 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr; 94 95 /* Reset hose to make sure its in a clean state */ 96 memset(hose, 0, sizeof(struct pci_controller)); 97 98 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 99 100 return fsl_is_pci_agent(hose); 101 } 102 103 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, 104 u64 out_lo, u8 pcie_cap, 105 volatile pit_t *pi) 106 { 107 struct pci_region *r = hose->regions + hose->region_count; 108 u64 sz = min((u64)gd->ram_size, (1ull << 32)); 109 110 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; 111 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; 112 pci_size_t pci_sz; 113 114 /* we have no space available for inbound memory mapping */ 115 if (bus_start > out_lo) { 116 printf ("no space for inbound mapping of memory\n"); 117 return 0; 118 } 119 120 /* limit size */ 121 if ((bus_start + sz) > out_lo) { 122 sz = out_lo - bus_start; 123 debug ("limiting size to %llx\n", sz); 124 } 125 126 pci_sz = 1ull << __ilog2_u64(sz); 127 /* 128 * we can overlap inbound/outbound windows on PCI-E since RX & TX 129 * links a separate 130 */ 131 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) { 132 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 133 (u64)bus_start, (u64)phys_start, (u64)sz); 134 pci_set_region(r, bus_start, phys_start, sz, 135 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 136 PCI_REGION_PREFETCH); 137 138 /* if we aren't an exact power of two match, pci_sz is smaller 139 * round it up to the next power of two. We report the actual 140 * size to pci region tracking. 141 */ 142 if (pci_sz != sz) 143 sz = 2ull << __ilog2_u64(sz); 144 145 set_inbound_window(pi--, r++, sz); 146 sz = 0; /* make sure we dont set the R2 window */ 147 } else { 148 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 149 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 150 pci_set_region(r, bus_start, phys_start, pci_sz, 151 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 152 PCI_REGION_PREFETCH); 153 set_inbound_window(pi--, r++, pci_sz); 154 155 sz -= pci_sz; 156 bus_start += pci_sz; 157 phys_start += pci_sz; 158 159 pci_sz = 1ull << __ilog2_u64(sz); 160 if (sz) { 161 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", 162 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 163 pci_set_region(r, bus_start, phys_start, pci_sz, 164 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 165 PCI_REGION_PREFETCH); 166 set_inbound_window(pi--, r++, pci_sz); 167 sz -= pci_sz; 168 bus_start += pci_sz; 169 phys_start += pci_sz; 170 } 171 } 172 173 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) 174 /* 175 * On 64-bit capable systems, set up a mapping for all of DRAM 176 * in high pci address space. 177 */ 178 pci_sz = 1ull << __ilog2_u64(gd->ram_size); 179 /* round up to the next largest power of two */ 180 if (gd->ram_size > pci_sz) 181 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); 182 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", 183 (u64)CONFIG_SYS_PCI64_MEMORY_BUS, 184 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, 185 (u64)pci_sz); 186 pci_set_region(r, 187 CONFIG_SYS_PCI64_MEMORY_BUS, 188 CONFIG_SYS_PCI_MEMORY_PHYS, 189 pci_sz, 190 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 191 PCI_REGION_PREFETCH); 192 set_inbound_window(pi--, r++, pci_sz); 193 #else 194 pci_sz = 1ull << __ilog2_u64(sz); 195 if (sz) { 196 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", 197 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 198 pci_set_region(r, bus_start, phys_start, pci_sz, 199 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 200 PCI_REGION_PREFETCH); 201 sz -= pci_sz; 202 bus_start += pci_sz; 203 phys_start += pci_sz; 204 set_inbound_window(pi--, r++, pci_sz); 205 } 206 #endif 207 208 #ifdef CONFIG_PHYS_64BIT 209 if (sz && (((u64)gd->ram_size) < (1ull << 32))) 210 printf("Was not able to map all of memory via " 211 "inbound windows -- %lld remaining\n", sz); 212 #endif 213 214 hose->region_count = r - hose->regions; 215 216 return 1; 217 } 218 219 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) 220 { 221 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; 222 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; 223 u16 temp16; 224 u32 temp32; 225 u32 block_rev; 226 int enabled, r, inbound = 0; 227 u16 ltssm; 228 u8 temp8, pcie_cap; 229 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; 230 struct pci_region *reg = hose->regions + hose->region_count; 231 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 232 233 /* Initialize ATMU registers based on hose regions and flags */ 234 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ 235 volatile pit_t *pi; 236 237 u64 out_hi = 0, out_lo = -1ULL; 238 u32 pcicsrbar, pcicsrbar_sz; 239 240 pci_setup_indirect(hose, cfg_addr, cfg_data); 241 242 block_rev = in_be32(&pci->block_rev1); 243 if (PEX_IP_BLK_REV_2_2 <= block_rev) { 244 pi = &pci->pit[2]; /* 0xDC0 */ 245 } else { 246 pi = &pci->pit[3]; /* 0xDE0 */ 247 } 248 249 /* Handle setup of outbound windows first */ 250 for (r = 0; r < hose->region_count; r++) { 251 unsigned long flags = hose->regions[r].flags; 252 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); 253 254 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE; 255 if (flags != PCI_REGION_SYS_MEMORY) { 256 u64 start = hose->regions[r].bus_start; 257 u64 end = start + hose->regions[r].size; 258 259 out_be32(&po->powbar, hose->regions[r].phys_start >> 12); 260 out_be32(&po->potar, start >> 12); 261 #ifdef CONFIG_SYS_PCI_64BIT 262 out_be32(&po->potear, start >> 44); 263 #else 264 out_be32(&po->potear, 0); 265 #endif 266 if (hose->regions[r].flags & PCI_REGION_IO) { 267 out_be32(&po->powar, POWAR_EN | sz | 268 POWAR_IO_READ | POWAR_IO_WRITE); 269 } else { 270 out_be32(&po->powar, POWAR_EN | sz | 271 POWAR_MEM_READ | POWAR_MEM_WRITE); 272 out_lo = min(start, out_lo); 273 out_hi = max(end, out_hi); 274 } 275 po++; 276 } 277 } 278 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi); 279 280 /* setup PCSRBAR/PEXCSRBAR */ 281 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); 282 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 283 pcicsrbar_sz = ~pcicsrbar_sz + 1; 284 285 if (out_hi < (0x100000000ull - pcicsrbar_sz) || 286 (out_lo > 0x100000000ull)) 287 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 288 else 289 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz; 290 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar); 291 292 out_lo = min(out_lo, (u64)pcicsrbar); 293 294 debug("PCICSRBAR @ 0x%x\n", pcicsrbar); 295 296 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS, 297 pcicsrbar_sz, PCI_REGION_SYS_MEMORY); 298 hose->region_count++; 299 300 /* see if we are a PCIe or PCI controller */ 301 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 302 303 /* inbound */ 304 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi); 305 306 for (r = 0; r < hose->region_count; r++) 307 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r, 308 (u64)hose->regions[r].phys_start, 309 (u64)hose->regions[r].bus_start, 310 (u64)hose->regions[r].size, 311 hose->regions[r].flags); 312 313 pci_register_hose(hose); 314 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 315 hose->current_busno = hose->first_busno; 316 317 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */ 318 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except 319 * - Master abort (pci) 320 * - Master PERR (pci) 321 * - ICCA (PCIe) 322 */ 323 pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32); 324 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 325 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); 326 327 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) 328 temp32 = 0; 329 pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32); 330 temp32 &= ~0x03; /* Disable ASPM */ 331 pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32); 332 udelay(1); 333 #endif 334 if (pcie_cap == PCI_CAP_ID_EXP) { 335 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 336 enabled = ltssm >= PCI_LTSSM_L0; 337 338 #ifdef CONFIG_FSL_PCIE_RESET 339 if (ltssm == 1) { 340 int i; 341 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm); 342 /* assert PCIe reset */ 343 setbits_be32(&pci->pdb_stat, 0x08000000); 344 (void) in_be32(&pci->pdb_stat); 345 udelay(100); 346 debug(" Asserting PCIe reset @%p = %x\n", 347 &pci->pdb_stat, in_be32(&pci->pdb_stat)); 348 /* clear PCIe reset */ 349 clrbits_be32(&pci->pdb_stat, 0x08000000); 350 asm("sync;isync"); 351 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { 352 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 353 <ssm); 354 udelay(1000); 355 debug("....PCIe link error. " 356 "LTSSM=0x%02x.\n", ltssm); 357 } 358 enabled = ltssm >= PCI_LTSSM_L0; 359 360 /* we need to re-write the bar0 since a reset will 361 * clear it 362 */ 363 pci_hose_write_config_dword(hose, dev, 364 PCI_BASE_ADDRESS_0, pcicsrbar); 365 } 366 #endif 367 368 if (!enabled) { 369 /* Let the user know there's no PCIe link */ 370 printf("no link, regs @ 0x%lx\n", pci_info->regs); 371 hose->last_busno = hose->first_busno; 372 return; 373 } 374 375 out_be32(&pci->pme_msg_det, 0xffffffff); 376 out_be32(&pci->pme_msg_int_en, 0xffffffff); 377 378 /* Print the negotiated PCIe link width */ 379 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); 380 printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, 381 pci_info->regs); 382 383 hose->current_busno++; /* Start scan with secondary */ 384 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 385 } 386 387 /* Use generic setup_device to initialize standard pci regs, 388 * but do not allocate any windows since any BAR found (such 389 * as PCSRBAR) is not in this cpu's memory space. 390 */ 391 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 392 hose->pci_prefetch, hose->pci_io); 393 394 if (inbound) { 395 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 396 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 397 temp16 | PCI_COMMAND_MEMORY); 398 } 399 400 #ifndef CONFIG_PCI_NOSCAN 401 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); 402 403 /* Programming Interface (PCI_CLASS_PROG) 404 * 0 == pci host or pcie root-complex, 405 * 1 == pci agent or pcie end-point 406 */ 407 if (!temp8) { 408 debug(" Scanning PCI bus %02x\n", 409 hose->current_busno); 410 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); 411 } else { 412 debug(" Not scanning PCI bus %02x. PI=%x\n", 413 hose->current_busno, temp8); 414 hose->last_busno = hose->current_busno; 415 } 416 417 /* if we are PCIe - update limit regs and subordinate busno 418 * for the virtual P2P bridge 419 */ 420 if (pcie_cap == PCI_CAP_ID_EXP) { 421 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 422 } 423 #else 424 hose->last_busno = hose->current_busno; 425 #endif 426 427 /* Clear all error indications */ 428 if (pcie_cap == PCI_CAP_ID_EXP) 429 out_be32(&pci->pme_msg_det, 0xffffffff); 430 out_be32(&pci->pedr, 0xffffffff); 431 432 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); 433 if (temp16) { 434 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff); 435 } 436 437 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 438 if (temp16) { 439 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 440 } 441 } 442 443 int fsl_is_pci_agent(struct pci_controller *hose) 444 { 445 u8 prog_if; 446 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 447 448 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); 449 450 return (prog_if == FSL_PROG_IF_AGENT); 451 } 452 453 int fsl_pci_init_port(struct fsl_pci_info *pci_info, 454 struct pci_controller *hose, int busno) 455 { 456 volatile ccsr_fsl_pci_t *pci; 457 struct pci_region *r; 458 pci_dev_t dev = PCI_BDF(busno,0,0); 459 u8 pcie_cap; 460 461 pci = (ccsr_fsl_pci_t *) pci_info->regs; 462 463 /* on non-PCIe controllers we don't have pme_msg_det so this code 464 * should do nothing since the read will return 0 465 */ 466 if (in_be32(&pci->pme_msg_det)) { 467 out_be32(&pci->pme_msg_det, 0xffffffff); 468 debug (" with errors. Clearing. Now 0x%08x", 469 pci->pme_msg_det); 470 } 471 472 r = hose->regions + hose->region_count; 473 474 /* outbound memory */ 475 pci_set_region(r++, 476 pci_info->mem_bus, 477 pci_info->mem_phys, 478 pci_info->mem_size, 479 PCI_REGION_MEM); 480 481 /* outbound io */ 482 pci_set_region(r++, 483 pci_info->io_bus, 484 pci_info->io_phys, 485 pci_info->io_size, 486 PCI_REGION_IO); 487 488 hose->region_count = r - hose->regions; 489 hose->first_busno = busno; 490 491 fsl_pci_init(hose, pci_info); 492 493 if (fsl_is_pci_agent(hose)) { 494 fsl_pci_config_unlock(hose); 495 hose->last_busno = hose->first_busno; 496 } 497 498 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 499 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? 500 "e" : "", pci_info->pci_num, 501 hose->first_busno, hose->last_busno); 502 503 return(hose->last_busno + 1); 504 } 505 506 /* Enable inbound PCI config cycles for agent/endpoint interface */ 507 void fsl_pci_config_unlock(struct pci_controller *hose) 508 { 509 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); 510 u8 agent; 511 u8 pcie_cap; 512 u16 pbfr; 513 514 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent); 515 if (!agent) 516 return; 517 518 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 519 if (pcie_cap != 0x0) { 520 /* PCIe - set CFG_READY bit of Configuration Ready Register */ 521 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); 522 } else { 523 /* PCI - clear ACL bit of PBFR */ 524 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); 525 pbfr &= ~0x20; 526 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr); 527 } 528 } 529 530 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \ 531 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4) 532 int fsl_configure_pcie(struct fsl_pci_info *info, 533 struct pci_controller *hose, 534 const char *connected, int busno) 535 { 536 int is_endpoint; 537 538 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); 539 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); 540 541 is_endpoint = fsl_setup_hose(hose, info->regs); 542 printf("PCIe%u: %s", info->pci_num, 543 is_endpoint ? "Endpoint" : "Root Complex"); 544 if (connected) 545 printf(" of %s", connected); 546 puts(", "); 547 548 return fsl_pci_init_port(info, hose, busno); 549 } 550 551 #if defined(CONFIG_FSL_CORENET) 552 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1 553 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2 554 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3 555 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4 556 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 557 #elif defined(CONFIG_MPC85xx) 558 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE 559 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 560 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 561 #define _DEVDISR_PCIE4 0 562 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 563 #elif defined(CONFIG_MPC86xx) 564 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1 565 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2 566 #define _DEVDISR_PCIE3 0 567 #define _DEVDISR_PCIE4 0 568 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ 569 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) 570 #else 571 #error "No defines for DEVDISR_PCIE" 572 #endif 573 574 /* Implement a dummy function for those platforms w/o SERDES */ 575 static const char *__board_serdes_name(enum srds_prtcl device) 576 { 577 switch (device) { 578 #ifdef CONFIG_SYS_PCIE1_NAME 579 case PCIE1: 580 return CONFIG_SYS_PCIE1_NAME; 581 #endif 582 #ifdef CONFIG_SYS_PCIE2_NAME 583 case PCIE2: 584 return CONFIG_SYS_PCIE2_NAME; 585 #endif 586 #ifdef CONFIG_SYS_PCIE3_NAME 587 case PCIE3: 588 return CONFIG_SYS_PCIE3_NAME; 589 #endif 590 #ifdef CONFIG_SYS_PCIE4_NAME 591 case PCIE4: 592 return CONFIG_SYS_PCIE4_NAME; 593 #endif 594 default: 595 return NULL; 596 } 597 598 return NULL; 599 } 600 601 __attribute__((weak, alias("__board_serdes_name"))) const char * 602 board_serdes_name(enum srds_prtcl device); 603 604 static u32 devdisr_mask[] = { 605 _DEVDISR_PCIE1, 606 _DEVDISR_PCIE2, 607 _DEVDISR_PCIE3, 608 _DEVDISR_PCIE4, 609 }; 610 611 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 612 struct fsl_pci_info *pci_info) 613 { 614 struct pci_controller *hose; 615 int num = dev - PCIE1; 616 617 hose = calloc(1, sizeof(struct pci_controller)); 618 if (!hose) 619 return busno; 620 621 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) { 622 busno = fsl_configure_pcie(pci_info, hose, 623 board_serdes_name(dev), busno); 624 } else { 625 printf("PCIe%d: disabled\n", num + 1); 626 } 627 628 return busno; 629 } 630 631 int fsl_pcie_init_board(int busno) 632 { 633 struct fsl_pci_info pci_info; 634 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; 635 u32 devdisr = in_be32(&gur->devdisr); 636 637 #ifdef CONFIG_PCIE1 638 SET_STD_PCIE_INFO(pci_info, 1); 639 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); 640 #else 641 setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ 642 #endif 643 644 #ifdef CONFIG_PCIE2 645 SET_STD_PCIE_INFO(pci_info, 2); 646 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info); 647 #else 648 setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ 649 #endif 650 651 #ifdef CONFIG_PCIE3 652 SET_STD_PCIE_INFO(pci_info, 3); 653 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info); 654 #else 655 setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */ 656 #endif 657 658 #ifdef CONFIG_PCIE4 659 SET_STD_PCIE_INFO(pci_info, 4); 660 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info); 661 #else 662 setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */ 663 #endif 664 665 return busno; 666 } 667 #else 668 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 669 struct fsl_pci_info *pci_info) 670 { 671 return busno; 672 } 673 674 int fsl_pcie_init_board(int busno) 675 { 676 return busno; 677 } 678 #endif 679 680 #ifdef CONFIG_OF_BOARD_SETUP 681 #include <libfdt.h> 682 #include <fdt_support.h> 683 684 void ft_fsl_pci_setup(void *blob, const char *pci_compat, 685 unsigned long ctrl_addr) 686 { 687 int off; 688 u32 bus_range[2]; 689 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr; 690 struct pci_controller *hose; 691 692 hose = find_hose_by_cfg_addr((void *)(ctrl_addr)); 693 694 /* convert ctrl_addr to true physical address */ 695 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR; 696 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS; 697 698 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr); 699 700 if (off < 0) 701 return; 702 703 /* We assume a cfg_addr not being set means we didn't setup the controller */ 704 if ((hose == NULL) || (hose->cfg_addr == NULL)) { 705 fdt_del_node(blob, off); 706 } else { 707 bus_range[0] = 0; 708 bus_range[1] = hose->last_busno - hose->first_busno; 709 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); 710 fdt_pci_dma_ranges(blob, off, hose); 711 } 712 } 713 #endif 714