1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <malloc.h> 22 #include <asm/fsl_serdes.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* 27 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 28 * 29 * Initialize controller and call the common driver/pci pci_hose_scan to 30 * scan for bridges and devices. 31 * 32 * Hose fields which need to be pre-initialized by board specific code: 33 * regions[] 34 * first_busno 35 * 36 * Fields updated: 37 * last_busno 38 */ 39 40 #include <pci.h> 41 #include <asm/io.h> 42 #include <asm/fsl_pci.h> 43 44 /* Freescale-specific PCI config registers */ 45 #define FSL_PCI_PBFR 0x44 46 #define FSL_PCIE_CAP_ID 0x4c 47 #define FSL_PCIE_CFG_RDY 0x4b0 48 #define FSL_PROG_IF_AGENT 0x1 49 50 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 51 #define CONFIG_SYS_PCI_MEMORY_BUS 0 52 #endif 53 54 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 55 #define CONFIG_SYS_PCI_MEMORY_PHYS 0 56 #endif 57 58 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) 59 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) 60 #endif 61 62 /* Setup one inbound ATMU window. 63 * 64 * We let the caller decide what the window size should be 65 */ 66 static void set_inbound_window(volatile pit_t *pi, 67 struct pci_region *r, 68 u64 size) 69 { 70 u32 sz = (__ilog2_u64(size) - 1); 71 u32 flag = PIWAR_EN | PIWAR_LOCAL | 72 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 73 74 out_be32(&pi->pitar, r->phys_start >> 12); 75 out_be32(&pi->piwbar, r->bus_start >> 12); 76 #ifdef CONFIG_SYS_PCI_64BIT 77 out_be32(&pi->piwbear, r->bus_start >> 44); 78 #else 79 out_be32(&pi->piwbear, 0); 80 #endif 81 if (r->flags & PCI_REGION_PREFETCH) 82 flag |= PIWAR_PF; 83 out_be32(&pi->piwar, flag | sz); 84 } 85 86 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) 87 { 88 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr; 89 90 /* Reset hose to make sure its in a clean state */ 91 memset(hose, 0, sizeof(struct pci_controller)); 92 93 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 94 95 return fsl_is_pci_agent(hose); 96 } 97 98 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, 99 u64 out_lo, u8 pcie_cap, 100 volatile pit_t *pi) 101 { 102 struct pci_region *r = hose->regions + hose->region_count; 103 u64 sz = min((u64)gd->ram_size, (1ull << 32)); 104 105 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; 106 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; 107 pci_size_t pci_sz; 108 109 /* we have no space available for inbound memory mapping */ 110 if (bus_start > out_lo) { 111 printf ("no space for inbound mapping of memory\n"); 112 return 0; 113 } 114 115 /* limit size */ 116 if ((bus_start + sz) > out_lo) { 117 sz = out_lo - bus_start; 118 debug ("limiting size to %llx\n", sz); 119 } 120 121 pci_sz = 1ull << __ilog2_u64(sz); 122 /* 123 * we can overlap inbound/outbound windows on PCI-E since RX & TX 124 * links a separate 125 */ 126 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) { 127 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 128 (u64)bus_start, (u64)phys_start, (u64)sz); 129 pci_set_region(r, bus_start, phys_start, sz, 130 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 131 PCI_REGION_PREFETCH); 132 133 /* if we aren't an exact power of two match, pci_sz is smaller 134 * round it up to the next power of two. We report the actual 135 * size to pci region tracking. 136 */ 137 if (pci_sz != sz) 138 sz = 2ull << __ilog2_u64(sz); 139 140 set_inbound_window(pi--, r++, sz); 141 sz = 0; /* make sure we dont set the R2 window */ 142 } else { 143 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 144 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 145 pci_set_region(r, bus_start, phys_start, pci_sz, 146 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 147 PCI_REGION_PREFETCH); 148 set_inbound_window(pi--, r++, pci_sz); 149 150 sz -= pci_sz; 151 bus_start += pci_sz; 152 phys_start += pci_sz; 153 154 pci_sz = 1ull << __ilog2_u64(sz); 155 if (sz) { 156 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", 157 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 158 pci_set_region(r, bus_start, phys_start, pci_sz, 159 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 160 PCI_REGION_PREFETCH); 161 set_inbound_window(pi--, r++, pci_sz); 162 sz -= pci_sz; 163 bus_start += pci_sz; 164 phys_start += pci_sz; 165 } 166 } 167 168 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) 169 /* 170 * On 64-bit capable systems, set up a mapping for all of DRAM 171 * in high pci address space. 172 */ 173 pci_sz = 1ull << __ilog2_u64(gd->ram_size); 174 /* round up to the next largest power of two */ 175 if (gd->ram_size > pci_sz) 176 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); 177 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", 178 (u64)CONFIG_SYS_PCI64_MEMORY_BUS, 179 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, 180 (u64)pci_sz); 181 pci_set_region(r, 182 CONFIG_SYS_PCI64_MEMORY_BUS, 183 CONFIG_SYS_PCI_MEMORY_PHYS, 184 pci_sz, 185 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 186 PCI_REGION_PREFETCH); 187 set_inbound_window(pi--, r++, pci_sz); 188 #else 189 pci_sz = 1ull << __ilog2_u64(sz); 190 if (sz) { 191 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", 192 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 193 pci_set_region(r, bus_start, phys_start, pci_sz, 194 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 195 PCI_REGION_PREFETCH); 196 sz -= pci_sz; 197 bus_start += pci_sz; 198 phys_start += pci_sz; 199 set_inbound_window(pi--, r++, pci_sz); 200 } 201 #endif 202 203 #ifdef CONFIG_PHYS_64BIT 204 if (sz && (((u64)gd->ram_size) < (1ull << 32))) 205 printf("Was not able to map all of memory via " 206 "inbound windows -- %lld remaining\n", sz); 207 #endif 208 209 hose->region_count = r - hose->regions; 210 211 return 1; 212 } 213 214 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) 215 { 216 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; 217 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; 218 u16 temp16; 219 u32 temp32; 220 u32 block_rev; 221 int enabled, r, inbound = 0; 222 u16 ltssm; 223 u8 temp8, pcie_cap; 224 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; 225 struct pci_region *reg = hose->regions + hose->region_count; 226 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 227 228 /* Initialize ATMU registers based on hose regions and flags */ 229 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ 230 volatile pit_t *pi; 231 232 u64 out_hi = 0, out_lo = -1ULL; 233 u32 pcicsrbar, pcicsrbar_sz; 234 235 pci_setup_indirect(hose, cfg_addr, cfg_data); 236 237 block_rev = in_be32(&pci->block_rev1); 238 if (PEX_IP_BLK_REV_2_2 <= block_rev) { 239 pi = &pci->pit[2]; /* 0xDC0 */ 240 } else { 241 pi = &pci->pit[3]; /* 0xDE0 */ 242 } 243 244 /* Handle setup of outbound windows first */ 245 for (r = 0; r < hose->region_count; r++) { 246 unsigned long flags = hose->regions[r].flags; 247 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); 248 249 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE; 250 if (flags != PCI_REGION_SYS_MEMORY) { 251 u64 start = hose->regions[r].bus_start; 252 u64 end = start + hose->regions[r].size; 253 254 out_be32(&po->powbar, hose->regions[r].phys_start >> 12); 255 out_be32(&po->potar, start >> 12); 256 #ifdef CONFIG_SYS_PCI_64BIT 257 out_be32(&po->potear, start >> 44); 258 #else 259 out_be32(&po->potear, 0); 260 #endif 261 if (hose->regions[r].flags & PCI_REGION_IO) { 262 out_be32(&po->powar, POWAR_EN | sz | 263 POWAR_IO_READ | POWAR_IO_WRITE); 264 } else { 265 out_be32(&po->powar, POWAR_EN | sz | 266 POWAR_MEM_READ | POWAR_MEM_WRITE); 267 out_lo = min(start, out_lo); 268 out_hi = max(end, out_hi); 269 } 270 po++; 271 } 272 } 273 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi); 274 275 /* setup PCSRBAR/PEXCSRBAR */ 276 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); 277 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 278 pcicsrbar_sz = ~pcicsrbar_sz + 1; 279 280 if (out_hi < (0x100000000ull - pcicsrbar_sz) || 281 (out_lo > 0x100000000ull)) 282 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 283 else 284 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz; 285 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar); 286 287 out_lo = min(out_lo, (u64)pcicsrbar); 288 289 debug("PCICSRBAR @ 0x%x\n", pcicsrbar); 290 291 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS, 292 pcicsrbar_sz, PCI_REGION_SYS_MEMORY); 293 hose->region_count++; 294 295 /* see if we are a PCIe or PCI controller */ 296 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 297 298 /* inbound */ 299 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi); 300 301 for (r = 0; r < hose->region_count; r++) 302 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r, 303 (u64)hose->regions[r].phys_start, 304 (u64)hose->regions[r].bus_start, 305 (u64)hose->regions[r].size, 306 hose->regions[r].flags); 307 308 pci_register_hose(hose); 309 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 310 hose->current_busno = hose->first_busno; 311 312 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */ 313 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except 314 * - Master abort (pci) 315 * - Master PERR (pci) 316 * - ICCA (PCIe) 317 */ 318 pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32); 319 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 320 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); 321 322 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) 323 temp32 = 0; 324 pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32); 325 temp32 &= ~0x03; /* Disable ASPM */ 326 pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32); 327 udelay(1); 328 #endif 329 if (pcie_cap == PCI_CAP_ID_EXP) { 330 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 331 enabled = ltssm >= PCI_LTSSM_L0; 332 333 #ifdef CONFIG_FSL_PCIE_RESET 334 if (ltssm == 1) { 335 int i; 336 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm); 337 /* assert PCIe reset */ 338 setbits_be32(&pci->pdb_stat, 0x08000000); 339 (void) in_be32(&pci->pdb_stat); 340 udelay(100); 341 debug(" Asserting PCIe reset @%p = %x\n", 342 &pci->pdb_stat, in_be32(&pci->pdb_stat)); 343 /* clear PCIe reset */ 344 clrbits_be32(&pci->pdb_stat, 0x08000000); 345 asm("sync;isync"); 346 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { 347 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 348 <ssm); 349 udelay(1000); 350 debug("....PCIe link error. " 351 "LTSSM=0x%02x.\n", ltssm); 352 } 353 enabled = ltssm >= PCI_LTSSM_L0; 354 355 /* we need to re-write the bar0 since a reset will 356 * clear it 357 */ 358 pci_hose_write_config_dword(hose, dev, 359 PCI_BASE_ADDRESS_0, pcicsrbar); 360 } 361 #endif 362 363 if (!enabled) { 364 /* Let the user know there's no PCIe link */ 365 printf("no link, regs @ 0x%lx\n", pci_info->regs); 366 hose->last_busno = hose->first_busno; 367 return; 368 } 369 370 out_be32(&pci->pme_msg_det, 0xffffffff); 371 out_be32(&pci->pme_msg_int_en, 0xffffffff); 372 373 /* Print the negotiated PCIe link width */ 374 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); 375 printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, 376 pci_info->regs); 377 378 hose->current_busno++; /* Start scan with secondary */ 379 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 380 } 381 382 /* Use generic setup_device to initialize standard pci regs, 383 * but do not allocate any windows since any BAR found (such 384 * as PCSRBAR) is not in this cpu's memory space. 385 */ 386 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 387 hose->pci_prefetch, hose->pci_io); 388 389 if (inbound) { 390 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 391 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 392 temp16 | PCI_COMMAND_MEMORY); 393 } 394 395 #ifndef CONFIG_PCI_NOSCAN 396 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); 397 398 /* Programming Interface (PCI_CLASS_PROG) 399 * 0 == pci host or pcie root-complex, 400 * 1 == pci agent or pcie end-point 401 */ 402 if (!temp8) { 403 debug(" Scanning PCI bus %02x\n", 404 hose->current_busno); 405 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); 406 } else { 407 debug(" Not scanning PCI bus %02x. PI=%x\n", 408 hose->current_busno, temp8); 409 hose->last_busno = hose->current_busno; 410 } 411 412 /* if we are PCIe - update limit regs and subordinate busno 413 * for the virtual P2P bridge 414 */ 415 if (pcie_cap == PCI_CAP_ID_EXP) { 416 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 417 } 418 #else 419 hose->last_busno = hose->current_busno; 420 #endif 421 422 /* Clear all error indications */ 423 if (pcie_cap == PCI_CAP_ID_EXP) 424 out_be32(&pci->pme_msg_det, 0xffffffff); 425 out_be32(&pci->pedr, 0xffffffff); 426 427 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); 428 if (temp16) { 429 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff); 430 } 431 432 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 433 if (temp16) { 434 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 435 } 436 } 437 438 int fsl_is_pci_agent(struct pci_controller *hose) 439 { 440 u8 prog_if; 441 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 442 443 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); 444 445 return (prog_if == FSL_PROG_IF_AGENT); 446 } 447 448 int fsl_pci_init_port(struct fsl_pci_info *pci_info, 449 struct pci_controller *hose, int busno) 450 { 451 volatile ccsr_fsl_pci_t *pci; 452 struct pci_region *r; 453 pci_dev_t dev = PCI_BDF(busno,0,0); 454 u8 pcie_cap; 455 456 pci = (ccsr_fsl_pci_t *) pci_info->regs; 457 458 /* on non-PCIe controllers we don't have pme_msg_det so this code 459 * should do nothing since the read will return 0 460 */ 461 if (in_be32(&pci->pme_msg_det)) { 462 out_be32(&pci->pme_msg_det, 0xffffffff); 463 debug (" with errors. Clearing. Now 0x%08x", 464 pci->pme_msg_det); 465 } 466 467 r = hose->regions + hose->region_count; 468 469 /* outbound memory */ 470 pci_set_region(r++, 471 pci_info->mem_bus, 472 pci_info->mem_phys, 473 pci_info->mem_size, 474 PCI_REGION_MEM); 475 476 /* outbound io */ 477 pci_set_region(r++, 478 pci_info->io_bus, 479 pci_info->io_phys, 480 pci_info->io_size, 481 PCI_REGION_IO); 482 483 hose->region_count = r - hose->regions; 484 hose->first_busno = busno; 485 486 fsl_pci_init(hose, pci_info); 487 488 if (fsl_is_pci_agent(hose)) { 489 fsl_pci_config_unlock(hose); 490 hose->last_busno = hose->first_busno; 491 } 492 493 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 494 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? 495 "e" : "", pci_info->pci_num, 496 hose->first_busno, hose->last_busno); 497 498 return(hose->last_busno + 1); 499 } 500 501 /* Enable inbound PCI config cycles for agent/endpoint interface */ 502 void fsl_pci_config_unlock(struct pci_controller *hose) 503 { 504 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); 505 u8 agent; 506 u8 pcie_cap; 507 u16 pbfr; 508 509 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent); 510 if (!agent) 511 return; 512 513 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 514 if (pcie_cap != 0x0) { 515 /* PCIe - set CFG_READY bit of Configuration Ready Register */ 516 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); 517 } else { 518 /* PCI - clear ACL bit of PBFR */ 519 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); 520 pbfr &= ~0x20; 521 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr); 522 } 523 } 524 525 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \ 526 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4) 527 int fsl_configure_pcie(struct fsl_pci_info *info, 528 struct pci_controller *hose, 529 const char *connected, int busno) 530 { 531 int is_endpoint; 532 533 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); 534 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); 535 536 is_endpoint = fsl_setup_hose(hose, info->regs); 537 printf("PCIe%u: %s", info->pci_num, 538 is_endpoint ? "Endpoint" : "Root Complex"); 539 if (connected) 540 printf(" of %s", connected); 541 puts(", "); 542 543 return fsl_pci_init_port(info, hose, busno); 544 } 545 546 #if defined(CONFIG_FSL_CORENET) 547 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1 548 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2 549 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3 550 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4 551 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 552 #elif defined(CONFIG_MPC85xx) 553 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE 554 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 555 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 556 #define _DEVDISR_PCIE4 0 557 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 558 #elif defined(CONFIG_MPC86xx) 559 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1 560 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2 561 #define _DEVDISR_PCIE3 0 562 #define _DEVDISR_PCIE4 0 563 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ 564 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) 565 #else 566 #error "No defines for DEVDISR_PCIE" 567 #endif 568 569 /* Implement a dummy function for those platforms w/o SERDES */ 570 static const char *__board_serdes_name(enum srds_prtcl device) 571 { 572 switch (device) { 573 #ifdef CONFIG_SYS_PCIE1_NAME 574 case PCIE1: 575 return CONFIG_SYS_PCIE1_NAME; 576 #endif 577 #ifdef CONFIG_SYS_PCIE2_NAME 578 case PCIE2: 579 return CONFIG_SYS_PCIE2_NAME; 580 #endif 581 #ifdef CONFIG_SYS_PCIE3_NAME 582 case PCIE3: 583 return CONFIG_SYS_PCIE3_NAME; 584 #endif 585 #ifdef CONFIG_SYS_PCIE4_NAME 586 case PCIE4: 587 return CONFIG_SYS_PCIE4_NAME; 588 #endif 589 default: 590 return NULL; 591 } 592 593 return NULL; 594 } 595 596 __attribute__((weak, alias("__board_serdes_name"))) const char * 597 board_serdes_name(enum srds_prtcl device); 598 599 static u32 devdisr_mask[] = { 600 _DEVDISR_PCIE1, 601 _DEVDISR_PCIE2, 602 _DEVDISR_PCIE3, 603 _DEVDISR_PCIE4, 604 }; 605 606 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 607 struct fsl_pci_info *pci_info) 608 { 609 struct pci_controller *hose; 610 int num = dev - PCIE1; 611 612 hose = calloc(1, sizeof(struct pci_controller)); 613 if (!hose) 614 return busno; 615 616 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) { 617 busno = fsl_configure_pcie(pci_info, hose, 618 board_serdes_name(dev), busno); 619 } else { 620 printf("PCIe%d: disabled\n", num + 1); 621 } 622 623 return busno; 624 } 625 626 int fsl_pcie_init_board(int busno) 627 { 628 struct fsl_pci_info pci_info; 629 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; 630 u32 devdisr = in_be32(&gur->devdisr); 631 632 #ifdef CONFIG_PCIE1 633 SET_STD_PCIE_INFO(pci_info, 1); 634 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); 635 #else 636 setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ 637 #endif 638 639 #ifdef CONFIG_PCIE2 640 SET_STD_PCIE_INFO(pci_info, 2); 641 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info); 642 #else 643 setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ 644 #endif 645 646 #ifdef CONFIG_PCIE3 647 SET_STD_PCIE_INFO(pci_info, 3); 648 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info); 649 #else 650 setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */ 651 #endif 652 653 #ifdef CONFIG_PCIE4 654 SET_STD_PCIE_INFO(pci_info, 4); 655 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info); 656 #else 657 setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */ 658 #endif 659 660 return busno; 661 } 662 #else 663 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 664 struct fsl_pci_info *pci_info) 665 { 666 return busno; 667 } 668 669 int fsl_pcie_init_board(int busno) 670 { 671 return busno; 672 } 673 #endif 674 675 #ifdef CONFIG_OF_BOARD_SETUP 676 #include <libfdt.h> 677 #include <fdt_support.h> 678 679 void ft_fsl_pci_setup(void *blob, const char *pci_compat, 680 unsigned long ctrl_addr) 681 { 682 int off; 683 u32 bus_range[2]; 684 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr; 685 struct pci_controller *hose; 686 687 hose = find_hose_by_cfg_addr((void *)(ctrl_addr)); 688 689 /* convert ctrl_addr to true physical address */ 690 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR; 691 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS; 692 693 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr); 694 695 if (off < 0) 696 return; 697 698 /* We assume a cfg_addr not being set means we didn't setup the controller */ 699 if ((hose == NULL) || (hose->cfg_addr == NULL)) { 700 fdt_del_node(blob, off); 701 } else { 702 bus_range[0] = 0; 703 bus_range[1] = hose->last_busno - hose->first_busno; 704 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); 705 fdt_pci_dma_ranges(blob, off, hose); 706 } 707 } 708 #endif 709