1 /* 2 * Copyright (C) 2014 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <pch.h> 10 11 #define BIOS_CTRL 0xd8 12 13 static int pch7_get_sbase(struct udevice *dev, ulong *sbasep) 14 { 15 u32 rcba; 16 17 dm_pci_read_config32(dev, PCH_RCBA, &rcba); 18 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ 19 rcba = rcba & 0xffffc000; 20 *sbasep = rcba + 0x3020; 21 22 return 0; 23 } 24 25 static int pch7_set_spi_protect(struct udevice *dev, bool protect) 26 { 27 uint8_t bios_cntl; 28 29 /* Adjust the BIOS write protect to dis/allow write commands */ 30 dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl); 31 if (protect) 32 bios_cntl &= ~BIOS_CTRL_BIOSWE; 33 else 34 bios_cntl |= BIOS_CTRL_BIOSWE; 35 dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl); 36 37 return 0; 38 } 39 40 static const struct pch_ops pch7_ops = { 41 .get_sbase = pch7_get_sbase, 42 .set_spi_protect = pch7_set_spi_protect, 43 }; 44 45 static const struct udevice_id pch7_ids[] = { 46 { .compatible = "intel,pch7" }, 47 { } 48 }; 49 50 U_BOOT_DRIVER(pch7_drv) = { 51 .name = "intel-pch7", 52 .id = UCLASS_PCH, 53 .of_match = pch7_ids, 54 .ops = &pch7_ops, 55 }; 56