1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <net.h> 14 #include <netdev.h> 15 #include <config.h> 16 #include <fdtdec.h> 17 #include <libfdt.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <phy.h> 21 #include <miiphy.h> 22 #include <watchdog.h> 23 #include <asm/system.h> 24 #include <asm/arch/hardware.h> 25 #include <asm/arch/sys_proto.h> 26 27 #if !defined(CONFIG_PHYLIB) 28 # error XILINX_GEM_ETHERNET requires PHYLIB 29 #endif 30 31 /* Bit/mask specification */ 32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 37 38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 41 42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 45 46 /* Wrap bit, last descriptor */ 47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 49 50 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 51 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 52 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 53 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 54 55 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 56 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 57 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 58 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 59 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ 60 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ 61 62 #ifdef CONFIG_ARM64 63 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 64 #else 65 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 66 #endif 67 68 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 69 ZYNQ_GEM_NWCFG_FDEN | \ 70 ZYNQ_GEM_NWCFG_FSREM | \ 71 ZYNQ_GEM_NWCFG_MDCCLKDIV) 72 73 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 74 75 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 76 /* Use full configured addressable space (8 Kb) */ 77 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 78 /* Use full configured addressable space (4 Kb) */ 79 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 80 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 81 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 82 83 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 84 ZYNQ_GEM_DMACR_RXSIZE | \ 85 ZYNQ_GEM_DMACR_TXSIZE | \ 86 ZYNQ_GEM_DMACR_RXBUF) 87 88 /* Use MII register 1 (MII status register) to detect PHY */ 89 #define PHY_DETECT_REG 1 90 91 /* Mask used to verify certain PHY features (or register contents) 92 * in the register above: 93 * 0x1000: 10Mbps full duplex support 94 * 0x0800: 10Mbps half duplex support 95 * 0x0008: Auto-negotiation support 96 */ 97 #define PHY_DETECT_MASK 0x1808 98 99 /* TX BD status masks */ 100 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 101 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 102 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 103 104 /* Clock frequencies for different speeds */ 105 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 106 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 107 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 108 109 /* Device registers */ 110 struct zynq_gem_regs { 111 u32 nwctrl; /* Network Control reg */ 112 u32 nwcfg; /* Network Config reg */ 113 u32 nwsr; /* Network Status reg */ 114 u32 reserved1; 115 u32 dmacr; /* DMA Control reg */ 116 u32 txsr; /* TX Status reg */ 117 u32 rxqbase; /* RX Q Base address reg */ 118 u32 txqbase; /* TX Q Base address reg */ 119 u32 rxsr; /* RX Status reg */ 120 u32 reserved2[2]; 121 u32 idr; /* Interrupt Disable reg */ 122 u32 reserved3; 123 u32 phymntnc; /* Phy Maintaince reg */ 124 u32 reserved4[18]; 125 u32 hashl; /* Hash Low address reg */ 126 u32 hashh; /* Hash High address reg */ 127 #define LADDR_LOW 0 128 #define LADDR_HIGH 1 129 u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */ 130 u32 match[4]; /* Type ID1 Match reg */ 131 u32 reserved6[18]; 132 u32 stat[44]; /* Octects transmitted Low reg - stat start */ 133 }; 134 135 /* BD descriptors */ 136 struct emac_bd { 137 u32 addr; /* Next descriptor pointer */ 138 u32 status; 139 }; 140 141 #define RX_BUF 32 142 /* Page table entries are set to 1MB, or multiples of 1MB 143 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 144 */ 145 #define BD_SPACE 0x100000 146 /* BD separation space */ 147 #define BD_SEPRN_SPACE 64 148 149 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 150 struct zynq_gem_priv { 151 struct emac_bd *tx_bd; 152 struct emac_bd *rx_bd; 153 char *rxbuffers; 154 u32 rxbd_current; 155 u32 rx_first_buf; 156 int phyaddr; 157 u32 emio; 158 int init; 159 struct phy_device *phydev; 160 struct mii_dev *bus; 161 }; 162 163 static inline int mdio_wait(struct eth_device *dev) 164 { 165 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 166 u32 timeout = 20000; 167 168 /* Wait till MDIO interface is ready to accept a new transaction. */ 169 while (--timeout) { 170 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 171 break; 172 WATCHDOG_RESET(); 173 } 174 175 if (!timeout) { 176 printf("%s: Timeout\n", __func__); 177 return 1; 178 } 179 180 return 0; 181 } 182 183 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, 184 u32 op, u16 *data) 185 { 186 u32 mgtcr; 187 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 188 189 if (mdio_wait(dev)) 190 return 1; 191 192 /* Construct mgtcr mask for the operation */ 193 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 194 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 195 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 196 197 /* Write mgtcr and wait for completion */ 198 writel(mgtcr, ®s->phymntnc); 199 200 if (mdio_wait(dev)) 201 return 1; 202 203 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 204 *data = readl(®s->phymntnc); 205 206 return 0; 207 } 208 209 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) 210 { 211 return phy_setup_op(dev, phy_addr, regnum, 212 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 213 } 214 215 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) 216 { 217 return phy_setup_op(dev, phy_addr, regnum, 218 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 219 } 220 221 static void phy_detection(struct eth_device *dev) 222 { 223 int i; 224 u16 phyreg; 225 struct zynq_gem_priv *priv = dev->priv; 226 227 if (priv->phyaddr != -1) { 228 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); 229 if ((phyreg != 0xFFFF) && 230 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 231 /* Found a valid PHY address */ 232 debug("Default phy address %d is valid\n", 233 priv->phyaddr); 234 return; 235 } else { 236 debug("PHY address is not setup correctly %d\n", 237 priv->phyaddr); 238 priv->phyaddr = -1; 239 } 240 } 241 242 debug("detecting phy address\n"); 243 if (priv->phyaddr == -1) { 244 /* detect the PHY address */ 245 for (i = 31; i >= 0; i--) { 246 phyread(dev, i, PHY_DETECT_REG, &phyreg); 247 if ((phyreg != 0xFFFF) && 248 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 249 /* Found a valid PHY address */ 250 priv->phyaddr = i; 251 debug("Found valid phy address, %d\n", i); 252 return; 253 } 254 } 255 } 256 printf("PHY is not detected\n"); 257 } 258 259 static int zynq_gem_setup_mac(struct eth_device *dev) 260 { 261 u32 i, macaddrlow, macaddrhigh; 262 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 263 264 /* Set the MAC bits [31:0] in BOT */ 265 macaddrlow = dev->enetaddr[0]; 266 macaddrlow |= dev->enetaddr[1] << 8; 267 macaddrlow |= dev->enetaddr[2] << 16; 268 macaddrlow |= dev->enetaddr[3] << 24; 269 270 /* Set MAC bits [47:32] in TOP */ 271 macaddrhigh = dev->enetaddr[4]; 272 macaddrhigh |= dev->enetaddr[5] << 8; 273 274 for (i = 0; i < 4; i++) { 275 writel(0, ®s->laddr[i][LADDR_LOW]); 276 writel(0, ®s->laddr[i][LADDR_HIGH]); 277 /* Do not use MATCHx register */ 278 writel(0, ®s->match[i]); 279 } 280 281 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 282 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 283 284 return 0; 285 } 286 287 static int zynq_gem_init(struct eth_device *dev, bd_t * bis) 288 { 289 u32 i; 290 unsigned long clk_rate = 0; 291 struct phy_device *phydev; 292 const u32 stat_size = (sizeof(struct zynq_gem_regs) - 293 offsetof(struct zynq_gem_regs, stat)) / 4; 294 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 295 struct zynq_gem_priv *priv = dev->priv; 296 const u32 supported = SUPPORTED_10baseT_Half | 297 SUPPORTED_10baseT_Full | 298 SUPPORTED_100baseT_Half | 299 SUPPORTED_100baseT_Full | 300 SUPPORTED_1000baseT_Half | 301 SUPPORTED_1000baseT_Full; 302 303 if (!priv->init) { 304 /* Disable all interrupts */ 305 writel(0xFFFFFFFF, ®s->idr); 306 307 /* Disable the receiver & transmitter */ 308 writel(0, ®s->nwctrl); 309 writel(0, ®s->txsr); 310 writel(0, ®s->rxsr); 311 writel(0, ®s->phymntnc); 312 313 /* Clear the Hash registers for the mac address 314 * pointed by AddressPtr 315 */ 316 writel(0x0, ®s->hashl); 317 /* Write bits [63:32] in TOP */ 318 writel(0x0, ®s->hashh); 319 320 /* Clear all counters */ 321 for (i = 0; i <= stat_size; i++) 322 readl(®s->stat[i]); 323 324 /* Setup RxBD space */ 325 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 326 327 for (i = 0; i < RX_BUF; i++) { 328 priv->rx_bd[i].status = 0xF0000000; 329 priv->rx_bd[i].addr = 330 ((u32)(priv->rxbuffers) + 331 (i * PKTSIZE_ALIGN)); 332 } 333 /* WRAP bit to last BD */ 334 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 335 /* Write RxBDs to IP */ 336 writel((u32)priv->rx_bd, ®s->rxqbase); 337 338 /* Setup for DMA Configuration register */ 339 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 340 341 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 342 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 343 344 priv->init++; 345 } 346 347 phy_detection(dev); 348 349 /* interface - look at tsec */ 350 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 351 PHY_INTERFACE_MODE_MII); 352 353 phydev->supported = supported | ADVERTISED_Pause | 354 ADVERTISED_Asym_Pause; 355 phydev->advertising = phydev->supported; 356 priv->phydev = phydev; 357 phy_config(phydev); 358 phy_startup(phydev); 359 360 if (!phydev->link) { 361 printf("%s: No link.\n", phydev->dev->name); 362 return -1; 363 } 364 365 switch (phydev->speed) { 366 case SPEED_1000: 367 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 368 ®s->nwcfg); 369 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 370 break; 371 case SPEED_100: 372 clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, 373 ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); 374 clk_rate = ZYNQ_GEM_FREQUENCY_100; 375 break; 376 case SPEED_10: 377 clk_rate = ZYNQ_GEM_FREQUENCY_10; 378 break; 379 } 380 381 /* Change the rclk and clk only not using EMIO interface */ 382 if (!priv->emio) 383 zynq_slcr_gem_clk_setup(dev->iobase != 384 ZYNQ_GEM_BASEADDR0, clk_rate); 385 386 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 387 ZYNQ_GEM_NWCTRL_TXEN_MASK); 388 389 return 0; 390 } 391 392 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) 393 { 394 u32 addr, size; 395 struct zynq_gem_priv *priv = dev->priv; 396 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 397 398 /* setup BD */ 399 writel((u32)priv->tx_bd, ®s->txqbase); 400 401 /* Setup Tx BD */ 402 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 403 404 priv->tx_bd->addr = (u32)ptr; 405 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 406 ZYNQ_GEM_TXBUF_LAST_MASK | 407 ZYNQ_GEM_TXBUF_WRAP_MASK; 408 409 addr = (u32) ptr; 410 addr &= ~(ARCH_DMA_MINALIGN - 1); 411 size = roundup(len, ARCH_DMA_MINALIGN); 412 flush_dcache_range(addr, addr + size); 413 414 addr = (u32)priv->rxbuffers; 415 addr &= ~(ARCH_DMA_MINALIGN - 1); 416 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 417 flush_dcache_range(addr, addr + size); 418 barrier(); 419 420 /* Start transmit */ 421 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 422 423 /* Read TX BD status */ 424 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN) 425 printf("TX underrun\n"); 426 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 427 printf("TX buffers exhausted in mid frame\n"); 428 429 return 0; 430 } 431 432 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 433 static int zynq_gem_recv(struct eth_device *dev) 434 { 435 int frame_len; 436 struct zynq_gem_priv *priv = dev->priv; 437 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 438 struct emac_bd *first_bd; 439 440 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 441 return 0; 442 443 if (!(current_bd->status & 444 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 445 printf("GEM: SOF or EOF not set for last buffer received!\n"); 446 return 0; 447 } 448 449 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 450 if (frame_len) { 451 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 452 addr &= ~(ARCH_DMA_MINALIGN - 1); 453 454 net_process_received_packet((u8 *)addr, frame_len); 455 456 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 457 priv->rx_first_buf = priv->rxbd_current; 458 else { 459 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 460 current_bd->status = 0xF0000000; /* FIXME */ 461 } 462 463 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 464 first_bd = &priv->rx_bd[priv->rx_first_buf]; 465 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 466 first_bd->status = 0xF0000000; 467 } 468 469 if ((++priv->rxbd_current) >= RX_BUF) 470 priv->rxbd_current = 0; 471 } 472 473 return frame_len; 474 } 475 476 static void zynq_gem_halt(struct eth_device *dev) 477 { 478 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 479 480 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 481 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 482 } 483 484 static int zynq_gem_miiphyread(const char *devname, uchar addr, 485 uchar reg, ushort *val) 486 { 487 struct eth_device *dev = eth_get_dev(); 488 int ret; 489 490 ret = phyread(dev, addr, reg, val); 491 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); 492 return ret; 493 } 494 495 static int zynq_gem_miiphy_write(const char *devname, uchar addr, 496 uchar reg, ushort val) 497 { 498 struct eth_device *dev = eth_get_dev(); 499 500 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); 501 return phywrite(dev, addr, reg, val); 502 } 503 504 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, 505 int phy_addr, u32 emio) 506 { 507 struct eth_device *dev; 508 struct zynq_gem_priv *priv; 509 void *bd_space; 510 511 dev = calloc(1, sizeof(*dev)); 512 if (dev == NULL) 513 return -1; 514 515 dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); 516 if (dev->priv == NULL) { 517 free(dev); 518 return -1; 519 } 520 priv = dev->priv; 521 522 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 523 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 524 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 525 526 /* Align bd_space to MMU_SECTION_SHIFT */ 527 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 528 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 529 BD_SPACE, DCACHE_OFF); 530 531 /* Initialize the bd spaces for tx and rx bd's */ 532 priv->tx_bd = (struct emac_bd *)bd_space; 533 priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE); 534 535 priv->phyaddr = phy_addr; 536 priv->emio = emio; 537 538 sprintf(dev->name, "Gem.%lx", base_addr); 539 540 dev->iobase = base_addr; 541 542 dev->init = zynq_gem_init; 543 dev->halt = zynq_gem_halt; 544 dev->send = zynq_gem_send; 545 dev->recv = zynq_gem_recv; 546 dev->write_hwaddr = zynq_gem_setup_mac; 547 548 eth_register(dev); 549 550 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); 551 priv->bus = miiphy_get_dev_by_name(dev->name); 552 553 return 1; 554 } 555 556 #ifdef CONFIG_OF_CONTROL 557 int zynq_gem_of_init(const void *blob) 558 { 559 int offset = 0; 560 u32 ret = 0; 561 u32 reg, phy_reg; 562 563 debug("ZYNQ GEM: Initialization\n"); 564 565 do { 566 offset = fdt_node_offset_by_compatible(blob, offset, 567 "xlnx,ps7-ethernet-1.00.a"); 568 if (offset != -1) { 569 reg = fdtdec_get_addr(blob, offset, "reg"); 570 if (reg != FDT_ADDR_T_NONE) { 571 offset = fdtdec_lookup_phandle(blob, offset, 572 "phy-handle"); 573 if (offset != -1) 574 phy_reg = fdtdec_get_addr(blob, offset, 575 "reg"); 576 else 577 phy_reg = 0; 578 579 debug("ZYNQ GEM: addr %x, phyaddr %x\n", 580 reg, phy_reg); 581 582 ret |= zynq_gem_initialize(NULL, reg, 583 phy_reg, 0); 584 585 } else { 586 debug("ZYNQ GEM: Can't get base address\n"); 587 return -1; 588 } 589 } 590 } while (offset != -1); 591 592 return ret; 593 } 594 #endif 595