1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <net.h> 15 #include <netdev.h> 16 #include <config.h> 17 #include <console.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <phy.h> 21 #include <miiphy.h> 22 #include <wait_bit.h> 23 #include <watchdog.h> 24 #include <asm/system.h> 25 #include <asm/arch/hardware.h> 26 #include <asm/arch/sys_proto.h> 27 #include <asm-generic/errno.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 /* Bit/mask specification */ 32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 37 38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 41 42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 45 46 /* Wrap bit, last descriptor */ 47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 49 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 50 51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 55 56 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 57 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 58 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 59 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 60 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x080000000 /* SGMII Enable */ 61 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x000000800 /* PCS select */ 62 #ifdef CONFIG_ARM64 63 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */ 64 #else 65 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ 66 #endif 67 68 #ifdef CONFIG_ARM64 69 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 70 #else 71 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 72 #endif 73 74 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 75 ZYNQ_GEM_NWCFG_FDEN | \ 76 ZYNQ_GEM_NWCFG_FSREM | \ 77 ZYNQ_GEM_NWCFG_MDCCLKDIV) 78 79 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 80 81 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 82 /* Use full configured addressable space (8 Kb) */ 83 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 84 /* Use full configured addressable space (4 Kb) */ 85 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 86 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 87 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 88 89 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 90 ZYNQ_GEM_DMACR_RXSIZE | \ 91 ZYNQ_GEM_DMACR_TXSIZE | \ 92 ZYNQ_GEM_DMACR_RXBUF) 93 94 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 95 96 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 97 98 /* Use MII register 1 (MII status register) to detect PHY */ 99 #define PHY_DETECT_REG 1 100 101 /* Mask used to verify certain PHY features (or register contents) 102 * in the register above: 103 * 0x1000: 10Mbps full duplex support 104 * 0x0800: 10Mbps half duplex support 105 * 0x0008: Auto-negotiation support 106 */ 107 #define PHY_DETECT_MASK 0x1808 108 109 /* TX BD status masks */ 110 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 111 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 112 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 113 114 /* Clock frequencies for different speeds */ 115 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 116 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 117 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 118 119 /* Device registers */ 120 struct zynq_gem_regs { 121 u32 nwctrl; /* 0x0 - Network Control reg */ 122 u32 nwcfg; /* 0x4 - Network Config reg */ 123 u32 nwsr; /* 0x8 - Network Status reg */ 124 u32 reserved1; 125 u32 dmacr; /* 0x10 - DMA Control reg */ 126 u32 txsr; /* 0x14 - TX Status reg */ 127 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 128 u32 txqbase; /* 0x1c - TX Q Base address reg */ 129 u32 rxsr; /* 0x20 - RX Status reg */ 130 u32 reserved2[2]; 131 u32 idr; /* 0x2c - Interrupt Disable reg */ 132 u32 reserved3; 133 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 134 u32 reserved4[18]; 135 u32 hashl; /* 0x80 - Hash Low address reg */ 136 u32 hashh; /* 0x84 - Hash High address reg */ 137 #define LADDR_LOW 0 138 #define LADDR_HIGH 1 139 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 140 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 141 u32 reserved6[18]; 142 #define STAT_SIZE 44 143 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 144 u32 reserved9[20]; 145 u32 pcscntrl; 146 u32 reserved7[143]; 147 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 148 u32 reserved8[15]; 149 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 150 }; 151 152 /* BD descriptors */ 153 struct emac_bd { 154 u32 addr; /* Next descriptor pointer */ 155 u32 status; 156 }; 157 158 #define RX_BUF 32 159 /* Page table entries are set to 1MB, or multiples of 1MB 160 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 161 */ 162 #define BD_SPACE 0x100000 163 /* BD separation space */ 164 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 165 166 /* Setup the first free TX descriptor */ 167 #define TX_FREE_DESC 2 168 169 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 170 struct zynq_gem_priv { 171 struct emac_bd *tx_bd; 172 struct emac_bd *rx_bd; 173 char *rxbuffers; 174 u32 rxbd_current; 175 u32 rx_first_buf; 176 int phyaddr; 177 u32 emio; 178 int init; 179 struct zynq_gem_regs *iobase; 180 phy_interface_t interface; 181 struct phy_device *phydev; 182 int phy_of_handle; 183 struct mii_dev *bus; 184 }; 185 186 static inline int mdio_wait(struct zynq_gem_regs *regs) 187 { 188 u32 timeout = 20000; 189 190 /* Wait till MDIO interface is ready to accept a new transaction. */ 191 while (--timeout) { 192 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 193 break; 194 WATCHDOG_RESET(); 195 } 196 197 if (!timeout) { 198 printf("%s: Timeout\n", __func__); 199 return 1; 200 } 201 202 return 0; 203 } 204 205 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, 206 u32 op, u16 *data) 207 { 208 u32 mgtcr; 209 struct zynq_gem_regs *regs = priv->iobase; 210 211 if (mdio_wait(regs)) 212 return 1; 213 214 /* Construct mgtcr mask for the operation */ 215 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 216 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 217 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 218 219 /* Write mgtcr and wait for completion */ 220 writel(mgtcr, ®s->phymntnc); 221 222 if (mdio_wait(regs)) 223 return 1; 224 225 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 226 *data = readl(®s->phymntnc); 227 228 return 0; 229 } 230 231 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, 232 u32 regnum, u16 *val) 233 { 234 u32 ret; 235 236 ret = phy_setup_op(priv, phy_addr, regnum, 237 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 238 239 if (!ret) 240 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 241 phy_addr, regnum, *val); 242 243 return ret; 244 } 245 246 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, 247 u32 regnum, u16 data) 248 { 249 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 250 regnum, data); 251 252 return phy_setup_op(priv, phy_addr, regnum, 253 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 254 } 255 256 static int phy_detection(struct udevice *dev) 257 { 258 int i; 259 u16 phyreg; 260 struct zynq_gem_priv *priv = dev->priv; 261 262 if (priv->phyaddr != -1) { 263 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); 264 if ((phyreg != 0xFFFF) && 265 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 266 /* Found a valid PHY address */ 267 debug("Default phy address %d is valid\n", 268 priv->phyaddr); 269 return 0; 270 } else { 271 debug("PHY address is not setup correctly %d\n", 272 priv->phyaddr); 273 priv->phyaddr = -1; 274 } 275 } 276 277 debug("detecting phy address\n"); 278 if (priv->phyaddr == -1) { 279 /* detect the PHY address */ 280 for (i = 31; i >= 0; i--) { 281 phyread(priv, i, PHY_DETECT_REG, &phyreg); 282 if ((phyreg != 0xFFFF) && 283 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 284 /* Found a valid PHY address */ 285 priv->phyaddr = i; 286 debug("Found valid phy address, %d\n", i); 287 return 0; 288 } 289 } 290 } 291 printf("PHY is not detected\n"); 292 return -1; 293 } 294 295 static int zynq_gem_setup_mac(struct udevice *dev) 296 { 297 u32 i, macaddrlow, macaddrhigh; 298 struct eth_pdata *pdata = dev_get_platdata(dev); 299 struct zynq_gem_priv *priv = dev_get_priv(dev); 300 struct zynq_gem_regs *regs = priv->iobase; 301 302 /* Set the MAC bits [31:0] in BOT */ 303 macaddrlow = pdata->enetaddr[0]; 304 macaddrlow |= pdata->enetaddr[1] << 8; 305 macaddrlow |= pdata->enetaddr[2] << 16; 306 macaddrlow |= pdata->enetaddr[3] << 24; 307 308 /* Set MAC bits [47:32] in TOP */ 309 macaddrhigh = pdata->enetaddr[4]; 310 macaddrhigh |= pdata->enetaddr[5] << 8; 311 312 for (i = 0; i < 4; i++) { 313 writel(0, ®s->laddr[i][LADDR_LOW]); 314 writel(0, ®s->laddr[i][LADDR_HIGH]); 315 /* Do not use MATCHx register */ 316 writel(0, ®s->match[i]); 317 } 318 319 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 320 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 321 322 return 0; 323 } 324 325 static int zynq_phy_init(struct udevice *dev) 326 { 327 int ret; 328 struct zynq_gem_priv *priv = dev_get_priv(dev); 329 struct zynq_gem_regs *regs = priv->iobase; 330 const u32 supported = SUPPORTED_10baseT_Half | 331 SUPPORTED_10baseT_Full | 332 SUPPORTED_100baseT_Half | 333 SUPPORTED_100baseT_Full | 334 SUPPORTED_1000baseT_Half | 335 SUPPORTED_1000baseT_Full; 336 337 /* Enable only MDIO bus */ 338 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); 339 340 if (priv->interface != PHY_INTERFACE_MODE_SGMII) { 341 ret = phy_detection(dev); 342 if (ret) { 343 printf("GEM PHY init failed\n"); 344 return ret; 345 } 346 } 347 348 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, 349 priv->interface); 350 if (!priv->phydev) 351 return -ENODEV; 352 353 priv->phydev->supported = supported | ADVERTISED_Pause | 354 ADVERTISED_Asym_Pause; 355 priv->phydev->advertising = priv->phydev->supported; 356 357 if (priv->phy_of_handle > 0) 358 priv->phydev->dev->of_offset = priv->phy_of_handle; 359 360 phy_config(priv->phydev); 361 362 return 0; 363 } 364 365 static int zynq_gem_init(struct udevice *dev) 366 { 367 u32 i, nwconfig; 368 unsigned long clk_rate = 0; 369 struct zynq_gem_priv *priv = dev_get_priv(dev); 370 struct zynq_gem_regs *regs = priv->iobase; 371 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 372 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 373 374 if (!priv->init) { 375 /* Disable all interrupts */ 376 writel(0xFFFFFFFF, ®s->idr); 377 378 /* Disable the receiver & transmitter */ 379 writel(0, ®s->nwctrl); 380 writel(0, ®s->txsr); 381 writel(0, ®s->rxsr); 382 writel(0, ®s->phymntnc); 383 384 /* Clear the Hash registers for the mac address 385 * pointed by AddressPtr 386 */ 387 writel(0x0, ®s->hashl); 388 /* Write bits [63:32] in TOP */ 389 writel(0x0, ®s->hashh); 390 391 /* Clear all counters */ 392 for (i = 0; i < STAT_SIZE; i++) 393 readl(®s->stat[i]); 394 395 /* Setup RxBD space */ 396 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 397 398 for (i = 0; i < RX_BUF; i++) { 399 priv->rx_bd[i].status = 0xF0000000; 400 priv->rx_bd[i].addr = 401 ((ulong)(priv->rxbuffers) + 402 (i * PKTSIZE_ALIGN)); 403 } 404 /* WRAP bit to last BD */ 405 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 406 /* Write RxBDs to IP */ 407 writel((ulong)priv->rx_bd, ®s->rxqbase); 408 409 /* Setup for DMA Configuration register */ 410 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 411 412 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 413 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 414 415 /* Disable the second priority queue */ 416 dummy_tx_bd->addr = 0; 417 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 418 ZYNQ_GEM_TXBUF_LAST_MASK| 419 ZYNQ_GEM_TXBUF_USED_MASK; 420 421 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 422 ZYNQ_GEM_RXBUF_NEW_MASK; 423 dummy_rx_bd->status = 0; 424 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + 425 sizeof(dummy_tx_bd)); 426 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + 427 sizeof(dummy_rx_bd)); 428 429 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 430 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 431 432 priv->init++; 433 } 434 435 phy_startup(priv->phydev); 436 437 if (!priv->phydev->link) { 438 printf("%s: No link.\n", priv->phydev->dev->name); 439 return -1; 440 } 441 442 nwconfig = ZYNQ_GEM_NWCFG_INIT; 443 444 if (priv->interface == PHY_INTERFACE_MODE_SGMII) { 445 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | 446 ZYNQ_GEM_NWCFG_PCS_SEL; 447 #ifdef CONFIG_ARM64 448 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, 449 ®s->pcscntrl); 450 #endif 451 } 452 453 switch (priv->phydev->speed) { 454 case SPEED_1000: 455 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, 456 ®s->nwcfg); 457 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 458 break; 459 case SPEED_100: 460 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, 461 ®s->nwcfg); 462 clk_rate = ZYNQ_GEM_FREQUENCY_100; 463 break; 464 case SPEED_10: 465 clk_rate = ZYNQ_GEM_FREQUENCY_10; 466 break; 467 } 468 469 /* Change the rclk and clk only not using EMIO interface */ 470 if (!priv->emio) 471 zynq_slcr_gem_clk_setup((ulong)priv->iobase != 472 ZYNQ_GEM_BASEADDR0, clk_rate); 473 474 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 475 ZYNQ_GEM_NWCTRL_TXEN_MASK); 476 477 return 0; 478 } 479 480 static int zynq_gem_send(struct udevice *dev, void *ptr, int len) 481 { 482 u32 addr, size; 483 struct zynq_gem_priv *priv = dev_get_priv(dev); 484 struct zynq_gem_regs *regs = priv->iobase; 485 struct emac_bd *current_bd = &priv->tx_bd[1]; 486 487 /* Setup Tx BD */ 488 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 489 490 priv->tx_bd->addr = (ulong)ptr; 491 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 492 ZYNQ_GEM_TXBUF_LAST_MASK; 493 /* Dummy descriptor to mark it as the last in descriptor chain */ 494 current_bd->addr = 0x0; 495 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 496 ZYNQ_GEM_TXBUF_LAST_MASK| 497 ZYNQ_GEM_TXBUF_USED_MASK; 498 499 /* setup BD */ 500 writel((ulong)priv->tx_bd, ®s->txqbase); 501 502 addr = (ulong) ptr; 503 addr &= ~(ARCH_DMA_MINALIGN - 1); 504 size = roundup(len, ARCH_DMA_MINALIGN); 505 flush_dcache_range(addr, addr + size); 506 507 addr = (ulong)priv->rxbuffers; 508 addr &= ~(ARCH_DMA_MINALIGN - 1); 509 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 510 flush_dcache_range(addr, addr + size); 511 barrier(); 512 513 /* Start transmit */ 514 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 515 516 /* Read TX BD status */ 517 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 518 printf("TX buffers exhausted in mid frame\n"); 519 520 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, 521 true, 20000, true); 522 } 523 524 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 525 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) 526 { 527 int frame_len; 528 u32 addr; 529 struct zynq_gem_priv *priv = dev_get_priv(dev); 530 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 531 532 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 533 return -1; 534 535 if (!(current_bd->status & 536 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 537 printf("GEM: SOF or EOF not set for last buffer received!\n"); 538 return -1; 539 } 540 541 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 542 if (!frame_len) { 543 printf("%s: Zero size packet?\n", __func__); 544 return -1; 545 } 546 547 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 548 addr &= ~(ARCH_DMA_MINALIGN - 1); 549 *packetp = (uchar *)(uintptr_t)addr; 550 551 return frame_len; 552 } 553 554 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) 555 { 556 struct zynq_gem_priv *priv = dev_get_priv(dev); 557 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 558 struct emac_bd *first_bd; 559 560 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { 561 priv->rx_first_buf = priv->rxbd_current; 562 } else { 563 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 564 current_bd->status = 0xF0000000; /* FIXME */ 565 } 566 567 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 568 first_bd = &priv->rx_bd[priv->rx_first_buf]; 569 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 570 first_bd->status = 0xF0000000; 571 } 572 573 if ((++priv->rxbd_current) >= RX_BUF) 574 priv->rxbd_current = 0; 575 576 return 0; 577 } 578 579 static void zynq_gem_halt(struct udevice *dev) 580 { 581 struct zynq_gem_priv *priv = dev_get_priv(dev); 582 struct zynq_gem_regs *regs = priv->iobase; 583 584 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 585 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 586 } 587 588 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 589 { 590 return -ENOSYS; 591 } 592 593 static int zynq_gem_read_rom_mac(struct udevice *dev) 594 { 595 int retval; 596 struct eth_pdata *pdata = dev_get_platdata(dev); 597 598 retval = zynq_board_read_rom_ethaddr(pdata->enetaddr); 599 if (retval == -ENOSYS) 600 retval = 0; 601 602 return retval; 603 } 604 605 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, 606 int devad, int reg) 607 { 608 struct zynq_gem_priv *priv = bus->priv; 609 int ret; 610 u16 val; 611 612 ret = phyread(priv, addr, reg, &val); 613 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); 614 return val; 615 } 616 617 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, 618 int reg, u16 value) 619 { 620 struct zynq_gem_priv *priv = bus->priv; 621 622 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); 623 return phywrite(priv, addr, reg, value); 624 } 625 626 static int zynq_gem_probe(struct udevice *dev) 627 { 628 void *bd_space; 629 struct zynq_gem_priv *priv = dev_get_priv(dev); 630 int ret; 631 632 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 633 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 634 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 635 636 /* Align bd_space to MMU_SECTION_SHIFT */ 637 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 638 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 639 BD_SPACE, DCACHE_OFF); 640 641 /* Initialize the bd spaces for tx and rx bd's */ 642 priv->tx_bd = (struct emac_bd *)bd_space; 643 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 644 645 priv->bus = mdio_alloc(); 646 priv->bus->read = zynq_gem_miiphy_read; 647 priv->bus->write = zynq_gem_miiphy_write; 648 priv->bus->priv = priv; 649 strcpy(priv->bus->name, "gem"); 650 651 ret = mdio_register(priv->bus); 652 if (ret) 653 return ret; 654 655 return zynq_phy_init(dev); 656 } 657 658 static int zynq_gem_remove(struct udevice *dev) 659 { 660 struct zynq_gem_priv *priv = dev_get_priv(dev); 661 662 free(priv->phydev); 663 mdio_unregister(priv->bus); 664 mdio_free(priv->bus); 665 666 return 0; 667 } 668 669 static const struct eth_ops zynq_gem_ops = { 670 .start = zynq_gem_init, 671 .send = zynq_gem_send, 672 .recv = zynq_gem_recv, 673 .free_pkt = zynq_gem_free_pkt, 674 .stop = zynq_gem_halt, 675 .write_hwaddr = zynq_gem_setup_mac, 676 .read_rom_hwaddr = zynq_gem_read_rom_mac, 677 }; 678 679 static int zynq_gem_ofdata_to_platdata(struct udevice *dev) 680 { 681 struct eth_pdata *pdata = dev_get_platdata(dev); 682 struct zynq_gem_priv *priv = dev_get_priv(dev); 683 const char *phy_mode; 684 685 pdata->iobase = (phys_addr_t)dev_get_addr(dev); 686 priv->iobase = (struct zynq_gem_regs *)pdata->iobase; 687 /* Hardcode for now */ 688 priv->emio = 0; 689 priv->phyaddr = -1; 690 691 priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, 692 dev->of_offset, "phy-handle"); 693 if (priv->phy_of_handle > 0) 694 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, 695 priv->phy_of_handle, "reg", -1); 696 697 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 698 if (phy_mode) 699 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 700 if (pdata->phy_interface == -1) { 701 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 702 return -EINVAL; 703 } 704 priv->interface = pdata->phy_interface; 705 706 priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio"); 707 708 printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, 709 priv->phyaddr, phy_string_for_interface(priv->interface)); 710 711 return 0; 712 } 713 714 static const struct udevice_id zynq_gem_ids[] = { 715 { .compatible = "cdns,zynqmp-gem" }, 716 { .compatible = "cdns,zynq-gem" }, 717 { .compatible = "cdns,gem" }, 718 { } 719 }; 720 721 U_BOOT_DRIVER(zynq_gem) = { 722 .name = "zynq_gem", 723 .id = UCLASS_ETH, 724 .of_match = zynq_gem_ids, 725 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, 726 .probe = zynq_gem_probe, 727 .remove = zynq_gem_remove, 728 .ops = &zynq_gem_ops, 729 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), 730 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 731 }; 732