1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <net.h> 30 #include <config.h> 31 #include <malloc.h> 32 #include <asm/io.h> 33 #include <phy.h> 34 #include <miiphy.h> 35 #include <watchdog.h> 36 #include <asm/arch/hardware.h> 37 #include <asm/arch/sys_proto.h> 38 39 #if !defined(CONFIG_PHYLIB) 40 # error XILINX_GEM_ETHERNET requires PHYLIB 41 #endif 42 43 /* Bit/mask specification */ 44 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 45 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 46 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 47 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 48 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 49 50 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 51 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 52 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 53 54 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 55 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 56 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 57 58 /* Wrap bit, last descriptor */ 59 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 60 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 61 62 #define ZYNQ_GEM_TXSR_HRESPNOK_MASK 0x00000100 /* Transmit hresp not OK */ 63 #define ZYNQ_GEM_TXSR_URUN_MASK 0x00000040 /* Transmit underrun */ 64 /* Transmit buffs exhausted mid frame */ 65 #define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x00000010 66 67 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 68 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 69 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 70 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 71 72 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 73 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 74 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 75 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 76 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ 77 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ 78 79 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \ 80 ZYNQ_GEM_NWCFG_FSREM | \ 81 ZYNQ_GEM_NWCFG_MDCCLKDIV) 82 83 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 84 85 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 86 /* Use full configured addressable space (8 Kb) */ 87 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 88 /* Use full configured addressable space (4 Kb) */ 89 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 90 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 91 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 92 93 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 94 ZYNQ_GEM_DMACR_RXSIZE | \ 95 ZYNQ_GEM_DMACR_TXSIZE | \ 96 ZYNQ_GEM_DMACR_RXBUF) 97 98 /* Use MII register 1 (MII status register) to detect PHY */ 99 #define PHY_DETECT_REG 1 100 101 /* Mask used to verify certain PHY features (or register contents) 102 * in the register above: 103 * 0x1000: 10Mbps full duplex support 104 * 0x0800: 10Mbps half duplex support 105 * 0x0008: Auto-negotiation support 106 */ 107 #define PHY_DETECT_MASK 0x1808 108 109 /* Device registers */ 110 struct zynq_gem_regs { 111 u32 nwctrl; /* Network Control reg */ 112 u32 nwcfg; /* Network Config reg */ 113 u32 nwsr; /* Network Status reg */ 114 u32 reserved1; 115 u32 dmacr; /* DMA Control reg */ 116 u32 txsr; /* TX Status reg */ 117 u32 rxqbase; /* RX Q Base address reg */ 118 u32 txqbase; /* TX Q Base address reg */ 119 u32 rxsr; /* RX Status reg */ 120 u32 reserved2[2]; 121 u32 idr; /* Interrupt Disable reg */ 122 u32 reserved3; 123 u32 phymntnc; /* Phy Maintaince reg */ 124 u32 reserved4[18]; 125 u32 hashl; /* Hash Low address reg */ 126 u32 hashh; /* Hash High address reg */ 127 #define LADDR_LOW 0 128 #define LADDR_HIGH 1 129 u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */ 130 u32 match[4]; /* Type ID1 Match reg */ 131 u32 reserved6[18]; 132 u32 stat[44]; /* Octects transmitted Low reg - stat start */ 133 }; 134 135 /* BD descriptors */ 136 struct emac_bd { 137 u32 addr; /* Next descriptor pointer */ 138 u32 status; 139 }; 140 141 #define RX_BUF 3 142 143 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 144 struct zynq_gem_priv { 145 struct emac_bd tx_bd; 146 struct emac_bd rx_bd[RX_BUF]; 147 char rxbuffers[RX_BUF * PKTSIZE_ALIGN]; 148 u32 rxbd_current; 149 u32 rx_first_buf; 150 int phyaddr; 151 u32 emio; 152 int init; 153 struct phy_device *phydev; 154 struct mii_dev *bus; 155 }; 156 157 static inline int mdio_wait(struct eth_device *dev) 158 { 159 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 160 u32 timeout = 200; 161 162 /* Wait till MDIO interface is ready to accept a new transaction. */ 163 while (--timeout) { 164 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 165 break; 166 WATCHDOG_RESET(); 167 } 168 169 if (!timeout) { 170 printf("%s: Timeout\n", __func__); 171 return 1; 172 } 173 174 return 0; 175 } 176 177 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, 178 u32 op, u16 *data) 179 { 180 u32 mgtcr; 181 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 182 183 if (mdio_wait(dev)) 184 return 1; 185 186 /* Construct mgtcr mask for the operation */ 187 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 188 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 189 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 190 191 /* Write mgtcr and wait for completion */ 192 writel(mgtcr, ®s->phymntnc); 193 194 if (mdio_wait(dev)) 195 return 1; 196 197 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 198 *data = readl(®s->phymntnc); 199 200 return 0; 201 } 202 203 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) 204 { 205 return phy_setup_op(dev, phy_addr, regnum, 206 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 207 } 208 209 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) 210 { 211 return phy_setup_op(dev, phy_addr, regnum, 212 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 213 } 214 215 static void phy_detection(struct eth_device *dev) 216 { 217 int i; 218 u16 phyreg; 219 struct zynq_gem_priv *priv = dev->priv; 220 221 if (priv->phyaddr != -1) { 222 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); 223 if ((phyreg != 0xFFFF) && 224 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 225 /* Found a valid PHY address */ 226 debug("Default phy address %d is valid\n", 227 priv->phyaddr); 228 return; 229 } else { 230 debug("PHY address is not setup correctly %d\n", 231 priv->phyaddr); 232 priv->phyaddr = -1; 233 } 234 } 235 236 debug("detecting phy address\n"); 237 if (priv->phyaddr == -1) { 238 /* detect the PHY address */ 239 for (i = 31; i >= 0; i--) { 240 phyread(dev, i, PHY_DETECT_REG, &phyreg); 241 if ((phyreg != 0xFFFF) && 242 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 243 /* Found a valid PHY address */ 244 priv->phyaddr = i; 245 debug("Found valid phy address, %d\n", i); 246 return; 247 } 248 } 249 } 250 printf("PHY is not detected\n"); 251 } 252 253 static int zynq_gem_setup_mac(struct eth_device *dev) 254 { 255 u32 i, macaddrlow, macaddrhigh; 256 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 257 258 /* Set the MAC bits [31:0] in BOT */ 259 macaddrlow = dev->enetaddr[0]; 260 macaddrlow |= dev->enetaddr[1] << 8; 261 macaddrlow |= dev->enetaddr[2] << 16; 262 macaddrlow |= dev->enetaddr[3] << 24; 263 264 /* Set MAC bits [47:32] in TOP */ 265 macaddrhigh = dev->enetaddr[4]; 266 macaddrhigh |= dev->enetaddr[5] << 8; 267 268 for (i = 0; i < 4; i++) { 269 writel(0, ®s->laddr[i][LADDR_LOW]); 270 writel(0, ®s->laddr[i][LADDR_HIGH]); 271 /* Do not use MATCHx register */ 272 writel(0, ®s->match[i]); 273 } 274 275 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 276 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 277 278 return 0; 279 } 280 281 static int zynq_gem_init(struct eth_device *dev, bd_t * bis) 282 { 283 u32 i, rclk, clk = 0; 284 struct phy_device *phydev; 285 const u32 stat_size = (sizeof(struct zynq_gem_regs) - 286 offsetof(struct zynq_gem_regs, stat)) / 4; 287 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 288 struct zynq_gem_priv *priv = dev->priv; 289 const u32 supported = SUPPORTED_10baseT_Half | 290 SUPPORTED_10baseT_Full | 291 SUPPORTED_100baseT_Half | 292 SUPPORTED_100baseT_Full | 293 SUPPORTED_1000baseT_Half | 294 SUPPORTED_1000baseT_Full; 295 296 if (!priv->init) { 297 /* Disable all interrupts */ 298 writel(0xFFFFFFFF, ®s->idr); 299 300 /* Disable the receiver & transmitter */ 301 writel(0, ®s->nwctrl); 302 writel(0, ®s->txsr); 303 writel(0, ®s->rxsr); 304 writel(0, ®s->phymntnc); 305 306 /* Clear the Hash registers for the mac address 307 * pointed by AddressPtr 308 */ 309 writel(0x0, ®s->hashl); 310 /* Write bits [63:32] in TOP */ 311 writel(0x0, ®s->hashh); 312 313 /* Clear all counters */ 314 for (i = 0; i <= stat_size; i++) 315 readl(®s->stat[i]); 316 317 /* Setup RxBD space */ 318 memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd)); 319 /* Create the RxBD ring */ 320 memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers)); 321 322 for (i = 0; i < RX_BUF; i++) { 323 priv->rx_bd[i].status = 0xF0000000; 324 priv->rx_bd[i].addr = 325 (u32)((char *)&(priv->rxbuffers) + 326 (i * PKTSIZE_ALIGN)); 327 } 328 /* WRAP bit to last BD */ 329 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 330 /* Write RxBDs to IP */ 331 writel((u32)&(priv->rx_bd), ®s->rxqbase); 332 333 /* Setup for DMA Configuration register */ 334 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 335 336 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 337 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 338 339 priv->init++; 340 } 341 342 phy_detection(dev); 343 344 /* interface - look at tsec */ 345 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); 346 347 phydev->supported = supported | ADVERTISED_Pause | 348 ADVERTISED_Asym_Pause; 349 phydev->advertising = phydev->supported; 350 priv->phydev = phydev; 351 phy_config(phydev); 352 phy_startup(phydev); 353 354 switch (phydev->speed) { 355 case SPEED_1000: 356 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 357 ®s->nwcfg); 358 rclk = (0 << 4) | (1 << 0); 359 clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0); 360 break; 361 case SPEED_100: 362 clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, 363 ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); 364 rclk = 1 << 0; 365 clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); 366 break; 367 case SPEED_10: 368 rclk = 1 << 0; 369 /* FIXME untested */ 370 clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); 371 break; 372 } 373 374 /* Change the rclk and clk only not using EMIO interface */ 375 if (!priv->emio) 376 zynq_slcr_gem_clk_setup(dev->iobase != 377 ZYNQ_GEM_BASEADDR0, rclk, clk); 378 379 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 380 ZYNQ_GEM_NWCTRL_TXEN_MASK); 381 382 return 0; 383 } 384 385 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) 386 { 387 u32 status; 388 struct zynq_gem_priv *priv = dev->priv; 389 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 390 const u32 mask = ZYNQ_GEM_TXSR_HRESPNOK_MASK | \ 391 ZYNQ_GEM_TXSR_URUN_MASK | ZYNQ_GEM_TXSR_BUFEXH_MASK; 392 393 /* setup BD */ 394 writel((u32)&(priv->tx_bd), ®s->txqbase); 395 396 /* Setup Tx BD */ 397 memset((void *)&(priv->tx_bd), 0, sizeof(struct emac_bd)); 398 399 priv->tx_bd.addr = (u32)ptr; 400 priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK; 401 402 /* Start transmit */ 403 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 404 405 /* Read the stat register to know if the packet has been transmitted */ 406 status = readl(®s->txsr); 407 if (status & mask) 408 printf("Something has gone wrong here!? Status is 0x%x.\n", 409 status); 410 411 /* Clear Tx status register before leaving . */ 412 writel(status, ®s->txsr); 413 return 0; 414 } 415 416 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 417 static int zynq_gem_recv(struct eth_device *dev) 418 { 419 int frame_len; 420 struct zynq_gem_priv *priv = dev->priv; 421 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 422 struct emac_bd *first_bd; 423 424 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 425 return 0; 426 427 if (!(current_bd->status & 428 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 429 printf("GEM: SOF or EOF not set for last buffer received!\n"); 430 return 0; 431 } 432 433 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 434 if (frame_len) { 435 NetReceive((u8 *) (current_bd->addr & 436 ZYNQ_GEM_RXBUF_ADD_MASK), frame_len); 437 438 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 439 priv->rx_first_buf = priv->rxbd_current; 440 else { 441 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 442 current_bd->status = 0xF0000000; /* FIXME */ 443 } 444 445 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 446 first_bd = &priv->rx_bd[priv->rx_first_buf]; 447 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 448 first_bd->status = 0xF0000000; 449 } 450 451 if ((++priv->rxbd_current) >= RX_BUF) 452 priv->rxbd_current = 0; 453 } 454 455 return frame_len; 456 } 457 458 static void zynq_gem_halt(struct eth_device *dev) 459 { 460 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 461 462 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 463 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 464 } 465 466 static int zynq_gem_miiphyread(const char *devname, uchar addr, 467 uchar reg, ushort *val) 468 { 469 struct eth_device *dev = eth_get_dev(); 470 int ret; 471 472 ret = phyread(dev, addr, reg, val); 473 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); 474 return ret; 475 } 476 477 static int zynq_gem_miiphy_write(const char *devname, uchar addr, 478 uchar reg, ushort val) 479 { 480 struct eth_device *dev = eth_get_dev(); 481 482 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); 483 return phywrite(dev, addr, reg, val); 484 } 485 486 int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio) 487 { 488 struct eth_device *dev; 489 struct zynq_gem_priv *priv; 490 491 dev = calloc(1, sizeof(*dev)); 492 if (dev == NULL) 493 return -1; 494 495 dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); 496 if (dev->priv == NULL) { 497 free(dev); 498 return -1; 499 } 500 priv = dev->priv; 501 502 priv->phyaddr = phy_addr; 503 priv->emio = emio; 504 505 sprintf(dev->name, "Gem.%x", base_addr); 506 507 dev->iobase = base_addr; 508 509 dev->init = zynq_gem_init; 510 dev->halt = zynq_gem_halt; 511 dev->send = zynq_gem_send; 512 dev->recv = zynq_gem_recv; 513 dev->write_hwaddr = zynq_gem_setup_mac; 514 515 eth_register(dev); 516 517 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); 518 priv->bus = miiphy_get_dev_by_name(dev->name); 519 520 return 1; 521 } 522