1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <clk.h> 13 #include <common.h> 14 #include <dm.h> 15 #include <net.h> 16 #include <netdev.h> 17 #include <config.h> 18 #include <console.h> 19 #include <malloc.h> 20 #include <asm/io.h> 21 #include <phy.h> 22 #include <miiphy.h> 23 #include <wait_bit.h> 24 #include <watchdog.h> 25 #include <asm/system.h> 26 #include <asm/arch/hardware.h> 27 #include <asm/arch/sys_proto.h> 28 #include <linux/errno.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 /* Bit/mask specification */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 38 39 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 40 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 41 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 42 43 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 44 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 45 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 46 47 /* Wrap bit, last descriptor */ 48 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 49 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 50 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 51 52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 56 57 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ 58 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ 59 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ 60 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ 61 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ 62 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ 63 #ifdef CONFIG_ARM64 64 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ 65 #else 66 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ 67 #endif 68 69 #ifdef CONFIG_ARM64 70 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 71 #else 72 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 73 #endif 74 75 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 76 ZYNQ_GEM_NWCFG_FDEN | \ 77 ZYNQ_GEM_NWCFG_FSREM | \ 78 ZYNQ_GEM_NWCFG_MDCCLKDIV) 79 80 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 81 82 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 83 /* Use full configured addressable space (8 Kb) */ 84 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 85 /* Use full configured addressable space (4 Kb) */ 86 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 87 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 88 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 89 90 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 91 ZYNQ_GEM_DMACR_RXSIZE | \ 92 ZYNQ_GEM_DMACR_TXSIZE | \ 93 ZYNQ_GEM_DMACR_RXBUF) 94 95 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 96 97 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 98 99 /* Use MII register 1 (MII status register) to detect PHY */ 100 #define PHY_DETECT_REG 1 101 102 /* Mask used to verify certain PHY features (or register contents) 103 * in the register above: 104 * 0x1000: 10Mbps full duplex support 105 * 0x0800: 10Mbps half duplex support 106 * 0x0008: Auto-negotiation support 107 */ 108 #define PHY_DETECT_MASK 0x1808 109 110 /* TX BD status masks */ 111 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 112 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 113 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 114 115 /* Clock frequencies for different speeds */ 116 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 117 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 118 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 119 120 /* Device registers */ 121 struct zynq_gem_regs { 122 u32 nwctrl; /* 0x0 - Network Control reg */ 123 u32 nwcfg; /* 0x4 - Network Config reg */ 124 u32 nwsr; /* 0x8 - Network Status reg */ 125 u32 reserved1; 126 u32 dmacr; /* 0x10 - DMA Control reg */ 127 u32 txsr; /* 0x14 - TX Status reg */ 128 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 129 u32 txqbase; /* 0x1c - TX Q Base address reg */ 130 u32 rxsr; /* 0x20 - RX Status reg */ 131 u32 reserved2[2]; 132 u32 idr; /* 0x2c - Interrupt Disable reg */ 133 u32 reserved3; 134 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 135 u32 reserved4[18]; 136 u32 hashl; /* 0x80 - Hash Low address reg */ 137 u32 hashh; /* 0x84 - Hash High address reg */ 138 #define LADDR_LOW 0 139 #define LADDR_HIGH 1 140 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 141 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 142 u32 reserved6[18]; 143 #define STAT_SIZE 44 144 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 145 u32 reserved9[20]; 146 u32 pcscntrl; 147 u32 reserved7[143]; 148 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 149 u32 reserved8[15]; 150 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 151 }; 152 153 /* BD descriptors */ 154 struct emac_bd { 155 u32 addr; /* Next descriptor pointer */ 156 u32 status; 157 }; 158 159 #define RX_BUF 32 160 /* Page table entries are set to 1MB, or multiples of 1MB 161 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 162 */ 163 #define BD_SPACE 0x100000 164 /* BD separation space */ 165 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 166 167 /* Setup the first free TX descriptor */ 168 #define TX_FREE_DESC 2 169 170 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 171 struct zynq_gem_priv { 172 struct emac_bd *tx_bd; 173 struct emac_bd *rx_bd; 174 char *rxbuffers; 175 u32 rxbd_current; 176 u32 rx_first_buf; 177 int phyaddr; 178 int init; 179 struct zynq_gem_regs *iobase; 180 phy_interface_t interface; 181 struct phy_device *phydev; 182 int phy_of_handle; 183 struct mii_dev *bus; 184 struct clk clk; 185 bool int_pcs; 186 }; 187 188 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, 189 u32 op, u16 *data) 190 { 191 u32 mgtcr; 192 struct zynq_gem_regs *regs = priv->iobase; 193 int err; 194 195 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, 196 true, 20000, false); 197 if (err) 198 return err; 199 200 /* Construct mgtcr mask for the operation */ 201 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 202 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 203 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 204 205 /* Write mgtcr and wait for completion */ 206 writel(mgtcr, ®s->phymntnc); 207 208 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, 209 true, 20000, false); 210 if (err) 211 return err; 212 213 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 214 *data = readl(®s->phymntnc); 215 216 return 0; 217 } 218 219 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, 220 u32 regnum, u16 *val) 221 { 222 u32 ret; 223 224 ret = phy_setup_op(priv, phy_addr, regnum, 225 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 226 227 if (!ret) 228 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 229 phy_addr, regnum, *val); 230 231 return ret; 232 } 233 234 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, 235 u32 regnum, u16 data) 236 { 237 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 238 regnum, data); 239 240 return phy_setup_op(priv, phy_addr, regnum, 241 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 242 } 243 244 static int phy_detection(struct udevice *dev) 245 { 246 int i; 247 u16 phyreg; 248 struct zynq_gem_priv *priv = dev->priv; 249 250 if (priv->phyaddr != -1) { 251 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); 252 if ((phyreg != 0xFFFF) && 253 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 254 /* Found a valid PHY address */ 255 debug("Default phy address %d is valid\n", 256 priv->phyaddr); 257 return 0; 258 } else { 259 debug("PHY address is not setup correctly %d\n", 260 priv->phyaddr); 261 priv->phyaddr = -1; 262 } 263 } 264 265 debug("detecting phy address\n"); 266 if (priv->phyaddr == -1) { 267 /* detect the PHY address */ 268 for (i = 31; i >= 0; i--) { 269 phyread(priv, i, PHY_DETECT_REG, &phyreg); 270 if ((phyreg != 0xFFFF) && 271 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 272 /* Found a valid PHY address */ 273 priv->phyaddr = i; 274 debug("Found valid phy address, %d\n", i); 275 return 0; 276 } 277 } 278 } 279 printf("PHY is not detected\n"); 280 return -1; 281 } 282 283 static int zynq_gem_setup_mac(struct udevice *dev) 284 { 285 u32 i, macaddrlow, macaddrhigh; 286 struct eth_pdata *pdata = dev_get_platdata(dev); 287 struct zynq_gem_priv *priv = dev_get_priv(dev); 288 struct zynq_gem_regs *regs = priv->iobase; 289 290 /* Set the MAC bits [31:0] in BOT */ 291 macaddrlow = pdata->enetaddr[0]; 292 macaddrlow |= pdata->enetaddr[1] << 8; 293 macaddrlow |= pdata->enetaddr[2] << 16; 294 macaddrlow |= pdata->enetaddr[3] << 24; 295 296 /* Set MAC bits [47:32] in TOP */ 297 macaddrhigh = pdata->enetaddr[4]; 298 macaddrhigh |= pdata->enetaddr[5] << 8; 299 300 for (i = 0; i < 4; i++) { 301 writel(0, ®s->laddr[i][LADDR_LOW]); 302 writel(0, ®s->laddr[i][LADDR_HIGH]); 303 /* Do not use MATCHx register */ 304 writel(0, ®s->match[i]); 305 } 306 307 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 308 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 309 310 return 0; 311 } 312 313 static int zynq_phy_init(struct udevice *dev) 314 { 315 int ret; 316 struct zynq_gem_priv *priv = dev_get_priv(dev); 317 struct zynq_gem_regs *regs = priv->iobase; 318 const u32 supported = SUPPORTED_10baseT_Half | 319 SUPPORTED_10baseT_Full | 320 SUPPORTED_100baseT_Half | 321 SUPPORTED_100baseT_Full | 322 SUPPORTED_1000baseT_Half | 323 SUPPORTED_1000baseT_Full; 324 325 /* Enable only MDIO bus */ 326 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); 327 328 if ((priv->interface != PHY_INTERFACE_MODE_SGMII) && 329 (priv->interface != PHY_INTERFACE_MODE_GMII)) { 330 ret = phy_detection(dev); 331 if (ret) { 332 printf("GEM PHY init failed\n"); 333 return ret; 334 } 335 } 336 337 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, 338 priv->interface); 339 if (!priv->phydev) 340 return -ENODEV; 341 342 priv->phydev->supported &= supported | ADVERTISED_Pause | 343 ADVERTISED_Asym_Pause; 344 priv->phydev->advertising = priv->phydev->supported; 345 346 if (priv->phy_of_handle > 0) 347 dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle); 348 349 return phy_config(priv->phydev); 350 } 351 352 static int zynq_gem_init(struct udevice *dev) 353 { 354 u32 i, nwconfig; 355 int ret; 356 unsigned long clk_rate = 0; 357 struct zynq_gem_priv *priv = dev_get_priv(dev); 358 struct zynq_gem_regs *regs = priv->iobase; 359 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 360 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 361 362 if (!priv->init) { 363 /* Disable all interrupts */ 364 writel(0xFFFFFFFF, ®s->idr); 365 366 /* Disable the receiver & transmitter */ 367 writel(0, ®s->nwctrl); 368 writel(0, ®s->txsr); 369 writel(0, ®s->rxsr); 370 writel(0, ®s->phymntnc); 371 372 /* Clear the Hash registers for the mac address 373 * pointed by AddressPtr 374 */ 375 writel(0x0, ®s->hashl); 376 /* Write bits [63:32] in TOP */ 377 writel(0x0, ®s->hashh); 378 379 /* Clear all counters */ 380 for (i = 0; i < STAT_SIZE; i++) 381 readl(®s->stat[i]); 382 383 /* Setup RxBD space */ 384 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 385 386 for (i = 0; i < RX_BUF; i++) { 387 priv->rx_bd[i].status = 0xF0000000; 388 priv->rx_bd[i].addr = 389 ((ulong)(priv->rxbuffers) + 390 (i * PKTSIZE_ALIGN)); 391 } 392 /* WRAP bit to last BD */ 393 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 394 /* Write RxBDs to IP */ 395 writel((ulong)priv->rx_bd, ®s->rxqbase); 396 397 /* Setup for DMA Configuration register */ 398 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 399 400 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 401 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 402 403 /* Disable the second priority queue */ 404 dummy_tx_bd->addr = 0; 405 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 406 ZYNQ_GEM_TXBUF_LAST_MASK| 407 ZYNQ_GEM_TXBUF_USED_MASK; 408 409 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 410 ZYNQ_GEM_RXBUF_NEW_MASK; 411 dummy_rx_bd->status = 0; 412 413 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 414 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 415 416 priv->init++; 417 } 418 419 ret = phy_startup(priv->phydev); 420 if (ret) 421 return ret; 422 423 if (!priv->phydev->link) { 424 printf("%s: No link.\n", priv->phydev->dev->name); 425 return -1; 426 } 427 428 nwconfig = ZYNQ_GEM_NWCFG_INIT; 429 430 /* 431 * Set SGMII enable PCS selection only if internal PCS/PMA 432 * core is used and interface is SGMII. 433 */ 434 if (priv->interface == PHY_INTERFACE_MODE_SGMII && 435 priv->int_pcs) { 436 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | 437 ZYNQ_GEM_NWCFG_PCS_SEL; 438 #ifdef CONFIG_ARM64 439 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, 440 ®s->pcscntrl); 441 #endif 442 } 443 444 switch (priv->phydev->speed) { 445 case SPEED_1000: 446 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, 447 ®s->nwcfg); 448 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 449 break; 450 case SPEED_100: 451 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, 452 ®s->nwcfg); 453 clk_rate = ZYNQ_GEM_FREQUENCY_100; 454 break; 455 case SPEED_10: 456 clk_rate = ZYNQ_GEM_FREQUENCY_10; 457 break; 458 } 459 460 ret = clk_set_rate(&priv->clk, clk_rate); 461 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { 462 dev_err(dev, "failed to set tx clock rate\n"); 463 return ret; 464 } 465 466 ret = clk_enable(&priv->clk); 467 if (ret && ret != -ENOSYS) { 468 dev_err(dev, "failed to enable tx clock\n"); 469 return ret; 470 } 471 472 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 473 ZYNQ_GEM_NWCTRL_TXEN_MASK); 474 475 return 0; 476 } 477 478 static int zynq_gem_send(struct udevice *dev, void *ptr, int len) 479 { 480 u32 addr, size; 481 struct zynq_gem_priv *priv = dev_get_priv(dev); 482 struct zynq_gem_regs *regs = priv->iobase; 483 struct emac_bd *current_bd = &priv->tx_bd[1]; 484 485 /* Setup Tx BD */ 486 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 487 488 priv->tx_bd->addr = (ulong)ptr; 489 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 490 ZYNQ_GEM_TXBUF_LAST_MASK; 491 /* Dummy descriptor to mark it as the last in descriptor chain */ 492 current_bd->addr = 0x0; 493 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 494 ZYNQ_GEM_TXBUF_LAST_MASK| 495 ZYNQ_GEM_TXBUF_USED_MASK; 496 497 /* setup BD */ 498 writel((ulong)priv->tx_bd, ®s->txqbase); 499 500 addr = (ulong) ptr; 501 addr &= ~(ARCH_DMA_MINALIGN - 1); 502 size = roundup(len, ARCH_DMA_MINALIGN); 503 flush_dcache_range(addr, addr + size); 504 505 addr = (ulong)priv->rxbuffers; 506 addr &= ~(ARCH_DMA_MINALIGN - 1); 507 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 508 flush_dcache_range(addr, addr + size); 509 barrier(); 510 511 /* Start transmit */ 512 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 513 514 /* Read TX BD status */ 515 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 516 printf("TX buffers exhausted in mid frame\n"); 517 518 return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, 519 true, 20000, true); 520 } 521 522 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 523 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) 524 { 525 int frame_len; 526 u32 addr; 527 struct zynq_gem_priv *priv = dev_get_priv(dev); 528 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 529 530 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 531 return -1; 532 533 if (!(current_bd->status & 534 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 535 printf("GEM: SOF or EOF not set for last buffer received!\n"); 536 return -1; 537 } 538 539 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 540 if (!frame_len) { 541 printf("%s: Zero size packet?\n", __func__); 542 return -1; 543 } 544 545 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 546 addr &= ~(ARCH_DMA_MINALIGN - 1); 547 *packetp = (uchar *)(uintptr_t)addr; 548 549 return frame_len; 550 } 551 552 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) 553 { 554 struct zynq_gem_priv *priv = dev_get_priv(dev); 555 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 556 struct emac_bd *first_bd; 557 558 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { 559 priv->rx_first_buf = priv->rxbd_current; 560 } else { 561 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 562 current_bd->status = 0xF0000000; /* FIXME */ 563 } 564 565 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 566 first_bd = &priv->rx_bd[priv->rx_first_buf]; 567 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 568 first_bd->status = 0xF0000000; 569 } 570 571 if ((++priv->rxbd_current) >= RX_BUF) 572 priv->rxbd_current = 0; 573 574 return 0; 575 } 576 577 static void zynq_gem_halt(struct udevice *dev) 578 { 579 struct zynq_gem_priv *priv = dev_get_priv(dev); 580 struct zynq_gem_regs *regs = priv->iobase; 581 582 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 583 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 584 } 585 586 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 587 { 588 return -ENOSYS; 589 } 590 591 static int zynq_gem_read_rom_mac(struct udevice *dev) 592 { 593 struct eth_pdata *pdata = dev_get_platdata(dev); 594 595 if (!pdata) 596 return -ENOSYS; 597 598 return zynq_board_read_rom_ethaddr(pdata->enetaddr); 599 } 600 601 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, 602 int devad, int reg) 603 { 604 struct zynq_gem_priv *priv = bus->priv; 605 int ret; 606 u16 val; 607 608 ret = phyread(priv, addr, reg, &val); 609 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); 610 return val; 611 } 612 613 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, 614 int reg, u16 value) 615 { 616 struct zynq_gem_priv *priv = bus->priv; 617 618 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); 619 return phywrite(priv, addr, reg, value); 620 } 621 622 static int zynq_gem_probe(struct udevice *dev) 623 { 624 void *bd_space; 625 struct zynq_gem_priv *priv = dev_get_priv(dev); 626 int ret; 627 628 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 629 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 630 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 631 632 /* Align bd_space to MMU_SECTION_SHIFT */ 633 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 634 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 635 BD_SPACE, DCACHE_OFF); 636 637 /* Initialize the bd spaces for tx and rx bd's */ 638 priv->tx_bd = (struct emac_bd *)bd_space; 639 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 640 641 ret = clk_get_by_name(dev, "tx_clk", &priv->clk); 642 if (ret < 0) { 643 dev_err(dev, "failed to get clock\n"); 644 return -EINVAL; 645 } 646 647 priv->bus = mdio_alloc(); 648 priv->bus->read = zynq_gem_miiphy_read; 649 priv->bus->write = zynq_gem_miiphy_write; 650 priv->bus->priv = priv; 651 652 ret = mdio_register_seq(priv->bus, dev->seq); 653 if (ret) 654 return ret; 655 656 return zynq_phy_init(dev); 657 } 658 659 static int zynq_gem_remove(struct udevice *dev) 660 { 661 struct zynq_gem_priv *priv = dev_get_priv(dev); 662 663 free(priv->phydev); 664 mdio_unregister(priv->bus); 665 mdio_free(priv->bus); 666 667 return 0; 668 } 669 670 static const struct eth_ops zynq_gem_ops = { 671 .start = zynq_gem_init, 672 .send = zynq_gem_send, 673 .recv = zynq_gem_recv, 674 .free_pkt = zynq_gem_free_pkt, 675 .stop = zynq_gem_halt, 676 .write_hwaddr = zynq_gem_setup_mac, 677 .read_rom_hwaddr = zynq_gem_read_rom_mac, 678 }; 679 680 static int zynq_gem_ofdata_to_platdata(struct udevice *dev) 681 { 682 struct eth_pdata *pdata = dev_get_platdata(dev); 683 struct zynq_gem_priv *priv = dev_get_priv(dev); 684 int node = dev_of_offset(dev); 685 const char *phy_mode; 686 687 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); 688 priv->iobase = (struct zynq_gem_regs *)pdata->iobase; 689 /* Hardcode for now */ 690 priv->phyaddr = -1; 691 692 priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node, 693 "phy-handle"); 694 if (priv->phy_of_handle > 0) 695 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, 696 priv->phy_of_handle, "reg", -1); 697 698 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); 699 if (phy_mode) 700 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 701 if (pdata->phy_interface == -1) { 702 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 703 return -EINVAL; 704 } 705 priv->interface = pdata->phy_interface; 706 707 priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node, 708 "is-internal-pcspma"); 709 710 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, 711 priv->phyaddr, phy_string_for_interface(priv->interface)); 712 713 return 0; 714 } 715 716 static const struct udevice_id zynq_gem_ids[] = { 717 { .compatible = "cdns,zynqmp-gem" }, 718 { .compatible = "cdns,zynq-gem" }, 719 { .compatible = "cdns,gem" }, 720 { } 721 }; 722 723 U_BOOT_DRIVER(zynq_gem) = { 724 .name = "zynq_gem", 725 .id = UCLASS_ETH, 726 .of_match = zynq_gem_ids, 727 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, 728 .probe = zynq_gem_probe, 729 .remove = zynq_gem_remove, 730 .ops = &zynq_gem_ops, 731 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), 732 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 733 }; 734