1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <clk.h> 13 #include <common.h> 14 #include <dm.h> 15 #include <net.h> 16 #include <netdev.h> 17 #include <config.h> 18 #include <console.h> 19 #include <malloc.h> 20 #include <asm/io.h> 21 #include <phy.h> 22 #include <miiphy.h> 23 #include <wait_bit.h> 24 #include <watchdog.h> 25 #include <asm/system.h> 26 #include <asm/arch/hardware.h> 27 #include <asm/arch/sys_proto.h> 28 #include <linux/errno.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 /* Bit/mask specification */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 38 39 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 40 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 41 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 42 43 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 44 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 45 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 46 47 /* Wrap bit, last descriptor */ 48 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 49 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 50 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 51 52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 56 57 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ 58 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ 59 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ 60 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ 61 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ 62 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ 63 #ifdef CONFIG_ARM64 64 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ 65 #else 66 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ 67 #endif 68 69 #ifdef CONFIG_ARM64 70 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 71 #else 72 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 73 #endif 74 75 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 76 ZYNQ_GEM_NWCFG_FDEN | \ 77 ZYNQ_GEM_NWCFG_FSREM | \ 78 ZYNQ_GEM_NWCFG_MDCCLKDIV) 79 80 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 81 82 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 83 /* Use full configured addressable space (8 Kb) */ 84 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 85 /* Use full configured addressable space (4 Kb) */ 86 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 87 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 88 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 89 90 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 91 ZYNQ_GEM_DMACR_RXSIZE | \ 92 ZYNQ_GEM_DMACR_TXSIZE | \ 93 ZYNQ_GEM_DMACR_RXBUF) 94 95 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 96 97 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 98 99 /* Use MII register 1 (MII status register) to detect PHY */ 100 #define PHY_DETECT_REG 1 101 102 /* Mask used to verify certain PHY features (or register contents) 103 * in the register above: 104 * 0x1000: 10Mbps full duplex support 105 * 0x0800: 10Mbps half duplex support 106 * 0x0008: Auto-negotiation support 107 */ 108 #define PHY_DETECT_MASK 0x1808 109 110 /* TX BD status masks */ 111 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 112 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 113 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 114 115 /* Clock frequencies for different speeds */ 116 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 117 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 118 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 119 120 /* Device registers */ 121 struct zynq_gem_regs { 122 u32 nwctrl; /* 0x0 - Network Control reg */ 123 u32 nwcfg; /* 0x4 - Network Config reg */ 124 u32 nwsr; /* 0x8 - Network Status reg */ 125 u32 reserved1; 126 u32 dmacr; /* 0x10 - DMA Control reg */ 127 u32 txsr; /* 0x14 - TX Status reg */ 128 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 129 u32 txqbase; /* 0x1c - TX Q Base address reg */ 130 u32 rxsr; /* 0x20 - RX Status reg */ 131 u32 reserved2[2]; 132 u32 idr; /* 0x2c - Interrupt Disable reg */ 133 u32 reserved3; 134 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 135 u32 reserved4[18]; 136 u32 hashl; /* 0x80 - Hash Low address reg */ 137 u32 hashh; /* 0x84 - Hash High address reg */ 138 #define LADDR_LOW 0 139 #define LADDR_HIGH 1 140 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 141 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 142 u32 reserved6[18]; 143 #define STAT_SIZE 44 144 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 145 u32 reserved9[20]; 146 u32 pcscntrl; 147 u32 reserved7[143]; 148 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 149 u32 reserved8[15]; 150 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 151 }; 152 153 /* BD descriptors */ 154 struct emac_bd { 155 u32 addr; /* Next descriptor pointer */ 156 u32 status; 157 }; 158 159 #define RX_BUF 32 160 /* Page table entries are set to 1MB, or multiples of 1MB 161 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 162 */ 163 #define BD_SPACE 0x100000 164 /* BD separation space */ 165 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 166 167 /* Setup the first free TX descriptor */ 168 #define TX_FREE_DESC 2 169 170 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 171 struct zynq_gem_priv { 172 struct emac_bd *tx_bd; 173 struct emac_bd *rx_bd; 174 char *rxbuffers; 175 u32 rxbd_current; 176 u32 rx_first_buf; 177 int phyaddr; 178 int init; 179 struct zynq_gem_regs *iobase; 180 phy_interface_t interface; 181 struct phy_device *phydev; 182 int phy_of_handle; 183 struct mii_dev *bus; 184 struct clk clk; 185 }; 186 187 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, 188 u32 op, u16 *data) 189 { 190 u32 mgtcr; 191 struct zynq_gem_regs *regs = priv->iobase; 192 int err; 193 194 err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, 195 true, 20000, false); 196 if (err) 197 return err; 198 199 /* Construct mgtcr mask for the operation */ 200 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 201 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 202 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 203 204 /* Write mgtcr and wait for completion */ 205 writel(mgtcr, ®s->phymntnc); 206 207 err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, 208 true, 20000, false); 209 if (err) 210 return err; 211 212 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 213 *data = readl(®s->phymntnc); 214 215 return 0; 216 } 217 218 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, 219 u32 regnum, u16 *val) 220 { 221 u32 ret; 222 223 ret = phy_setup_op(priv, phy_addr, regnum, 224 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 225 226 if (!ret) 227 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 228 phy_addr, regnum, *val); 229 230 return ret; 231 } 232 233 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, 234 u32 regnum, u16 data) 235 { 236 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 237 regnum, data); 238 239 return phy_setup_op(priv, phy_addr, regnum, 240 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 241 } 242 243 static int phy_detection(struct udevice *dev) 244 { 245 int i; 246 u16 phyreg; 247 struct zynq_gem_priv *priv = dev->priv; 248 249 if (priv->phyaddr != -1) { 250 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); 251 if ((phyreg != 0xFFFF) && 252 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 253 /* Found a valid PHY address */ 254 debug("Default phy address %d is valid\n", 255 priv->phyaddr); 256 return 0; 257 } else { 258 debug("PHY address is not setup correctly %d\n", 259 priv->phyaddr); 260 priv->phyaddr = -1; 261 } 262 } 263 264 debug("detecting phy address\n"); 265 if (priv->phyaddr == -1) { 266 /* detect the PHY address */ 267 for (i = 31; i >= 0; i--) { 268 phyread(priv, i, PHY_DETECT_REG, &phyreg); 269 if ((phyreg != 0xFFFF) && 270 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 271 /* Found a valid PHY address */ 272 priv->phyaddr = i; 273 debug("Found valid phy address, %d\n", i); 274 return 0; 275 } 276 } 277 } 278 printf("PHY is not detected\n"); 279 return -1; 280 } 281 282 static int zynq_gem_setup_mac(struct udevice *dev) 283 { 284 u32 i, macaddrlow, macaddrhigh; 285 struct eth_pdata *pdata = dev_get_platdata(dev); 286 struct zynq_gem_priv *priv = dev_get_priv(dev); 287 struct zynq_gem_regs *regs = priv->iobase; 288 289 /* Set the MAC bits [31:0] in BOT */ 290 macaddrlow = pdata->enetaddr[0]; 291 macaddrlow |= pdata->enetaddr[1] << 8; 292 macaddrlow |= pdata->enetaddr[2] << 16; 293 macaddrlow |= pdata->enetaddr[3] << 24; 294 295 /* Set MAC bits [47:32] in TOP */ 296 macaddrhigh = pdata->enetaddr[4]; 297 macaddrhigh |= pdata->enetaddr[5] << 8; 298 299 for (i = 0; i < 4; i++) { 300 writel(0, ®s->laddr[i][LADDR_LOW]); 301 writel(0, ®s->laddr[i][LADDR_HIGH]); 302 /* Do not use MATCHx register */ 303 writel(0, ®s->match[i]); 304 } 305 306 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 307 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 308 309 return 0; 310 } 311 312 static int zynq_phy_init(struct udevice *dev) 313 { 314 int ret; 315 struct zynq_gem_priv *priv = dev_get_priv(dev); 316 struct zynq_gem_regs *regs = priv->iobase; 317 const u32 supported = SUPPORTED_10baseT_Half | 318 SUPPORTED_10baseT_Full | 319 SUPPORTED_100baseT_Half | 320 SUPPORTED_100baseT_Full | 321 SUPPORTED_1000baseT_Half | 322 SUPPORTED_1000baseT_Full; 323 324 /* Enable only MDIO bus */ 325 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); 326 327 if (priv->interface != PHY_INTERFACE_MODE_SGMII) { 328 ret = phy_detection(dev); 329 if (ret) { 330 printf("GEM PHY init failed\n"); 331 return ret; 332 } 333 } 334 335 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, 336 priv->interface); 337 if (!priv->phydev) 338 return -ENODEV; 339 340 priv->phydev->supported &= supported | ADVERTISED_Pause | 341 ADVERTISED_Asym_Pause; 342 priv->phydev->advertising = priv->phydev->supported; 343 344 if (priv->phy_of_handle > 0) 345 dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle); 346 347 return phy_config(priv->phydev); 348 } 349 350 static int zynq_gem_init(struct udevice *dev) 351 { 352 u32 i, nwconfig; 353 int ret; 354 unsigned long clk_rate = 0; 355 struct zynq_gem_priv *priv = dev_get_priv(dev); 356 struct zynq_gem_regs *regs = priv->iobase; 357 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 358 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 359 360 if (!priv->init) { 361 /* Disable all interrupts */ 362 writel(0xFFFFFFFF, ®s->idr); 363 364 /* Disable the receiver & transmitter */ 365 writel(0, ®s->nwctrl); 366 writel(0, ®s->txsr); 367 writel(0, ®s->rxsr); 368 writel(0, ®s->phymntnc); 369 370 /* Clear the Hash registers for the mac address 371 * pointed by AddressPtr 372 */ 373 writel(0x0, ®s->hashl); 374 /* Write bits [63:32] in TOP */ 375 writel(0x0, ®s->hashh); 376 377 /* Clear all counters */ 378 for (i = 0; i < STAT_SIZE; i++) 379 readl(®s->stat[i]); 380 381 /* Setup RxBD space */ 382 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 383 384 for (i = 0; i < RX_BUF; i++) { 385 priv->rx_bd[i].status = 0xF0000000; 386 priv->rx_bd[i].addr = 387 ((ulong)(priv->rxbuffers) + 388 (i * PKTSIZE_ALIGN)); 389 } 390 /* WRAP bit to last BD */ 391 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 392 /* Write RxBDs to IP */ 393 writel((ulong)priv->rx_bd, ®s->rxqbase); 394 395 /* Setup for DMA Configuration register */ 396 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 397 398 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 399 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 400 401 /* Disable the second priority queue */ 402 dummy_tx_bd->addr = 0; 403 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 404 ZYNQ_GEM_TXBUF_LAST_MASK| 405 ZYNQ_GEM_TXBUF_USED_MASK; 406 407 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 408 ZYNQ_GEM_RXBUF_NEW_MASK; 409 dummy_rx_bd->status = 0; 410 411 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 412 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 413 414 priv->init++; 415 } 416 417 ret = phy_startup(priv->phydev); 418 if (ret) 419 return ret; 420 421 if (!priv->phydev->link) { 422 printf("%s: No link.\n", priv->phydev->dev->name); 423 return -1; 424 } 425 426 nwconfig = ZYNQ_GEM_NWCFG_INIT; 427 428 if (priv->interface == PHY_INTERFACE_MODE_SGMII) { 429 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | 430 ZYNQ_GEM_NWCFG_PCS_SEL; 431 #ifdef CONFIG_ARM64 432 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, 433 ®s->pcscntrl); 434 #endif 435 } 436 437 switch (priv->phydev->speed) { 438 case SPEED_1000: 439 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, 440 ®s->nwcfg); 441 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 442 break; 443 case SPEED_100: 444 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, 445 ®s->nwcfg); 446 clk_rate = ZYNQ_GEM_FREQUENCY_100; 447 break; 448 case SPEED_10: 449 clk_rate = ZYNQ_GEM_FREQUENCY_10; 450 break; 451 } 452 453 ret = clk_set_rate(&priv->clk, clk_rate); 454 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { 455 dev_err(dev, "failed to set tx clock rate\n"); 456 return ret; 457 } 458 459 ret = clk_enable(&priv->clk); 460 if (ret && ret != -ENOSYS) { 461 dev_err(dev, "failed to enable tx clock\n"); 462 return ret; 463 } 464 465 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 466 ZYNQ_GEM_NWCTRL_TXEN_MASK); 467 468 return 0; 469 } 470 471 static int zynq_gem_send(struct udevice *dev, void *ptr, int len) 472 { 473 u32 addr, size; 474 struct zynq_gem_priv *priv = dev_get_priv(dev); 475 struct zynq_gem_regs *regs = priv->iobase; 476 struct emac_bd *current_bd = &priv->tx_bd[1]; 477 478 /* Setup Tx BD */ 479 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 480 481 priv->tx_bd->addr = (ulong)ptr; 482 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 483 ZYNQ_GEM_TXBUF_LAST_MASK; 484 /* Dummy descriptor to mark it as the last in descriptor chain */ 485 current_bd->addr = 0x0; 486 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 487 ZYNQ_GEM_TXBUF_LAST_MASK| 488 ZYNQ_GEM_TXBUF_USED_MASK; 489 490 /* setup BD */ 491 writel((ulong)priv->tx_bd, ®s->txqbase); 492 493 addr = (ulong) ptr; 494 addr &= ~(ARCH_DMA_MINALIGN - 1); 495 size = roundup(len, ARCH_DMA_MINALIGN); 496 flush_dcache_range(addr, addr + size); 497 498 addr = (ulong)priv->rxbuffers; 499 addr &= ~(ARCH_DMA_MINALIGN - 1); 500 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 501 flush_dcache_range(addr, addr + size); 502 barrier(); 503 504 /* Start transmit */ 505 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 506 507 /* Read TX BD status */ 508 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 509 printf("TX buffers exhausted in mid frame\n"); 510 511 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, 512 true, 20000, true); 513 } 514 515 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 516 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) 517 { 518 int frame_len; 519 u32 addr; 520 struct zynq_gem_priv *priv = dev_get_priv(dev); 521 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 522 523 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 524 return -1; 525 526 if (!(current_bd->status & 527 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 528 printf("GEM: SOF or EOF not set for last buffer received!\n"); 529 return -1; 530 } 531 532 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 533 if (!frame_len) { 534 printf("%s: Zero size packet?\n", __func__); 535 return -1; 536 } 537 538 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 539 addr &= ~(ARCH_DMA_MINALIGN - 1); 540 *packetp = (uchar *)(uintptr_t)addr; 541 542 return frame_len; 543 } 544 545 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) 546 { 547 struct zynq_gem_priv *priv = dev_get_priv(dev); 548 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 549 struct emac_bd *first_bd; 550 551 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { 552 priv->rx_first_buf = priv->rxbd_current; 553 } else { 554 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 555 current_bd->status = 0xF0000000; /* FIXME */ 556 } 557 558 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 559 first_bd = &priv->rx_bd[priv->rx_first_buf]; 560 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 561 first_bd->status = 0xF0000000; 562 } 563 564 if ((++priv->rxbd_current) >= RX_BUF) 565 priv->rxbd_current = 0; 566 567 return 0; 568 } 569 570 static void zynq_gem_halt(struct udevice *dev) 571 { 572 struct zynq_gem_priv *priv = dev_get_priv(dev); 573 struct zynq_gem_regs *regs = priv->iobase; 574 575 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 576 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 577 } 578 579 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 580 { 581 return -ENOSYS; 582 } 583 584 static int zynq_gem_read_rom_mac(struct udevice *dev) 585 { 586 struct eth_pdata *pdata = dev_get_platdata(dev); 587 588 if (!pdata) 589 return -ENOSYS; 590 591 return zynq_board_read_rom_ethaddr(pdata->enetaddr); 592 } 593 594 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, 595 int devad, int reg) 596 { 597 struct zynq_gem_priv *priv = bus->priv; 598 int ret; 599 u16 val; 600 601 ret = phyread(priv, addr, reg, &val); 602 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); 603 return val; 604 } 605 606 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, 607 int reg, u16 value) 608 { 609 struct zynq_gem_priv *priv = bus->priv; 610 611 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); 612 return phywrite(priv, addr, reg, value); 613 } 614 615 static int zynq_gem_probe(struct udevice *dev) 616 { 617 void *bd_space; 618 struct zynq_gem_priv *priv = dev_get_priv(dev); 619 int ret; 620 621 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 622 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 623 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 624 625 /* Align bd_space to MMU_SECTION_SHIFT */ 626 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 627 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 628 BD_SPACE, DCACHE_OFF); 629 630 /* Initialize the bd spaces for tx and rx bd's */ 631 priv->tx_bd = (struct emac_bd *)bd_space; 632 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 633 634 ret = clk_get_by_name(dev, "tx_clk", &priv->clk); 635 if (ret < 0) { 636 dev_err(dev, "failed to get clock\n"); 637 return -EINVAL; 638 } 639 640 priv->bus = mdio_alloc(); 641 priv->bus->read = zynq_gem_miiphy_read; 642 priv->bus->write = zynq_gem_miiphy_write; 643 priv->bus->priv = priv; 644 645 ret = mdio_register_seq(priv->bus, dev->seq); 646 if (ret) 647 return ret; 648 649 return zynq_phy_init(dev); 650 } 651 652 static int zynq_gem_remove(struct udevice *dev) 653 { 654 struct zynq_gem_priv *priv = dev_get_priv(dev); 655 656 free(priv->phydev); 657 mdio_unregister(priv->bus); 658 mdio_free(priv->bus); 659 660 return 0; 661 } 662 663 static const struct eth_ops zynq_gem_ops = { 664 .start = zynq_gem_init, 665 .send = zynq_gem_send, 666 .recv = zynq_gem_recv, 667 .free_pkt = zynq_gem_free_pkt, 668 .stop = zynq_gem_halt, 669 .write_hwaddr = zynq_gem_setup_mac, 670 .read_rom_hwaddr = zynq_gem_read_rom_mac, 671 }; 672 673 static int zynq_gem_ofdata_to_platdata(struct udevice *dev) 674 { 675 struct eth_pdata *pdata = dev_get_platdata(dev); 676 struct zynq_gem_priv *priv = dev_get_priv(dev); 677 int node = dev_of_offset(dev); 678 const char *phy_mode; 679 680 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); 681 priv->iobase = (struct zynq_gem_regs *)pdata->iobase; 682 /* Hardcode for now */ 683 priv->phyaddr = -1; 684 685 priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node, 686 "phy-handle"); 687 if (priv->phy_of_handle > 0) 688 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, 689 priv->phy_of_handle, "reg", -1); 690 691 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); 692 if (phy_mode) 693 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 694 if (pdata->phy_interface == -1) { 695 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 696 return -EINVAL; 697 } 698 priv->interface = pdata->phy_interface; 699 700 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, 701 priv->phyaddr, phy_string_for_interface(priv->interface)); 702 703 return 0; 704 } 705 706 static const struct udevice_id zynq_gem_ids[] = { 707 { .compatible = "cdns,zynqmp-gem" }, 708 { .compatible = "cdns,zynq-gem" }, 709 { .compatible = "cdns,gem" }, 710 { } 711 }; 712 713 U_BOOT_DRIVER(zynq_gem) = { 714 .name = "zynq_gem", 715 .id = UCLASS_ETH, 716 .of_match = zynq_gem_ids, 717 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, 718 .probe = zynq_gem_probe, 719 .remove = zynq_gem_remove, 720 .ops = &zynq_gem_ops, 721 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), 722 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 723 }; 724