1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <net.h> 30 #include <config.h> 31 #include <malloc.h> 32 #include <asm/io.h> 33 #include <phy.h> 34 #include <miiphy.h> 35 #include <watchdog.h> 36 37 #if !defined(CONFIG_PHYLIB) 38 # error XILINX_GEM_ETHERNET requires PHYLIB 39 #endif 40 41 /* Bit/mask specification */ 42 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 43 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 44 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 45 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 46 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 47 48 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 49 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 50 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 51 52 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 53 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 54 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 55 56 /* Wrap bit, last descriptor */ 57 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 58 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 59 60 #define ZYNQ_GEM_TXSR_HRESPNOK_MASK 0x00000100 /* Transmit hresp not OK */ 61 #define ZYNQ_GEM_TXSR_URUN_MASK 0x00000040 /* Transmit underrun */ 62 /* Transmit buffs exhausted mid frame */ 63 #define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x00000010 64 65 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 66 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 67 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 68 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 69 70 #define ZYNQ_GEM_NWCFG_SPEED 0x00000001 /* 100 Mbps operation */ 71 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ 72 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ 73 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ 74 75 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_SPEED | \ 76 ZYNQ_GEM_NWCFG_FDEN | \ 77 ZYNQ_GEM_NWCFG_FSREM | \ 78 ZYNQ_GEM_NWCFG_MDCCLKDIV) 79 80 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 81 82 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 83 /* Use full configured addressable space (8 Kb) */ 84 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 85 /* Use full configured addressable space (4 Kb) */ 86 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 87 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 88 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 89 90 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 91 ZYNQ_GEM_DMACR_RXSIZE | \ 92 ZYNQ_GEM_DMACR_TXSIZE | \ 93 ZYNQ_GEM_DMACR_RXBUF) 94 95 /* Device registers */ 96 struct zynq_gem_regs { 97 u32 nwctrl; /* Network Control reg */ 98 u32 nwcfg; /* Network Config reg */ 99 u32 nwsr; /* Network Status reg */ 100 u32 reserved1; 101 u32 dmacr; /* DMA Control reg */ 102 u32 txsr; /* TX Status reg */ 103 u32 rxqbase; /* RX Q Base address reg */ 104 u32 txqbase; /* TX Q Base address reg */ 105 u32 rxsr; /* RX Status reg */ 106 u32 reserved2[2]; 107 u32 idr; /* Interrupt Disable reg */ 108 u32 reserved3; 109 u32 phymntnc; /* Phy Maintaince reg */ 110 u32 reserved4[18]; 111 u32 hashl; /* Hash Low address reg */ 112 u32 hashh; /* Hash High address reg */ 113 #define LADDR_LOW 0 114 #define LADDR_HIGH 1 115 u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */ 116 u32 match[4]; /* Type ID1 Match reg */ 117 u32 reserved6[18]; 118 u32 stat[44]; /* Octects transmitted Low reg - stat start */ 119 }; 120 121 /* BD descriptors */ 122 struct emac_bd { 123 u32 addr; /* Next descriptor pointer */ 124 u32 status; 125 }; 126 127 #define RX_BUF 3 128 129 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 130 struct zynq_gem_priv { 131 struct emac_bd tx_bd; 132 struct emac_bd rx_bd[RX_BUF]; 133 char rxbuffers[RX_BUF * PKTSIZE_ALIGN]; 134 u32 rxbd_current; 135 u32 rx_first_buf; 136 int phyaddr; 137 struct phy_device *phydev; 138 struct mii_dev *bus; 139 }; 140 141 static inline int mdio_wait(struct eth_device *dev) 142 { 143 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 144 u32 timeout = 200; 145 146 /* Wait till MDIO interface is ready to accept a new transaction. */ 147 while (--timeout) { 148 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 149 break; 150 WATCHDOG_RESET(); 151 } 152 153 if (!timeout) { 154 printf("%s: Timeout\n", __func__); 155 return 1; 156 } 157 158 return 0; 159 } 160 161 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, 162 u32 op, u16 *data) 163 { 164 u32 mgtcr; 165 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 166 167 if (mdio_wait(dev)) 168 return 1; 169 170 /* Construct mgtcr mask for the operation */ 171 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 172 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 173 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 174 175 /* Write mgtcr and wait for completion */ 176 writel(mgtcr, ®s->phymntnc); 177 178 if (mdio_wait(dev)) 179 return 1; 180 181 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 182 *data = readl(®s->phymntnc); 183 184 return 0; 185 } 186 187 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) 188 { 189 return phy_setup_op(dev, phy_addr, regnum, 190 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 191 } 192 193 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) 194 { 195 return phy_setup_op(dev, phy_addr, regnum, 196 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 197 } 198 199 static int zynq_gem_setup_mac(struct eth_device *dev) 200 { 201 u32 i, macaddrlow, macaddrhigh; 202 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 203 204 /* Set the MAC bits [31:0] in BOT */ 205 macaddrlow = dev->enetaddr[0]; 206 macaddrlow |= dev->enetaddr[1] << 8; 207 macaddrlow |= dev->enetaddr[2] << 16; 208 macaddrlow |= dev->enetaddr[3] << 24; 209 210 /* Set MAC bits [47:32] in TOP */ 211 macaddrhigh = dev->enetaddr[4]; 212 macaddrhigh |= dev->enetaddr[5] << 8; 213 214 for (i = 0; i < 4; i++) { 215 writel(0, ®s->laddr[i][LADDR_LOW]); 216 writel(0, ®s->laddr[i][LADDR_HIGH]); 217 /* Do not use MATCHx register */ 218 writel(0, ®s->match[i]); 219 } 220 221 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 222 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 223 224 return 0; 225 } 226 227 static int zynq_gem_init(struct eth_device *dev, bd_t * bis) 228 { 229 u32 i; 230 struct phy_device *phydev; 231 const u32 stat_size = (sizeof(struct zynq_gem_regs) - 232 offsetof(struct zynq_gem_regs, stat)) / 4; 233 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 234 struct zynq_gem_priv *priv = dev->priv; 235 const u32 supported = SUPPORTED_10baseT_Half | 236 SUPPORTED_10baseT_Full | 237 SUPPORTED_100baseT_Half | 238 SUPPORTED_100baseT_Full | 239 SUPPORTED_1000baseT_Half | 240 SUPPORTED_1000baseT_Full; 241 242 /* Disable all interrupts */ 243 writel(0xFFFFFFFF, ®s->idr); 244 245 /* Disable the receiver & transmitter */ 246 writel(0, ®s->nwctrl); 247 writel(0, ®s->txsr); 248 writel(0, ®s->rxsr); 249 writel(0, ®s->phymntnc); 250 251 /* Clear the Hash registers for the mac address pointed by AddressPtr */ 252 writel(0x0, ®s->hashl); 253 /* Write bits [63:32] in TOP */ 254 writel(0x0, ®s->hashh); 255 256 /* Clear all counters */ 257 for (i = 0; i <= stat_size; i++) 258 readl(®s->stat[i]); 259 260 /* Setup RxBD space */ 261 memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd)); 262 /* Create the RxBD ring */ 263 memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers)); 264 265 for (i = 0; i < RX_BUF; i++) { 266 priv->rx_bd[i].status = 0xF0000000; 267 priv->rx_bd[i].addr = (u32)((char *) &(priv->rxbuffers) + 268 (i * PKTSIZE_ALIGN)); 269 } 270 /* WRAP bit to last BD */ 271 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 272 /* Write RxBDs to IP */ 273 writel((u32) &(priv->rx_bd), ®s->rxqbase); 274 275 /* MAC Setup */ 276 /* Setup Network Configuration register */ 277 writel(ZYNQ_GEM_NWCFG_INIT, ®s->nwcfg); 278 279 /* Setup for DMA Configuration register */ 280 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 281 282 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 283 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK | 284 ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); 285 286 /* interface - look at tsec */ 287 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); 288 289 phydev->supported &= supported; 290 phydev->advertising = phydev->supported; 291 priv->phydev = phydev; 292 phy_config(phydev); 293 phy_startup(phydev); 294 295 return 0; 296 } 297 298 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) 299 { 300 u32 status; 301 struct zynq_gem_priv *priv = dev->priv; 302 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 303 const u32 mask = ZYNQ_GEM_TXSR_HRESPNOK_MASK | \ 304 ZYNQ_GEM_TXSR_URUN_MASK | ZYNQ_GEM_TXSR_BUFEXH_MASK; 305 306 /* setup BD */ 307 writel((u32)&(priv->tx_bd), ®s->txqbase); 308 309 /* Setup Tx BD */ 310 memset((void *) &(priv->tx_bd), 0, sizeof(struct emac_bd)); 311 312 priv->tx_bd.addr = (u32)ptr; 313 priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK | 314 ZYNQ_GEM_TXBUF_WRAP_MASK; 315 316 /* Start transmit */ 317 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 318 319 /* Read the stat register to know if the packet has been transmitted */ 320 status = readl(®s->txsr); 321 if (status & mask) 322 printf("Something has gone wrong here!? Status is 0x%x.\n", 323 status); 324 325 /* Clear Tx status register before leaving . */ 326 writel(status, ®s->txsr); 327 return 0; 328 } 329 330 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 331 static int zynq_gem_recv(struct eth_device *dev) 332 { 333 int frame_len; 334 struct zynq_gem_priv *priv = dev->priv; 335 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 336 struct emac_bd *first_bd; 337 338 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 339 return 0; 340 341 if (!(current_bd->status & 342 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 343 printf("GEM: SOF or EOF not set for last buffer received!\n"); 344 return 0; 345 } 346 347 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 348 if (frame_len) { 349 NetReceive((u8 *) (current_bd->addr & 350 ZYNQ_GEM_RXBUF_ADD_MASK), frame_len); 351 352 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 353 priv->rx_first_buf = priv->rxbd_current; 354 else { 355 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 356 current_bd->status = 0xF0000000; /* FIXME */ 357 } 358 359 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 360 first_bd = &priv->rx_bd[priv->rx_first_buf]; 361 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 362 first_bd->status = 0xF0000000; 363 } 364 365 if ((++priv->rxbd_current) >= RX_BUF) 366 priv->rxbd_current = 0; 367 368 return frame_len; 369 } 370 371 return 0; 372 } 373 374 static void zynq_gem_halt(struct eth_device *dev) 375 { 376 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 377 378 /* Disable the receiver & transmitter */ 379 writel(0, ®s->nwctrl); 380 } 381 382 static int zynq_gem_miiphyread(const char *devname, uchar addr, 383 uchar reg, ushort *val) 384 { 385 struct eth_device *dev = eth_get_dev(); 386 int ret; 387 388 ret = phyread(dev, addr, reg, val); 389 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); 390 return ret; 391 } 392 393 static int zynq_gem_miiphy_write(const char *devname, uchar addr, 394 uchar reg, ushort val) 395 { 396 struct eth_device *dev = eth_get_dev(); 397 398 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); 399 return phywrite(dev, addr, reg, val); 400 } 401 402 int zynq_gem_initialize(bd_t *bis, int base_addr) 403 { 404 struct eth_device *dev; 405 struct zynq_gem_priv *priv; 406 407 dev = calloc(1, sizeof(*dev)); 408 if (dev == NULL) 409 return -1; 410 411 dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); 412 if (dev->priv == NULL) { 413 free(dev); 414 return -1; 415 } 416 priv = dev->priv; 417 418 #ifdef CONFIG_PHY_ADDR 419 priv->phyaddr = CONFIG_PHY_ADDR; 420 #else 421 priv->phyaddr = -1; 422 #endif 423 424 sprintf(dev->name, "Gem.%x", base_addr); 425 426 dev->iobase = base_addr; 427 428 dev->init = zynq_gem_init; 429 dev->halt = zynq_gem_halt; 430 dev->send = zynq_gem_send; 431 dev->recv = zynq_gem_recv; 432 dev->write_hwaddr = zynq_gem_setup_mac; 433 434 eth_register(dev); 435 436 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); 437 priv->bus = miiphy_get_dev_by_name(dev->name); 438 439 return 1; 440 } 441