1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2011 Michal Simek 4 * 5 * Michal SIMEK <monstr@monstr.eu> 6 * 7 * Based on Xilinx gmac driver: 8 * (C) Copyright 2011 Xilinx 9 */ 10 11 #include <clk.h> 12 #include <common.h> 13 #include <dm.h> 14 #include <net.h> 15 #include <netdev.h> 16 #include <config.h> 17 #include <console.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <phy.h> 21 #include <miiphy.h> 22 #include <wait_bit.h> 23 #include <watchdog.h> 24 #include <asm/system.h> 25 #include <asm/arch/hardware.h> 26 #include <asm/arch/sys_proto.h> 27 #include <linux/errno.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 /* Bit/mask specification */ 32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 37 38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 41 42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 45 46 /* Wrap bit, last descriptor */ 47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 49 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 50 51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 55 56 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ 57 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ 58 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ 59 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ 60 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ 61 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ 62 #ifdef CONFIG_ARM64 63 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ 64 #else 65 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ 66 #endif 67 68 #ifdef CONFIG_ARM64 69 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 70 #else 71 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 72 #endif 73 74 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 75 ZYNQ_GEM_NWCFG_FDEN | \ 76 ZYNQ_GEM_NWCFG_FSREM | \ 77 ZYNQ_GEM_NWCFG_MDCCLKDIV) 78 79 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 80 81 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 82 /* Use full configured addressable space (8 Kb) */ 83 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 84 /* Use full configured addressable space (4 Kb) */ 85 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 86 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 87 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 88 89 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 90 ZYNQ_GEM_DMACR_RXSIZE | \ 91 ZYNQ_GEM_DMACR_TXSIZE | \ 92 ZYNQ_GEM_DMACR_RXBUF) 93 94 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 95 96 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 97 98 /* Use MII register 1 (MII status register) to detect PHY */ 99 #define PHY_DETECT_REG 1 100 101 /* Mask used to verify certain PHY features (or register contents) 102 * in the register above: 103 * 0x1000: 10Mbps full duplex support 104 * 0x0800: 10Mbps half duplex support 105 * 0x0008: Auto-negotiation support 106 */ 107 #define PHY_DETECT_MASK 0x1808 108 109 /* TX BD status masks */ 110 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 111 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 112 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 113 114 /* Clock frequencies for different speeds */ 115 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 116 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 117 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 118 119 /* Device registers */ 120 struct zynq_gem_regs { 121 u32 nwctrl; /* 0x0 - Network Control reg */ 122 u32 nwcfg; /* 0x4 - Network Config reg */ 123 u32 nwsr; /* 0x8 - Network Status reg */ 124 u32 reserved1; 125 u32 dmacr; /* 0x10 - DMA Control reg */ 126 u32 txsr; /* 0x14 - TX Status reg */ 127 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 128 u32 txqbase; /* 0x1c - TX Q Base address reg */ 129 u32 rxsr; /* 0x20 - RX Status reg */ 130 u32 reserved2[2]; 131 u32 idr; /* 0x2c - Interrupt Disable reg */ 132 u32 reserved3; 133 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 134 u32 reserved4[18]; 135 u32 hashl; /* 0x80 - Hash Low address reg */ 136 u32 hashh; /* 0x84 - Hash High address reg */ 137 #define LADDR_LOW 0 138 #define LADDR_HIGH 1 139 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 140 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 141 u32 reserved6[18]; 142 #define STAT_SIZE 44 143 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 144 u32 reserved9[20]; 145 u32 pcscntrl; 146 u32 reserved7[143]; 147 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 148 u32 reserved8[15]; 149 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 150 }; 151 152 /* BD descriptors */ 153 struct emac_bd { 154 u32 addr; /* Next descriptor pointer */ 155 u32 status; 156 }; 157 158 #define RX_BUF 32 159 /* Page table entries are set to 1MB, or multiples of 1MB 160 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 161 */ 162 #define BD_SPACE 0x100000 163 /* BD separation space */ 164 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 165 166 /* Setup the first free TX descriptor */ 167 #define TX_FREE_DESC 2 168 169 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 170 struct zynq_gem_priv { 171 struct emac_bd *tx_bd; 172 struct emac_bd *rx_bd; 173 char *rxbuffers; 174 u32 rxbd_current; 175 u32 rx_first_buf; 176 int phyaddr; 177 int init; 178 struct zynq_gem_regs *iobase; 179 phy_interface_t interface; 180 struct phy_device *phydev; 181 ofnode phy_of_node; 182 struct mii_dev *bus; 183 struct clk clk; 184 u32 max_speed; 185 bool int_pcs; 186 }; 187 188 static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, 189 u32 op, u16 *data) 190 { 191 u32 mgtcr; 192 struct zynq_gem_regs *regs = priv->iobase; 193 int err; 194 195 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, 196 true, 20000, false); 197 if (err) 198 return err; 199 200 /* Construct mgtcr mask for the operation */ 201 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 202 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 203 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 204 205 /* Write mgtcr and wait for completion */ 206 writel(mgtcr, ®s->phymntnc); 207 208 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, 209 true, 20000, false); 210 if (err) 211 return err; 212 213 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 214 *data = readl(®s->phymntnc); 215 216 return 0; 217 } 218 219 static int phyread(struct zynq_gem_priv *priv, u32 phy_addr, 220 u32 regnum, u16 *val) 221 { 222 int ret; 223 224 ret = phy_setup_op(priv, phy_addr, regnum, 225 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 226 227 if (!ret) 228 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 229 phy_addr, regnum, *val); 230 231 return ret; 232 } 233 234 static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr, 235 u32 regnum, u16 data) 236 { 237 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 238 regnum, data); 239 240 return phy_setup_op(priv, phy_addr, regnum, 241 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 242 } 243 244 static int phy_detection(struct udevice *dev) 245 { 246 int i; 247 u16 phyreg = 0; 248 struct zynq_gem_priv *priv = dev->priv; 249 250 if (priv->phyaddr != -1) { 251 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); 252 if ((phyreg != 0xFFFF) && 253 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 254 /* Found a valid PHY address */ 255 debug("Default phy address %d is valid\n", 256 priv->phyaddr); 257 return 0; 258 } else { 259 debug("PHY address is not setup correctly %d\n", 260 priv->phyaddr); 261 priv->phyaddr = -1; 262 } 263 } 264 265 debug("detecting phy address\n"); 266 if (priv->phyaddr == -1) { 267 /* detect the PHY address */ 268 for (i = 31; i >= 0; i--) { 269 phyread(priv, i, PHY_DETECT_REG, &phyreg); 270 if ((phyreg != 0xFFFF) && 271 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 272 /* Found a valid PHY address */ 273 priv->phyaddr = i; 274 debug("Found valid phy address, %d\n", i); 275 return 0; 276 } 277 } 278 } 279 printf("PHY is not detected\n"); 280 return -1; 281 } 282 283 static int zynq_gem_setup_mac(struct udevice *dev) 284 { 285 u32 i, macaddrlow, macaddrhigh; 286 struct eth_pdata *pdata = dev_get_platdata(dev); 287 struct zynq_gem_priv *priv = dev_get_priv(dev); 288 struct zynq_gem_regs *regs = priv->iobase; 289 290 /* Set the MAC bits [31:0] in BOT */ 291 macaddrlow = pdata->enetaddr[0]; 292 macaddrlow |= pdata->enetaddr[1] << 8; 293 macaddrlow |= pdata->enetaddr[2] << 16; 294 macaddrlow |= pdata->enetaddr[3] << 24; 295 296 /* Set MAC bits [47:32] in TOP */ 297 macaddrhigh = pdata->enetaddr[4]; 298 macaddrhigh |= pdata->enetaddr[5] << 8; 299 300 for (i = 0; i < 4; i++) { 301 writel(0, ®s->laddr[i][LADDR_LOW]); 302 writel(0, ®s->laddr[i][LADDR_HIGH]); 303 /* Do not use MATCHx register */ 304 writel(0, ®s->match[i]); 305 } 306 307 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 308 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 309 310 return 0; 311 } 312 313 static int zynq_phy_init(struct udevice *dev) 314 { 315 int ret; 316 struct zynq_gem_priv *priv = dev_get_priv(dev); 317 struct zynq_gem_regs *regs = priv->iobase; 318 const u32 supported = SUPPORTED_10baseT_Half | 319 SUPPORTED_10baseT_Full | 320 SUPPORTED_100baseT_Half | 321 SUPPORTED_100baseT_Full | 322 SUPPORTED_1000baseT_Half | 323 SUPPORTED_1000baseT_Full; 324 325 /* Enable only MDIO bus */ 326 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); 327 328 if ((priv->interface != PHY_INTERFACE_MODE_SGMII) && 329 (priv->interface != PHY_INTERFACE_MODE_GMII)) { 330 ret = phy_detection(dev); 331 if (ret) { 332 printf("GEM PHY init failed\n"); 333 return ret; 334 } 335 } 336 337 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, 338 priv->interface); 339 if (!priv->phydev) 340 return -ENODEV; 341 342 priv->phydev->supported &= supported | ADVERTISED_Pause | 343 ADVERTISED_Asym_Pause; 344 if (priv->max_speed) { 345 ret = phy_set_supported(priv->phydev, priv->max_speed); 346 if (ret) 347 return ret; 348 } 349 350 priv->phydev->advertising = priv->phydev->supported; 351 priv->phydev->node = priv->phy_of_node; 352 353 return phy_config(priv->phydev); 354 } 355 356 static int zynq_gem_init(struct udevice *dev) 357 { 358 u32 i, nwconfig; 359 int ret; 360 unsigned long clk_rate = 0; 361 struct zynq_gem_priv *priv = dev_get_priv(dev); 362 struct zynq_gem_regs *regs = priv->iobase; 363 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 364 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 365 366 if (!priv->init) { 367 /* Disable all interrupts */ 368 writel(0xFFFFFFFF, ®s->idr); 369 370 /* Disable the receiver & transmitter */ 371 writel(0, ®s->nwctrl); 372 writel(0, ®s->txsr); 373 writel(0, ®s->rxsr); 374 writel(0, ®s->phymntnc); 375 376 /* Clear the Hash registers for the mac address 377 * pointed by AddressPtr 378 */ 379 writel(0x0, ®s->hashl); 380 /* Write bits [63:32] in TOP */ 381 writel(0x0, ®s->hashh); 382 383 /* Clear all counters */ 384 for (i = 0; i < STAT_SIZE; i++) 385 readl(®s->stat[i]); 386 387 /* Setup RxBD space */ 388 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 389 390 for (i = 0; i < RX_BUF; i++) { 391 priv->rx_bd[i].status = 0xF0000000; 392 priv->rx_bd[i].addr = 393 ((ulong)(priv->rxbuffers) + 394 (i * PKTSIZE_ALIGN)); 395 } 396 /* WRAP bit to last BD */ 397 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 398 /* Write RxBDs to IP */ 399 writel((ulong)priv->rx_bd, ®s->rxqbase); 400 401 /* Setup for DMA Configuration register */ 402 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 403 404 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 405 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 406 407 /* Disable the second priority queue */ 408 dummy_tx_bd->addr = 0; 409 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 410 ZYNQ_GEM_TXBUF_LAST_MASK| 411 ZYNQ_GEM_TXBUF_USED_MASK; 412 413 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 414 ZYNQ_GEM_RXBUF_NEW_MASK; 415 dummy_rx_bd->status = 0; 416 417 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 418 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 419 420 priv->init++; 421 } 422 423 ret = phy_startup(priv->phydev); 424 if (ret) 425 return ret; 426 427 if (!priv->phydev->link) { 428 printf("%s: No link.\n", priv->phydev->dev->name); 429 return -1; 430 } 431 432 nwconfig = ZYNQ_GEM_NWCFG_INIT; 433 434 /* 435 * Set SGMII enable PCS selection only if internal PCS/PMA 436 * core is used and interface is SGMII. 437 */ 438 if (priv->interface == PHY_INTERFACE_MODE_SGMII && 439 priv->int_pcs) { 440 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | 441 ZYNQ_GEM_NWCFG_PCS_SEL; 442 #ifdef CONFIG_ARM64 443 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, 444 ®s->pcscntrl); 445 #endif 446 } 447 448 switch (priv->phydev->speed) { 449 case SPEED_1000: 450 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, 451 ®s->nwcfg); 452 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 453 break; 454 case SPEED_100: 455 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, 456 ®s->nwcfg); 457 clk_rate = ZYNQ_GEM_FREQUENCY_100; 458 break; 459 case SPEED_10: 460 clk_rate = ZYNQ_GEM_FREQUENCY_10; 461 break; 462 } 463 464 #if !defined(CONFIG_ARCH_VERSAL) 465 ret = clk_set_rate(&priv->clk, clk_rate); 466 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { 467 dev_err(dev, "failed to set tx clock rate\n"); 468 return ret; 469 } 470 471 ret = clk_enable(&priv->clk); 472 if (ret && ret != -ENOSYS) { 473 dev_err(dev, "failed to enable tx clock\n"); 474 return ret; 475 } 476 #else 477 debug("requested clk_rate %ld\n", clk_rate); 478 #endif 479 480 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 481 ZYNQ_GEM_NWCTRL_TXEN_MASK); 482 483 return 0; 484 } 485 486 static int zynq_gem_send(struct udevice *dev, void *ptr, int len) 487 { 488 u32 addr, size; 489 struct zynq_gem_priv *priv = dev_get_priv(dev); 490 struct zynq_gem_regs *regs = priv->iobase; 491 struct emac_bd *current_bd = &priv->tx_bd[1]; 492 493 /* Setup Tx BD */ 494 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 495 496 priv->tx_bd->addr = (ulong)ptr; 497 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 498 ZYNQ_GEM_TXBUF_LAST_MASK; 499 /* Dummy descriptor to mark it as the last in descriptor chain */ 500 current_bd->addr = 0x0; 501 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 502 ZYNQ_GEM_TXBUF_LAST_MASK| 503 ZYNQ_GEM_TXBUF_USED_MASK; 504 505 /* setup BD */ 506 writel((ulong)priv->tx_bd, ®s->txqbase); 507 508 addr = (ulong) ptr; 509 addr &= ~(ARCH_DMA_MINALIGN - 1); 510 size = roundup(len, ARCH_DMA_MINALIGN); 511 flush_dcache_range(addr, addr + size); 512 513 addr = (ulong)priv->rxbuffers; 514 addr &= ~(ARCH_DMA_MINALIGN - 1); 515 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 516 flush_dcache_range(addr, addr + size); 517 barrier(); 518 519 /* Start transmit */ 520 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 521 522 /* Read TX BD status */ 523 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 524 printf("TX buffers exhausted in mid frame\n"); 525 526 return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, 527 true, 20000, true); 528 } 529 530 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 531 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) 532 { 533 int frame_len; 534 u32 addr; 535 struct zynq_gem_priv *priv = dev_get_priv(dev); 536 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 537 538 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 539 return -1; 540 541 if (!(current_bd->status & 542 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 543 printf("GEM: SOF or EOF not set for last buffer received!\n"); 544 return -1; 545 } 546 547 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 548 if (!frame_len) { 549 printf("%s: Zero size packet?\n", __func__); 550 return -1; 551 } 552 553 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 554 addr &= ~(ARCH_DMA_MINALIGN - 1); 555 *packetp = (uchar *)(uintptr_t)addr; 556 557 return frame_len; 558 } 559 560 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) 561 { 562 struct zynq_gem_priv *priv = dev_get_priv(dev); 563 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 564 struct emac_bd *first_bd; 565 566 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { 567 priv->rx_first_buf = priv->rxbd_current; 568 } else { 569 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 570 current_bd->status = 0xF0000000; /* FIXME */ 571 } 572 573 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 574 first_bd = &priv->rx_bd[priv->rx_first_buf]; 575 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 576 first_bd->status = 0xF0000000; 577 } 578 579 if ((++priv->rxbd_current) >= RX_BUF) 580 priv->rxbd_current = 0; 581 582 return 0; 583 } 584 585 static void zynq_gem_halt(struct udevice *dev) 586 { 587 struct zynq_gem_priv *priv = dev_get_priv(dev); 588 struct zynq_gem_regs *regs = priv->iobase; 589 590 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 591 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 592 } 593 594 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 595 { 596 return -ENOSYS; 597 } 598 599 static int zynq_gem_read_rom_mac(struct udevice *dev) 600 { 601 struct eth_pdata *pdata = dev_get_platdata(dev); 602 603 if (!pdata) 604 return -ENOSYS; 605 606 return zynq_board_read_rom_ethaddr(pdata->enetaddr); 607 } 608 609 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, 610 int devad, int reg) 611 { 612 struct zynq_gem_priv *priv = bus->priv; 613 int ret; 614 u16 val = 0; 615 616 ret = phyread(priv, addr, reg, &val); 617 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); 618 return val; 619 } 620 621 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, 622 int reg, u16 value) 623 { 624 struct zynq_gem_priv *priv = bus->priv; 625 626 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); 627 return phywrite(priv, addr, reg, value); 628 } 629 630 static int zynq_gem_probe(struct udevice *dev) 631 { 632 void *bd_space; 633 struct zynq_gem_priv *priv = dev_get_priv(dev); 634 int ret; 635 636 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 637 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 638 if (!priv->rxbuffers) 639 return -ENOMEM; 640 641 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 642 643 /* Align bd_space to MMU_SECTION_SHIFT */ 644 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 645 if (!bd_space) 646 return -ENOMEM; 647 648 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 649 BD_SPACE, DCACHE_OFF); 650 651 /* Initialize the bd spaces for tx and rx bd's */ 652 priv->tx_bd = (struct emac_bd *)bd_space; 653 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 654 655 ret = clk_get_by_name(dev, "tx_clk", &priv->clk); 656 if (ret < 0) { 657 dev_err(dev, "failed to get clock\n"); 658 return -EINVAL; 659 } 660 661 priv->bus = mdio_alloc(); 662 priv->bus->read = zynq_gem_miiphy_read; 663 priv->bus->write = zynq_gem_miiphy_write; 664 priv->bus->priv = priv; 665 666 ret = mdio_register_seq(priv->bus, dev->seq); 667 if (ret) 668 return ret; 669 670 return zynq_phy_init(dev); 671 } 672 673 static int zynq_gem_remove(struct udevice *dev) 674 { 675 struct zynq_gem_priv *priv = dev_get_priv(dev); 676 677 free(priv->phydev); 678 mdio_unregister(priv->bus); 679 mdio_free(priv->bus); 680 681 return 0; 682 } 683 684 static const struct eth_ops zynq_gem_ops = { 685 .start = zynq_gem_init, 686 .send = zynq_gem_send, 687 .recv = zynq_gem_recv, 688 .free_pkt = zynq_gem_free_pkt, 689 .stop = zynq_gem_halt, 690 .write_hwaddr = zynq_gem_setup_mac, 691 .read_rom_hwaddr = zynq_gem_read_rom_mac, 692 }; 693 694 static int zynq_gem_ofdata_to_platdata(struct udevice *dev) 695 { 696 struct eth_pdata *pdata = dev_get_platdata(dev); 697 struct zynq_gem_priv *priv = dev_get_priv(dev); 698 struct ofnode_phandle_args phandle_args; 699 const char *phy_mode; 700 701 pdata->iobase = (phys_addr_t)dev_read_addr(dev); 702 priv->iobase = (struct zynq_gem_regs *)pdata->iobase; 703 /* Hardcode for now */ 704 priv->phyaddr = -1; 705 706 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, 707 &phandle_args)) { 708 debug("phy-handle does exist %s\n", dev->name); 709 priv->phyaddr = ofnode_read_u32_default(phandle_args.node, 710 "reg", -1); 711 priv->phy_of_node = phandle_args.node; 712 priv->max_speed = ofnode_read_u32_default(phandle_args.node, 713 "max-speed", 714 SPEED_1000); 715 } 716 717 phy_mode = dev_read_prop(dev, "phy-mode", NULL); 718 if (phy_mode) 719 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 720 if (pdata->phy_interface == -1) { 721 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 722 return -EINVAL; 723 } 724 priv->interface = pdata->phy_interface; 725 726 priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma"); 727 728 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, 729 priv->phyaddr, phy_string_for_interface(priv->interface)); 730 731 return 0; 732 } 733 734 static const struct udevice_id zynq_gem_ids[] = { 735 { .compatible = "cdns,zynqmp-gem" }, 736 { .compatible = "cdns,zynq-gem" }, 737 { .compatible = "cdns,gem" }, 738 { } 739 }; 740 741 U_BOOT_DRIVER(zynq_gem) = { 742 .name = "zynq_gem", 743 .id = UCLASS_ETH, 744 .of_match = zynq_gem_ids, 745 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, 746 .probe = zynq_gem_probe, 747 .remove = zynq_gem_remove, 748 .ops = &zynq_gem_ops, 749 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), 750 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 751 }; 752