1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <net.h> 15 #include <netdev.h> 16 #include <config.h> 17 #include <console.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <phy.h> 21 #include <miiphy.h> 22 #include <wait_bit.h> 23 #include <watchdog.h> 24 #include <asm/system.h> 25 #include <asm/arch/hardware.h> 26 #include <asm/arch/sys_proto.h> 27 #include <asm-generic/errno.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 /* Bit/mask specification */ 32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 37 38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 41 42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 45 46 /* Wrap bit, last descriptor */ 47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 49 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 50 51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 55 56 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 57 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 58 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 59 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 60 #ifdef CONFIG_ARM64 61 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */ 62 #else 63 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ 64 #endif 65 66 #ifdef CONFIG_ARM64 67 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 68 #else 69 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 70 #endif 71 72 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 73 ZYNQ_GEM_NWCFG_FDEN | \ 74 ZYNQ_GEM_NWCFG_FSREM | \ 75 ZYNQ_GEM_NWCFG_MDCCLKDIV) 76 77 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 78 79 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 80 /* Use full configured addressable space (8 Kb) */ 81 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 82 /* Use full configured addressable space (4 Kb) */ 83 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 84 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 85 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 86 87 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 88 ZYNQ_GEM_DMACR_RXSIZE | \ 89 ZYNQ_GEM_DMACR_TXSIZE | \ 90 ZYNQ_GEM_DMACR_RXBUF) 91 92 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 93 94 /* Use MII register 1 (MII status register) to detect PHY */ 95 #define PHY_DETECT_REG 1 96 97 /* Mask used to verify certain PHY features (or register contents) 98 * in the register above: 99 * 0x1000: 10Mbps full duplex support 100 * 0x0800: 10Mbps half duplex support 101 * 0x0008: Auto-negotiation support 102 */ 103 #define PHY_DETECT_MASK 0x1808 104 105 /* TX BD status masks */ 106 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 107 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 108 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 109 110 /* Clock frequencies for different speeds */ 111 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 112 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 113 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 114 115 /* Device registers */ 116 struct zynq_gem_regs { 117 u32 nwctrl; /* 0x0 - Network Control reg */ 118 u32 nwcfg; /* 0x4 - Network Config reg */ 119 u32 nwsr; /* 0x8 - Network Status reg */ 120 u32 reserved1; 121 u32 dmacr; /* 0x10 - DMA Control reg */ 122 u32 txsr; /* 0x14 - TX Status reg */ 123 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 124 u32 txqbase; /* 0x1c - TX Q Base address reg */ 125 u32 rxsr; /* 0x20 - RX Status reg */ 126 u32 reserved2[2]; 127 u32 idr; /* 0x2c - Interrupt Disable reg */ 128 u32 reserved3; 129 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 130 u32 reserved4[18]; 131 u32 hashl; /* 0x80 - Hash Low address reg */ 132 u32 hashh; /* 0x84 - Hash High address reg */ 133 #define LADDR_LOW 0 134 #define LADDR_HIGH 1 135 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 136 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 137 u32 reserved6[18]; 138 #define STAT_SIZE 44 139 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 140 u32 reserved7[164]; 141 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 142 u32 reserved8[15]; 143 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 144 }; 145 146 /* BD descriptors */ 147 struct emac_bd { 148 u32 addr; /* Next descriptor pointer */ 149 u32 status; 150 }; 151 152 #define RX_BUF 32 153 /* Page table entries are set to 1MB, or multiples of 1MB 154 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 155 */ 156 #define BD_SPACE 0x100000 157 /* BD separation space */ 158 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 159 160 /* Setup the first free TX descriptor */ 161 #define TX_FREE_DESC 2 162 163 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 164 struct zynq_gem_priv { 165 struct emac_bd *tx_bd; 166 struct emac_bd *rx_bd; 167 char *rxbuffers; 168 u32 rxbd_current; 169 u32 rx_first_buf; 170 int phyaddr; 171 u32 emio; 172 int init; 173 struct zynq_gem_regs *iobase; 174 phy_interface_t interface; 175 struct phy_device *phydev; 176 struct mii_dev *bus; 177 }; 178 179 static inline int mdio_wait(struct zynq_gem_regs *regs) 180 { 181 u32 timeout = 20000; 182 183 /* Wait till MDIO interface is ready to accept a new transaction. */ 184 while (--timeout) { 185 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 186 break; 187 WATCHDOG_RESET(); 188 } 189 190 if (!timeout) { 191 printf("%s: Timeout\n", __func__); 192 return 1; 193 } 194 195 return 0; 196 } 197 198 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, 199 u32 op, u16 *data) 200 { 201 u32 mgtcr; 202 struct zynq_gem_regs *regs = priv->iobase; 203 204 if (mdio_wait(regs)) 205 return 1; 206 207 /* Construct mgtcr mask for the operation */ 208 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 209 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 210 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 211 212 /* Write mgtcr and wait for completion */ 213 writel(mgtcr, ®s->phymntnc); 214 215 if (mdio_wait(regs)) 216 return 1; 217 218 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 219 *data = readl(®s->phymntnc); 220 221 return 0; 222 } 223 224 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, 225 u32 regnum, u16 *val) 226 { 227 u32 ret; 228 229 ret = phy_setup_op(priv, phy_addr, regnum, 230 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 231 232 if (!ret) 233 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 234 phy_addr, regnum, *val); 235 236 return ret; 237 } 238 239 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, 240 u32 regnum, u16 data) 241 { 242 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 243 regnum, data); 244 245 return phy_setup_op(priv, phy_addr, regnum, 246 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 247 } 248 249 static int phy_detection(struct udevice *dev) 250 { 251 int i; 252 u16 phyreg; 253 struct zynq_gem_priv *priv = dev->priv; 254 255 if (priv->phyaddr != -1) { 256 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); 257 if ((phyreg != 0xFFFF) && 258 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 259 /* Found a valid PHY address */ 260 debug("Default phy address %d is valid\n", 261 priv->phyaddr); 262 return 0; 263 } else { 264 debug("PHY address is not setup correctly %d\n", 265 priv->phyaddr); 266 priv->phyaddr = -1; 267 } 268 } 269 270 debug("detecting phy address\n"); 271 if (priv->phyaddr == -1) { 272 /* detect the PHY address */ 273 for (i = 31; i >= 0; i--) { 274 phyread(priv, i, PHY_DETECT_REG, &phyreg); 275 if ((phyreg != 0xFFFF) && 276 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 277 /* Found a valid PHY address */ 278 priv->phyaddr = i; 279 debug("Found valid phy address, %d\n", i); 280 return 0; 281 } 282 } 283 } 284 printf("PHY is not detected\n"); 285 return -1; 286 } 287 288 static int zynq_gem_setup_mac(struct udevice *dev) 289 { 290 u32 i, macaddrlow, macaddrhigh; 291 struct eth_pdata *pdata = dev_get_platdata(dev); 292 struct zynq_gem_priv *priv = dev_get_priv(dev); 293 struct zynq_gem_regs *regs = priv->iobase; 294 295 /* Set the MAC bits [31:0] in BOT */ 296 macaddrlow = pdata->enetaddr[0]; 297 macaddrlow |= pdata->enetaddr[1] << 8; 298 macaddrlow |= pdata->enetaddr[2] << 16; 299 macaddrlow |= pdata->enetaddr[3] << 24; 300 301 /* Set MAC bits [47:32] in TOP */ 302 macaddrhigh = pdata->enetaddr[4]; 303 macaddrhigh |= pdata->enetaddr[5] << 8; 304 305 for (i = 0; i < 4; i++) { 306 writel(0, ®s->laddr[i][LADDR_LOW]); 307 writel(0, ®s->laddr[i][LADDR_HIGH]); 308 /* Do not use MATCHx register */ 309 writel(0, ®s->match[i]); 310 } 311 312 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 313 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 314 315 return 0; 316 } 317 318 static int zynq_phy_init(struct udevice *dev) 319 { 320 int ret; 321 struct zynq_gem_priv *priv = dev_get_priv(dev); 322 struct zynq_gem_regs *regs = priv->iobase; 323 const u32 supported = SUPPORTED_10baseT_Half | 324 SUPPORTED_10baseT_Full | 325 SUPPORTED_100baseT_Half | 326 SUPPORTED_100baseT_Full | 327 SUPPORTED_1000baseT_Half | 328 SUPPORTED_1000baseT_Full; 329 330 /* Enable only MDIO bus */ 331 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); 332 333 ret = phy_detection(dev); 334 if (ret) { 335 printf("GEM PHY init failed\n"); 336 return ret; 337 } 338 339 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, 340 priv->interface); 341 if (!priv->phydev) 342 return -ENODEV; 343 344 priv->phydev->supported = supported | ADVERTISED_Pause | 345 ADVERTISED_Asym_Pause; 346 priv->phydev->advertising = priv->phydev->supported; 347 phy_config(priv->phydev); 348 349 return 0; 350 } 351 352 static int zynq_gem_init(struct udevice *dev) 353 { 354 u32 i; 355 unsigned long clk_rate = 0; 356 struct zynq_gem_priv *priv = dev_get_priv(dev); 357 struct zynq_gem_regs *regs = priv->iobase; 358 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 359 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 360 361 if (!priv->init) { 362 /* Disable all interrupts */ 363 writel(0xFFFFFFFF, ®s->idr); 364 365 /* Disable the receiver & transmitter */ 366 writel(0, ®s->nwctrl); 367 writel(0, ®s->txsr); 368 writel(0, ®s->rxsr); 369 writel(0, ®s->phymntnc); 370 371 /* Clear the Hash registers for the mac address 372 * pointed by AddressPtr 373 */ 374 writel(0x0, ®s->hashl); 375 /* Write bits [63:32] in TOP */ 376 writel(0x0, ®s->hashh); 377 378 /* Clear all counters */ 379 for (i = 0; i < STAT_SIZE; i++) 380 readl(®s->stat[i]); 381 382 /* Setup RxBD space */ 383 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 384 385 for (i = 0; i < RX_BUF; i++) { 386 priv->rx_bd[i].status = 0xF0000000; 387 priv->rx_bd[i].addr = 388 ((ulong)(priv->rxbuffers) + 389 (i * PKTSIZE_ALIGN)); 390 } 391 /* WRAP bit to last BD */ 392 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 393 /* Write RxBDs to IP */ 394 writel((ulong)priv->rx_bd, ®s->rxqbase); 395 396 /* Setup for DMA Configuration register */ 397 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 398 399 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 400 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 401 402 /* Disable the second priority queue */ 403 dummy_tx_bd->addr = 0; 404 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 405 ZYNQ_GEM_TXBUF_LAST_MASK| 406 ZYNQ_GEM_TXBUF_USED_MASK; 407 408 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 409 ZYNQ_GEM_RXBUF_NEW_MASK; 410 dummy_rx_bd->status = 0; 411 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + 412 sizeof(dummy_tx_bd)); 413 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + 414 sizeof(dummy_rx_bd)); 415 416 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 417 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 418 419 priv->init++; 420 } 421 422 phy_startup(priv->phydev); 423 424 if (!priv->phydev->link) { 425 printf("%s: No link.\n", priv->phydev->dev->name); 426 return -1; 427 } 428 429 switch (priv->phydev->speed) { 430 case SPEED_1000: 431 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 432 ®s->nwcfg); 433 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 434 break; 435 case SPEED_100: 436 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100, 437 ®s->nwcfg); 438 clk_rate = ZYNQ_GEM_FREQUENCY_100; 439 break; 440 case SPEED_10: 441 clk_rate = ZYNQ_GEM_FREQUENCY_10; 442 break; 443 } 444 445 /* Change the rclk and clk only not using EMIO interface */ 446 if (!priv->emio) 447 zynq_slcr_gem_clk_setup((ulong)priv->iobase != 448 ZYNQ_GEM_BASEADDR0, clk_rate); 449 450 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 451 ZYNQ_GEM_NWCTRL_TXEN_MASK); 452 453 return 0; 454 } 455 456 static int zynq_gem_send(struct udevice *dev, void *ptr, int len) 457 { 458 u32 addr, size; 459 struct zynq_gem_priv *priv = dev_get_priv(dev); 460 struct zynq_gem_regs *regs = priv->iobase; 461 struct emac_bd *current_bd = &priv->tx_bd[1]; 462 463 /* Setup Tx BD */ 464 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 465 466 priv->tx_bd->addr = (ulong)ptr; 467 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 468 ZYNQ_GEM_TXBUF_LAST_MASK; 469 /* Dummy descriptor to mark it as the last in descriptor chain */ 470 current_bd->addr = 0x0; 471 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 472 ZYNQ_GEM_TXBUF_LAST_MASK| 473 ZYNQ_GEM_TXBUF_USED_MASK; 474 475 /* setup BD */ 476 writel((ulong)priv->tx_bd, ®s->txqbase); 477 478 addr = (ulong) ptr; 479 addr &= ~(ARCH_DMA_MINALIGN - 1); 480 size = roundup(len, ARCH_DMA_MINALIGN); 481 flush_dcache_range(addr, addr + size); 482 483 addr = (ulong)priv->rxbuffers; 484 addr &= ~(ARCH_DMA_MINALIGN - 1); 485 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 486 flush_dcache_range(addr, addr + size); 487 barrier(); 488 489 /* Start transmit */ 490 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 491 492 /* Read TX BD status */ 493 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 494 printf("TX buffers exhausted in mid frame\n"); 495 496 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, 497 true, 20000, true); 498 } 499 500 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 501 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) 502 { 503 int frame_len; 504 u32 addr; 505 struct zynq_gem_priv *priv = dev_get_priv(dev); 506 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 507 508 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 509 return -1; 510 511 if (!(current_bd->status & 512 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 513 printf("GEM: SOF or EOF not set for last buffer received!\n"); 514 return -1; 515 } 516 517 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 518 if (!frame_len) { 519 printf("%s: Zero size packet?\n", __func__); 520 return -1; 521 } 522 523 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 524 addr &= ~(ARCH_DMA_MINALIGN - 1); 525 *packetp = (uchar *)(uintptr_t)addr; 526 527 return frame_len; 528 } 529 530 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) 531 { 532 struct zynq_gem_priv *priv = dev_get_priv(dev); 533 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 534 struct emac_bd *first_bd; 535 536 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { 537 priv->rx_first_buf = priv->rxbd_current; 538 } else { 539 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 540 current_bd->status = 0xF0000000; /* FIXME */ 541 } 542 543 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 544 first_bd = &priv->rx_bd[priv->rx_first_buf]; 545 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 546 first_bd->status = 0xF0000000; 547 } 548 549 if ((++priv->rxbd_current) >= RX_BUF) 550 priv->rxbd_current = 0; 551 552 return 0; 553 } 554 555 static void zynq_gem_halt(struct udevice *dev) 556 { 557 struct zynq_gem_priv *priv = dev_get_priv(dev); 558 struct zynq_gem_regs *regs = priv->iobase; 559 560 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 561 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 562 } 563 564 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, 565 int devad, int reg) 566 { 567 struct zynq_gem_priv *priv = bus->priv; 568 int ret; 569 u16 val; 570 571 ret = phyread(priv, addr, reg, &val); 572 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); 573 return val; 574 } 575 576 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, 577 int reg, u16 value) 578 { 579 struct zynq_gem_priv *priv = bus->priv; 580 581 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); 582 return phywrite(priv, addr, reg, value); 583 } 584 585 static int zynq_gem_probe(struct udevice *dev) 586 { 587 void *bd_space; 588 struct zynq_gem_priv *priv = dev_get_priv(dev); 589 int ret; 590 591 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 592 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 593 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 594 595 /* Align bd_space to MMU_SECTION_SHIFT */ 596 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 597 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 598 BD_SPACE, DCACHE_OFF); 599 600 /* Initialize the bd spaces for tx and rx bd's */ 601 priv->tx_bd = (struct emac_bd *)bd_space; 602 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 603 604 priv->bus = mdio_alloc(); 605 priv->bus->read = zynq_gem_miiphy_read; 606 priv->bus->write = zynq_gem_miiphy_write; 607 priv->bus->priv = priv; 608 strcpy(priv->bus->name, "gem"); 609 610 ret = mdio_register(priv->bus); 611 if (ret) 612 return ret; 613 614 zynq_phy_init(dev); 615 616 return 0; 617 } 618 619 static int zynq_gem_remove(struct udevice *dev) 620 { 621 struct zynq_gem_priv *priv = dev_get_priv(dev); 622 623 free(priv->phydev); 624 mdio_unregister(priv->bus); 625 mdio_free(priv->bus); 626 627 return 0; 628 } 629 630 static const struct eth_ops zynq_gem_ops = { 631 .start = zynq_gem_init, 632 .send = zynq_gem_send, 633 .recv = zynq_gem_recv, 634 .free_pkt = zynq_gem_free_pkt, 635 .stop = zynq_gem_halt, 636 .write_hwaddr = zynq_gem_setup_mac, 637 }; 638 639 static int zynq_gem_ofdata_to_platdata(struct udevice *dev) 640 { 641 struct eth_pdata *pdata = dev_get_platdata(dev); 642 struct zynq_gem_priv *priv = dev_get_priv(dev); 643 int offset = 0; 644 const char *phy_mode; 645 646 pdata->iobase = (phys_addr_t)dev_get_addr(dev); 647 priv->iobase = (struct zynq_gem_regs *)pdata->iobase; 648 /* Hardcode for now */ 649 priv->emio = 0; 650 priv->phyaddr = -1; 651 652 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, 653 "phy-handle"); 654 if (offset > 0) 655 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); 656 657 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 658 if (phy_mode) 659 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 660 if (pdata->phy_interface == -1) { 661 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 662 return -EINVAL; 663 } 664 priv->interface = pdata->phy_interface; 665 666 printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, 667 priv->phyaddr, phy_string_for_interface(priv->interface)); 668 669 return 0; 670 } 671 672 static const struct udevice_id zynq_gem_ids[] = { 673 { .compatible = "cdns,zynqmp-gem" }, 674 { .compatible = "cdns,zynq-gem" }, 675 { .compatible = "cdns,gem" }, 676 { } 677 }; 678 679 U_BOOT_DRIVER(zynq_gem) = { 680 .name = "zynq_gem", 681 .id = UCLASS_ETH, 682 .of_match = zynq_gem_ids, 683 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, 684 .probe = zynq_gem_probe, 685 .remove = zynq_gem_remove, 686 .ops = &zynq_gem_ops, 687 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), 688 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 689 }; 690