1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <clk.h> 13 #include <common.h> 14 #include <dm.h> 15 #include <net.h> 16 #include <netdev.h> 17 #include <config.h> 18 #include <console.h> 19 #include <malloc.h> 20 #include <asm/io.h> 21 #include <phy.h> 22 #include <miiphy.h> 23 #include <wait_bit.h> 24 #include <watchdog.h> 25 #include <asm/system.h> 26 #include <asm/arch/hardware.h> 27 #include <asm/arch/sys_proto.h> 28 #include <linux/errno.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 /* Bit/mask specification */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 38 39 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 40 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 41 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 42 43 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 44 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 45 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 46 47 /* Wrap bit, last descriptor */ 48 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 49 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 50 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 51 52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 56 57 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ 58 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ 59 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ 60 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ 61 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ 62 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ 63 #ifdef CONFIG_ARM64 64 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ 65 #else 66 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ 67 #endif 68 69 #ifdef CONFIG_ARM64 70 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 71 #else 72 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 73 #endif 74 75 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 76 ZYNQ_GEM_NWCFG_FDEN | \ 77 ZYNQ_GEM_NWCFG_FSREM | \ 78 ZYNQ_GEM_NWCFG_MDCCLKDIV) 79 80 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 81 82 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 83 /* Use full configured addressable space (8 Kb) */ 84 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 85 /* Use full configured addressable space (4 Kb) */ 86 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 87 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 88 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 89 90 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 91 ZYNQ_GEM_DMACR_RXSIZE | \ 92 ZYNQ_GEM_DMACR_TXSIZE | \ 93 ZYNQ_GEM_DMACR_RXBUF) 94 95 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 96 97 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 98 99 /* Use MII register 1 (MII status register) to detect PHY */ 100 #define PHY_DETECT_REG 1 101 102 /* Mask used to verify certain PHY features (or register contents) 103 * in the register above: 104 * 0x1000: 10Mbps full duplex support 105 * 0x0800: 10Mbps half duplex support 106 * 0x0008: Auto-negotiation support 107 */ 108 #define PHY_DETECT_MASK 0x1808 109 110 /* TX BD status masks */ 111 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 112 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 113 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 114 115 /* Clock frequencies for different speeds */ 116 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 117 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 118 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 119 120 /* Device registers */ 121 struct zynq_gem_regs { 122 u32 nwctrl; /* 0x0 - Network Control reg */ 123 u32 nwcfg; /* 0x4 - Network Config reg */ 124 u32 nwsr; /* 0x8 - Network Status reg */ 125 u32 reserved1; 126 u32 dmacr; /* 0x10 - DMA Control reg */ 127 u32 txsr; /* 0x14 - TX Status reg */ 128 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 129 u32 txqbase; /* 0x1c - TX Q Base address reg */ 130 u32 rxsr; /* 0x20 - RX Status reg */ 131 u32 reserved2[2]; 132 u32 idr; /* 0x2c - Interrupt Disable reg */ 133 u32 reserved3; 134 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 135 u32 reserved4[18]; 136 u32 hashl; /* 0x80 - Hash Low address reg */ 137 u32 hashh; /* 0x84 - Hash High address reg */ 138 #define LADDR_LOW 0 139 #define LADDR_HIGH 1 140 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 141 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 142 u32 reserved6[18]; 143 #define STAT_SIZE 44 144 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 145 u32 reserved9[20]; 146 u32 pcscntrl; 147 u32 reserved7[143]; 148 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 149 u32 reserved8[15]; 150 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 151 }; 152 153 /* BD descriptors */ 154 struct emac_bd { 155 u32 addr; /* Next descriptor pointer */ 156 u32 status; 157 }; 158 159 #define RX_BUF 32 160 /* Page table entries are set to 1MB, or multiples of 1MB 161 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 162 */ 163 #define BD_SPACE 0x100000 164 /* BD separation space */ 165 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 166 167 /* Setup the first free TX descriptor */ 168 #define TX_FREE_DESC 2 169 170 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 171 struct zynq_gem_priv { 172 struct emac_bd *tx_bd; 173 struct emac_bd *rx_bd; 174 char *rxbuffers; 175 u32 rxbd_current; 176 u32 rx_first_buf; 177 int phyaddr; 178 int init; 179 struct zynq_gem_regs *iobase; 180 phy_interface_t interface; 181 struct phy_device *phydev; 182 int phy_of_handle; 183 struct mii_dev *bus; 184 struct clk clk; 185 u32 max_speed; 186 bool int_pcs; 187 }; 188 189 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, 190 u32 op, u16 *data) 191 { 192 u32 mgtcr; 193 struct zynq_gem_regs *regs = priv->iobase; 194 int err; 195 196 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, 197 true, 20000, false); 198 if (err) 199 return err; 200 201 /* Construct mgtcr mask for the operation */ 202 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 203 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 204 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 205 206 /* Write mgtcr and wait for completion */ 207 writel(mgtcr, ®s->phymntnc); 208 209 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, 210 true, 20000, false); 211 if (err) 212 return err; 213 214 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 215 *data = readl(®s->phymntnc); 216 217 return 0; 218 } 219 220 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, 221 u32 regnum, u16 *val) 222 { 223 u32 ret; 224 225 ret = phy_setup_op(priv, phy_addr, regnum, 226 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 227 228 if (!ret) 229 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 230 phy_addr, regnum, *val); 231 232 return ret; 233 } 234 235 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, 236 u32 regnum, u16 data) 237 { 238 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 239 regnum, data); 240 241 return phy_setup_op(priv, phy_addr, regnum, 242 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 243 } 244 245 static int phy_detection(struct udevice *dev) 246 { 247 int i; 248 u16 phyreg; 249 struct zynq_gem_priv *priv = dev->priv; 250 251 if (priv->phyaddr != -1) { 252 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); 253 if ((phyreg != 0xFFFF) && 254 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 255 /* Found a valid PHY address */ 256 debug("Default phy address %d is valid\n", 257 priv->phyaddr); 258 return 0; 259 } else { 260 debug("PHY address is not setup correctly %d\n", 261 priv->phyaddr); 262 priv->phyaddr = -1; 263 } 264 } 265 266 debug("detecting phy address\n"); 267 if (priv->phyaddr == -1) { 268 /* detect the PHY address */ 269 for (i = 31; i >= 0; i--) { 270 phyread(priv, i, PHY_DETECT_REG, &phyreg); 271 if ((phyreg != 0xFFFF) && 272 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 273 /* Found a valid PHY address */ 274 priv->phyaddr = i; 275 debug("Found valid phy address, %d\n", i); 276 return 0; 277 } 278 } 279 } 280 printf("PHY is not detected\n"); 281 return -1; 282 } 283 284 static int zynq_gem_setup_mac(struct udevice *dev) 285 { 286 u32 i, macaddrlow, macaddrhigh; 287 struct eth_pdata *pdata = dev_get_platdata(dev); 288 struct zynq_gem_priv *priv = dev_get_priv(dev); 289 struct zynq_gem_regs *regs = priv->iobase; 290 291 /* Set the MAC bits [31:0] in BOT */ 292 macaddrlow = pdata->enetaddr[0]; 293 macaddrlow |= pdata->enetaddr[1] << 8; 294 macaddrlow |= pdata->enetaddr[2] << 16; 295 macaddrlow |= pdata->enetaddr[3] << 24; 296 297 /* Set MAC bits [47:32] in TOP */ 298 macaddrhigh = pdata->enetaddr[4]; 299 macaddrhigh |= pdata->enetaddr[5] << 8; 300 301 for (i = 0; i < 4; i++) { 302 writel(0, ®s->laddr[i][LADDR_LOW]); 303 writel(0, ®s->laddr[i][LADDR_HIGH]); 304 /* Do not use MATCHx register */ 305 writel(0, ®s->match[i]); 306 } 307 308 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 309 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 310 311 return 0; 312 } 313 314 static int zynq_phy_init(struct udevice *dev) 315 { 316 int ret; 317 struct zynq_gem_priv *priv = dev_get_priv(dev); 318 struct zynq_gem_regs *regs = priv->iobase; 319 const u32 supported = SUPPORTED_10baseT_Half | 320 SUPPORTED_10baseT_Full | 321 SUPPORTED_100baseT_Half | 322 SUPPORTED_100baseT_Full | 323 SUPPORTED_1000baseT_Half | 324 SUPPORTED_1000baseT_Full; 325 326 /* Enable only MDIO bus */ 327 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); 328 329 if ((priv->interface != PHY_INTERFACE_MODE_SGMII) && 330 (priv->interface != PHY_INTERFACE_MODE_GMII)) { 331 ret = phy_detection(dev); 332 if (ret) { 333 printf("GEM PHY init failed\n"); 334 return ret; 335 } 336 } 337 338 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, 339 priv->interface); 340 if (!priv->phydev) 341 return -ENODEV; 342 343 priv->phydev->supported &= supported | ADVERTISED_Pause | 344 ADVERTISED_Asym_Pause; 345 if (priv->max_speed) { 346 ret = phy_set_supported(priv->phydev, priv->max_speed); 347 if (ret) 348 return ret; 349 } 350 351 priv->phydev->advertising = priv->phydev->supported; 352 353 if (priv->phy_of_handle > 0) 354 dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle); 355 356 return phy_config(priv->phydev); 357 } 358 359 static int zynq_gem_init(struct udevice *dev) 360 { 361 u32 i, nwconfig; 362 int ret; 363 unsigned long clk_rate = 0; 364 struct zynq_gem_priv *priv = dev_get_priv(dev); 365 struct zynq_gem_regs *regs = priv->iobase; 366 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 367 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 368 369 if (!priv->init) { 370 /* Disable all interrupts */ 371 writel(0xFFFFFFFF, ®s->idr); 372 373 /* Disable the receiver & transmitter */ 374 writel(0, ®s->nwctrl); 375 writel(0, ®s->txsr); 376 writel(0, ®s->rxsr); 377 writel(0, ®s->phymntnc); 378 379 /* Clear the Hash registers for the mac address 380 * pointed by AddressPtr 381 */ 382 writel(0x0, ®s->hashl); 383 /* Write bits [63:32] in TOP */ 384 writel(0x0, ®s->hashh); 385 386 /* Clear all counters */ 387 for (i = 0; i < STAT_SIZE; i++) 388 readl(®s->stat[i]); 389 390 /* Setup RxBD space */ 391 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 392 393 for (i = 0; i < RX_BUF; i++) { 394 priv->rx_bd[i].status = 0xF0000000; 395 priv->rx_bd[i].addr = 396 ((ulong)(priv->rxbuffers) + 397 (i * PKTSIZE_ALIGN)); 398 } 399 /* WRAP bit to last BD */ 400 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 401 /* Write RxBDs to IP */ 402 writel((ulong)priv->rx_bd, ®s->rxqbase); 403 404 /* Setup for DMA Configuration register */ 405 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 406 407 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 408 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 409 410 /* Disable the second priority queue */ 411 dummy_tx_bd->addr = 0; 412 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 413 ZYNQ_GEM_TXBUF_LAST_MASK| 414 ZYNQ_GEM_TXBUF_USED_MASK; 415 416 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 417 ZYNQ_GEM_RXBUF_NEW_MASK; 418 dummy_rx_bd->status = 0; 419 420 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 421 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 422 423 priv->init++; 424 } 425 426 ret = phy_startup(priv->phydev); 427 if (ret) 428 return ret; 429 430 if (!priv->phydev->link) { 431 printf("%s: No link.\n", priv->phydev->dev->name); 432 return -1; 433 } 434 435 nwconfig = ZYNQ_GEM_NWCFG_INIT; 436 437 /* 438 * Set SGMII enable PCS selection only if internal PCS/PMA 439 * core is used and interface is SGMII. 440 */ 441 if (priv->interface == PHY_INTERFACE_MODE_SGMII && 442 priv->int_pcs) { 443 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | 444 ZYNQ_GEM_NWCFG_PCS_SEL; 445 #ifdef CONFIG_ARM64 446 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, 447 ®s->pcscntrl); 448 #endif 449 } 450 451 switch (priv->phydev->speed) { 452 case SPEED_1000: 453 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, 454 ®s->nwcfg); 455 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 456 break; 457 case SPEED_100: 458 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, 459 ®s->nwcfg); 460 clk_rate = ZYNQ_GEM_FREQUENCY_100; 461 break; 462 case SPEED_10: 463 clk_rate = ZYNQ_GEM_FREQUENCY_10; 464 break; 465 } 466 467 ret = clk_set_rate(&priv->clk, clk_rate); 468 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { 469 dev_err(dev, "failed to set tx clock rate\n"); 470 return ret; 471 } 472 473 ret = clk_enable(&priv->clk); 474 if (ret && ret != -ENOSYS) { 475 dev_err(dev, "failed to enable tx clock\n"); 476 return ret; 477 } 478 479 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 480 ZYNQ_GEM_NWCTRL_TXEN_MASK); 481 482 return 0; 483 } 484 485 static int zynq_gem_send(struct udevice *dev, void *ptr, int len) 486 { 487 u32 addr, size; 488 struct zynq_gem_priv *priv = dev_get_priv(dev); 489 struct zynq_gem_regs *regs = priv->iobase; 490 struct emac_bd *current_bd = &priv->tx_bd[1]; 491 492 /* Setup Tx BD */ 493 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 494 495 priv->tx_bd->addr = (ulong)ptr; 496 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 497 ZYNQ_GEM_TXBUF_LAST_MASK; 498 /* Dummy descriptor to mark it as the last in descriptor chain */ 499 current_bd->addr = 0x0; 500 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 501 ZYNQ_GEM_TXBUF_LAST_MASK| 502 ZYNQ_GEM_TXBUF_USED_MASK; 503 504 /* setup BD */ 505 writel((ulong)priv->tx_bd, ®s->txqbase); 506 507 addr = (ulong) ptr; 508 addr &= ~(ARCH_DMA_MINALIGN - 1); 509 size = roundup(len, ARCH_DMA_MINALIGN); 510 flush_dcache_range(addr, addr + size); 511 512 addr = (ulong)priv->rxbuffers; 513 addr &= ~(ARCH_DMA_MINALIGN - 1); 514 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 515 flush_dcache_range(addr, addr + size); 516 barrier(); 517 518 /* Start transmit */ 519 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 520 521 /* Read TX BD status */ 522 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 523 printf("TX buffers exhausted in mid frame\n"); 524 525 return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, 526 true, 20000, true); 527 } 528 529 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 530 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) 531 { 532 int frame_len; 533 u32 addr; 534 struct zynq_gem_priv *priv = dev_get_priv(dev); 535 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 536 537 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 538 return -1; 539 540 if (!(current_bd->status & 541 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 542 printf("GEM: SOF or EOF not set for last buffer received!\n"); 543 return -1; 544 } 545 546 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 547 if (!frame_len) { 548 printf("%s: Zero size packet?\n", __func__); 549 return -1; 550 } 551 552 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 553 addr &= ~(ARCH_DMA_MINALIGN - 1); 554 *packetp = (uchar *)(uintptr_t)addr; 555 556 return frame_len; 557 } 558 559 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) 560 { 561 struct zynq_gem_priv *priv = dev_get_priv(dev); 562 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 563 struct emac_bd *first_bd; 564 565 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { 566 priv->rx_first_buf = priv->rxbd_current; 567 } else { 568 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 569 current_bd->status = 0xF0000000; /* FIXME */ 570 } 571 572 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 573 first_bd = &priv->rx_bd[priv->rx_first_buf]; 574 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 575 first_bd->status = 0xF0000000; 576 } 577 578 if ((++priv->rxbd_current) >= RX_BUF) 579 priv->rxbd_current = 0; 580 581 return 0; 582 } 583 584 static void zynq_gem_halt(struct udevice *dev) 585 { 586 struct zynq_gem_priv *priv = dev_get_priv(dev); 587 struct zynq_gem_regs *regs = priv->iobase; 588 589 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 590 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 591 } 592 593 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 594 { 595 return -ENOSYS; 596 } 597 598 static int zynq_gem_read_rom_mac(struct udevice *dev) 599 { 600 struct eth_pdata *pdata = dev_get_platdata(dev); 601 602 if (!pdata) 603 return -ENOSYS; 604 605 return zynq_board_read_rom_ethaddr(pdata->enetaddr); 606 } 607 608 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, 609 int devad, int reg) 610 { 611 struct zynq_gem_priv *priv = bus->priv; 612 int ret; 613 u16 val; 614 615 ret = phyread(priv, addr, reg, &val); 616 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); 617 return val; 618 } 619 620 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, 621 int reg, u16 value) 622 { 623 struct zynq_gem_priv *priv = bus->priv; 624 625 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); 626 return phywrite(priv, addr, reg, value); 627 } 628 629 static int zynq_gem_probe(struct udevice *dev) 630 { 631 void *bd_space; 632 struct zynq_gem_priv *priv = dev_get_priv(dev); 633 int ret; 634 635 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 636 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 637 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 638 639 /* Align bd_space to MMU_SECTION_SHIFT */ 640 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 641 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 642 BD_SPACE, DCACHE_OFF); 643 644 /* Initialize the bd spaces for tx and rx bd's */ 645 priv->tx_bd = (struct emac_bd *)bd_space; 646 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 647 648 ret = clk_get_by_name(dev, "tx_clk", &priv->clk); 649 if (ret < 0) { 650 dev_err(dev, "failed to get clock\n"); 651 return -EINVAL; 652 } 653 654 priv->bus = mdio_alloc(); 655 priv->bus->read = zynq_gem_miiphy_read; 656 priv->bus->write = zynq_gem_miiphy_write; 657 priv->bus->priv = priv; 658 659 ret = mdio_register_seq(priv->bus, dev->seq); 660 if (ret) 661 return ret; 662 663 return zynq_phy_init(dev); 664 } 665 666 static int zynq_gem_remove(struct udevice *dev) 667 { 668 struct zynq_gem_priv *priv = dev_get_priv(dev); 669 670 free(priv->phydev); 671 mdio_unregister(priv->bus); 672 mdio_free(priv->bus); 673 674 return 0; 675 } 676 677 static const struct eth_ops zynq_gem_ops = { 678 .start = zynq_gem_init, 679 .send = zynq_gem_send, 680 .recv = zynq_gem_recv, 681 .free_pkt = zynq_gem_free_pkt, 682 .stop = zynq_gem_halt, 683 .write_hwaddr = zynq_gem_setup_mac, 684 .read_rom_hwaddr = zynq_gem_read_rom_mac, 685 }; 686 687 static int zynq_gem_ofdata_to_platdata(struct udevice *dev) 688 { 689 struct eth_pdata *pdata = dev_get_platdata(dev); 690 struct zynq_gem_priv *priv = dev_get_priv(dev); 691 int node = dev_of_offset(dev); 692 const char *phy_mode; 693 694 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); 695 priv->iobase = (struct zynq_gem_regs *)pdata->iobase; 696 /* Hardcode for now */ 697 priv->phyaddr = -1; 698 699 priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node, 700 "phy-handle"); 701 if (priv->phy_of_handle > 0) 702 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, 703 priv->phy_of_handle, "reg", -1); 704 705 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); 706 if (phy_mode) 707 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 708 if (pdata->phy_interface == -1) { 709 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 710 return -EINVAL; 711 } 712 priv->interface = pdata->phy_interface; 713 714 priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv->phy_of_handle, 715 "max-speed", SPEED_1000); 716 priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node, 717 "is-internal-pcspma"); 718 719 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, 720 priv->phyaddr, phy_string_for_interface(priv->interface)); 721 722 return 0; 723 } 724 725 static const struct udevice_id zynq_gem_ids[] = { 726 { .compatible = "cdns,zynqmp-gem" }, 727 { .compatible = "cdns,zynq-gem" }, 728 { .compatible = "cdns,gem" }, 729 { } 730 }; 731 732 U_BOOT_DRIVER(zynq_gem) = { 733 .name = "zynq_gem", 734 .id = UCLASS_ETH, 735 .of_match = zynq_gem_ids, 736 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, 737 .probe = zynq_gem_probe, 738 .remove = zynq_gem_remove, 739 .ops = &zynq_gem_ops, 740 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), 741 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 742 }; 743