1185f7d9aSMichal Simek /* 2185f7d9aSMichal Simek * (C) Copyright 2011 Michal Simek 3185f7d9aSMichal Simek * 4185f7d9aSMichal Simek * Michal SIMEK <monstr@monstr.eu> 5185f7d9aSMichal Simek * 6185f7d9aSMichal Simek * Based on Xilinx gmac driver: 7185f7d9aSMichal Simek * (C) Copyright 2011 Xilinx 8185f7d9aSMichal Simek * 91a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 10185f7d9aSMichal Simek */ 11185f7d9aSMichal Simek 12185f7d9aSMichal Simek #include <common.h> 13185f7d9aSMichal Simek #include <net.h> 142fd2489bSMichal Simek #include <netdev.h> 15185f7d9aSMichal Simek #include <config.h> 16f88a6869SMichal Simek #include <fdtdec.h> 17f88a6869SMichal Simek #include <libfdt.h> 18185f7d9aSMichal Simek #include <malloc.h> 19185f7d9aSMichal Simek #include <asm/io.h> 20185f7d9aSMichal Simek #include <phy.h> 21185f7d9aSMichal Simek #include <miiphy.h> 22185f7d9aSMichal Simek #include <watchdog.h> 2396f4f149SSiva Durga Prasad Paladugu #include <asm/system.h> 2401fbf310SDavid Andrey #include <asm/arch/hardware.h> 2580243528SMichal Simek #include <asm/arch/sys_proto.h> 26*e4d2318aSMichal Simek #include <asm-generic/errno.h> 27185f7d9aSMichal Simek 28185f7d9aSMichal Simek #if !defined(CONFIG_PHYLIB) 29185f7d9aSMichal Simek # error XILINX_GEM_ETHERNET requires PHYLIB 30185f7d9aSMichal Simek #endif 31185f7d9aSMichal Simek 32185f7d9aSMichal Simek /* Bit/mask specification */ 33185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 34185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 35185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 36185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 37185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 38185f7d9aSMichal Simek 39185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 40185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 41185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 42185f7d9aSMichal Simek 43185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 44185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 45185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 46185f7d9aSMichal Simek 47185f7d9aSMichal Simek /* Wrap bit, last descriptor */ 48185f7d9aSMichal Simek #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 49185f7d9aSMichal Simek #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 5023a598f7SMichal Simek #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 51185f7d9aSMichal Simek 52185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 53185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 54185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 55185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 56185f7d9aSMichal Simek 5780243528SMichal Simek #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 5880243528SMichal Simek #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 5980243528SMichal Simek #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 6080243528SMichal Simek #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 61185f7d9aSMichal Simek #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ 6280243528SMichal Simek #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ 63185f7d9aSMichal Simek 648a584c8aSSiva Durga Prasad Paladugu #ifdef CONFIG_ARM64 658a584c8aSSiva Durga Prasad Paladugu # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 668a584c8aSSiva Durga Prasad Paladugu #else 678a584c8aSSiva Durga Prasad Paladugu # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 688a584c8aSSiva Durga Prasad Paladugu #endif 698a584c8aSSiva Durga Prasad Paladugu 708a584c8aSSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 718a584c8aSSiva Durga Prasad Paladugu ZYNQ_GEM_NWCFG_FDEN | \ 72185f7d9aSMichal Simek ZYNQ_GEM_NWCFG_FSREM | \ 73185f7d9aSMichal Simek ZYNQ_GEM_NWCFG_MDCCLKDIV) 74185f7d9aSMichal Simek 75185f7d9aSMichal Simek #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 76185f7d9aSMichal Simek 77185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 78185f7d9aSMichal Simek /* Use full configured addressable space (8 Kb) */ 79185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 80185f7d9aSMichal Simek /* Use full configured addressable space (4 Kb) */ 81185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 82185f7d9aSMichal Simek /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 83185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 84185f7d9aSMichal Simek 85185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 86185f7d9aSMichal Simek ZYNQ_GEM_DMACR_RXSIZE | \ 87185f7d9aSMichal Simek ZYNQ_GEM_DMACR_TXSIZE | \ 88185f7d9aSMichal Simek ZYNQ_GEM_DMACR_RXBUF) 89185f7d9aSMichal Simek 90*e4d2318aSMichal Simek #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 91*e4d2318aSMichal Simek 92f97d7e8bSMichal Simek /* Use MII register 1 (MII status register) to detect PHY */ 93f97d7e8bSMichal Simek #define PHY_DETECT_REG 1 94f97d7e8bSMichal Simek 95f97d7e8bSMichal Simek /* Mask used to verify certain PHY features (or register contents) 96f97d7e8bSMichal Simek * in the register above: 97f97d7e8bSMichal Simek * 0x1000: 10Mbps full duplex support 98f97d7e8bSMichal Simek * 0x0800: 10Mbps half duplex support 99f97d7e8bSMichal Simek * 0x0008: Auto-negotiation support 100f97d7e8bSMichal Simek */ 101f97d7e8bSMichal Simek #define PHY_DETECT_MASK 0x1808 102f97d7e8bSMichal Simek 103a5144237SSrikanth Thokala /* TX BD status masks */ 104a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 105a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 106a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 107a5144237SSrikanth Thokala 10897598fcfSSoren Brinkmann /* Clock frequencies for different speeds */ 10997598fcfSSoren Brinkmann #define ZYNQ_GEM_FREQUENCY_10 2500000UL 11097598fcfSSoren Brinkmann #define ZYNQ_GEM_FREQUENCY_100 25000000UL 11197598fcfSSoren Brinkmann #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 11297598fcfSSoren Brinkmann 113185f7d9aSMichal Simek /* Device registers */ 114185f7d9aSMichal Simek struct zynq_gem_regs { 11597a51a03SMichal Simek u32 nwctrl; /* 0x0 - Network Control reg */ 11697a51a03SMichal Simek u32 nwcfg; /* 0x4 - Network Config reg */ 11797a51a03SMichal Simek u32 nwsr; /* 0x8 - Network Status reg */ 118185f7d9aSMichal Simek u32 reserved1; 11997a51a03SMichal Simek u32 dmacr; /* 0x10 - DMA Control reg */ 12097a51a03SMichal Simek u32 txsr; /* 0x14 - TX Status reg */ 12197a51a03SMichal Simek u32 rxqbase; /* 0x18 - RX Q Base address reg */ 12297a51a03SMichal Simek u32 txqbase; /* 0x1c - TX Q Base address reg */ 12397a51a03SMichal Simek u32 rxsr; /* 0x20 - RX Status reg */ 124185f7d9aSMichal Simek u32 reserved2[2]; 12597a51a03SMichal Simek u32 idr; /* 0x2c - Interrupt Disable reg */ 126185f7d9aSMichal Simek u32 reserved3; 12797a51a03SMichal Simek u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 128185f7d9aSMichal Simek u32 reserved4[18]; 12997a51a03SMichal Simek u32 hashl; /* 0x80 - Hash Low address reg */ 13097a51a03SMichal Simek u32 hashh; /* 0x84 - Hash High address reg */ 131185f7d9aSMichal Simek #define LADDR_LOW 0 132185f7d9aSMichal Simek #define LADDR_HIGH 1 13397a51a03SMichal Simek u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 13497a51a03SMichal Simek u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 135185f7d9aSMichal Simek u32 reserved6[18]; 1360ebf4041SMichal Simek #define STAT_SIZE 44 1370ebf4041SMichal Simek u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 138603ff008SEdgar E. Iglesias u32 reserved7[164]; 139603ff008SEdgar E. Iglesias u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 140603ff008SEdgar E. Iglesias u32 reserved8[15]; 141603ff008SEdgar E. Iglesias u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 142185f7d9aSMichal Simek }; 143185f7d9aSMichal Simek 144185f7d9aSMichal Simek /* BD descriptors */ 145185f7d9aSMichal Simek struct emac_bd { 146185f7d9aSMichal Simek u32 addr; /* Next descriptor pointer */ 147185f7d9aSMichal Simek u32 status; 148185f7d9aSMichal Simek }; 149185f7d9aSMichal Simek 150eda9d307SSiva Durga Prasad Paladugu #define RX_BUF 32 151a5144237SSrikanth Thokala /* Page table entries are set to 1MB, or multiples of 1MB 152a5144237SSrikanth Thokala * (not < 1MB). driver uses less bd's so use 1MB bdspace. 153a5144237SSrikanth Thokala */ 154a5144237SSrikanth Thokala #define BD_SPACE 0x100000 155a5144237SSrikanth Thokala /* BD separation space */ 156ff475878SMichal Simek #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 157185f7d9aSMichal Simek 158603ff008SEdgar E. Iglesias /* Setup the first free TX descriptor */ 159603ff008SEdgar E. Iglesias #define TX_FREE_DESC 2 160603ff008SEdgar E. Iglesias 161185f7d9aSMichal Simek /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 162185f7d9aSMichal Simek struct zynq_gem_priv { 163a5144237SSrikanth Thokala struct emac_bd *tx_bd; 164a5144237SSrikanth Thokala struct emac_bd *rx_bd; 165a5144237SSrikanth Thokala char *rxbuffers; 166185f7d9aSMichal Simek u32 rxbd_current; 167185f7d9aSMichal Simek u32 rx_first_buf; 168185f7d9aSMichal Simek int phyaddr; 16901fbf310SDavid Andrey u32 emio; 17005868759SMichal Simek int init; 17116ce6de8SMichal Simek phy_interface_t interface; 172185f7d9aSMichal Simek struct phy_device *phydev; 173185f7d9aSMichal Simek struct mii_dev *bus; 174185f7d9aSMichal Simek }; 175185f7d9aSMichal Simek 176185f7d9aSMichal Simek static inline int mdio_wait(struct eth_device *dev) 177185f7d9aSMichal Simek { 178185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 1794c8b7bf4SMichal Simek u32 timeout = 20000; 180185f7d9aSMichal Simek 181185f7d9aSMichal Simek /* Wait till MDIO interface is ready to accept a new transaction. */ 182185f7d9aSMichal Simek while (--timeout) { 183185f7d9aSMichal Simek if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 184185f7d9aSMichal Simek break; 185185f7d9aSMichal Simek WATCHDOG_RESET(); 186185f7d9aSMichal Simek } 187185f7d9aSMichal Simek 188185f7d9aSMichal Simek if (!timeout) { 189185f7d9aSMichal Simek printf("%s: Timeout\n", __func__); 190185f7d9aSMichal Simek return 1; 191185f7d9aSMichal Simek } 192185f7d9aSMichal Simek 193185f7d9aSMichal Simek return 0; 194185f7d9aSMichal Simek } 195185f7d9aSMichal Simek 196185f7d9aSMichal Simek static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, 197185f7d9aSMichal Simek u32 op, u16 *data) 198185f7d9aSMichal Simek { 199185f7d9aSMichal Simek u32 mgtcr; 200185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 201185f7d9aSMichal Simek 202185f7d9aSMichal Simek if (mdio_wait(dev)) 203185f7d9aSMichal Simek return 1; 204185f7d9aSMichal Simek 205185f7d9aSMichal Simek /* Construct mgtcr mask for the operation */ 206185f7d9aSMichal Simek mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 207185f7d9aSMichal Simek (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 208185f7d9aSMichal Simek (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 209185f7d9aSMichal Simek 210185f7d9aSMichal Simek /* Write mgtcr and wait for completion */ 211185f7d9aSMichal Simek writel(mgtcr, ®s->phymntnc); 212185f7d9aSMichal Simek 213185f7d9aSMichal Simek if (mdio_wait(dev)) 214185f7d9aSMichal Simek return 1; 215185f7d9aSMichal Simek 216185f7d9aSMichal Simek if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 217185f7d9aSMichal Simek *data = readl(®s->phymntnc); 218185f7d9aSMichal Simek 219185f7d9aSMichal Simek return 0; 220185f7d9aSMichal Simek } 221185f7d9aSMichal Simek 222185f7d9aSMichal Simek static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) 223185f7d9aSMichal Simek { 224198e9a4fSMichal Simek u32 ret; 225198e9a4fSMichal Simek 226198e9a4fSMichal Simek ret = phy_setup_op(dev, phy_addr, regnum, 227185f7d9aSMichal Simek ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 228198e9a4fSMichal Simek 229198e9a4fSMichal Simek if (!ret) 230198e9a4fSMichal Simek debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 231198e9a4fSMichal Simek phy_addr, regnum, *val); 232198e9a4fSMichal Simek 233198e9a4fSMichal Simek return ret; 234185f7d9aSMichal Simek } 235185f7d9aSMichal Simek 236185f7d9aSMichal Simek static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) 237185f7d9aSMichal Simek { 238198e9a4fSMichal Simek debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 239198e9a4fSMichal Simek regnum, data); 240198e9a4fSMichal Simek 241185f7d9aSMichal Simek return phy_setup_op(dev, phy_addr, regnum, 242185f7d9aSMichal Simek ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 243185f7d9aSMichal Simek } 244185f7d9aSMichal Simek 245f97d7e8bSMichal Simek static void phy_detection(struct eth_device *dev) 246f97d7e8bSMichal Simek { 247f97d7e8bSMichal Simek int i; 248f97d7e8bSMichal Simek u16 phyreg; 249f97d7e8bSMichal Simek struct zynq_gem_priv *priv = dev->priv; 250f97d7e8bSMichal Simek 251f97d7e8bSMichal Simek if (priv->phyaddr != -1) { 252f97d7e8bSMichal Simek phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); 253f97d7e8bSMichal Simek if ((phyreg != 0xFFFF) && 254f97d7e8bSMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 255f97d7e8bSMichal Simek /* Found a valid PHY address */ 256f97d7e8bSMichal Simek debug("Default phy address %d is valid\n", 257f97d7e8bSMichal Simek priv->phyaddr); 258f97d7e8bSMichal Simek return; 259f97d7e8bSMichal Simek } else { 260f97d7e8bSMichal Simek debug("PHY address is not setup correctly %d\n", 261f97d7e8bSMichal Simek priv->phyaddr); 262f97d7e8bSMichal Simek priv->phyaddr = -1; 263f97d7e8bSMichal Simek } 264f97d7e8bSMichal Simek } 265f97d7e8bSMichal Simek 266f97d7e8bSMichal Simek debug("detecting phy address\n"); 267f97d7e8bSMichal Simek if (priv->phyaddr == -1) { 268f97d7e8bSMichal Simek /* detect the PHY address */ 269f97d7e8bSMichal Simek for (i = 31; i >= 0; i--) { 270f97d7e8bSMichal Simek phyread(dev, i, PHY_DETECT_REG, &phyreg); 271f97d7e8bSMichal Simek if ((phyreg != 0xFFFF) && 272f97d7e8bSMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 273f97d7e8bSMichal Simek /* Found a valid PHY address */ 274f97d7e8bSMichal Simek priv->phyaddr = i; 275f97d7e8bSMichal Simek debug("Found valid phy address, %d\n", i); 276f97d7e8bSMichal Simek return; 277f97d7e8bSMichal Simek } 278f97d7e8bSMichal Simek } 279f97d7e8bSMichal Simek } 280f97d7e8bSMichal Simek printf("PHY is not detected\n"); 281f97d7e8bSMichal Simek } 282f97d7e8bSMichal Simek 283185f7d9aSMichal Simek static int zynq_gem_setup_mac(struct eth_device *dev) 284185f7d9aSMichal Simek { 285185f7d9aSMichal Simek u32 i, macaddrlow, macaddrhigh; 286185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 287185f7d9aSMichal Simek 288185f7d9aSMichal Simek /* Set the MAC bits [31:0] in BOT */ 289185f7d9aSMichal Simek macaddrlow = dev->enetaddr[0]; 290185f7d9aSMichal Simek macaddrlow |= dev->enetaddr[1] << 8; 291185f7d9aSMichal Simek macaddrlow |= dev->enetaddr[2] << 16; 292185f7d9aSMichal Simek macaddrlow |= dev->enetaddr[3] << 24; 293185f7d9aSMichal Simek 294185f7d9aSMichal Simek /* Set MAC bits [47:32] in TOP */ 295185f7d9aSMichal Simek macaddrhigh = dev->enetaddr[4]; 296185f7d9aSMichal Simek macaddrhigh |= dev->enetaddr[5] << 8; 297185f7d9aSMichal Simek 298185f7d9aSMichal Simek for (i = 0; i < 4; i++) { 299185f7d9aSMichal Simek writel(0, ®s->laddr[i][LADDR_LOW]); 300185f7d9aSMichal Simek writel(0, ®s->laddr[i][LADDR_HIGH]); 301185f7d9aSMichal Simek /* Do not use MATCHx register */ 302185f7d9aSMichal Simek writel(0, ®s->match[i]); 303185f7d9aSMichal Simek } 304185f7d9aSMichal Simek 305185f7d9aSMichal Simek writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 306185f7d9aSMichal Simek writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 307185f7d9aSMichal Simek 308185f7d9aSMichal Simek return 0; 309185f7d9aSMichal Simek } 310185f7d9aSMichal Simek 311185f7d9aSMichal Simek static int zynq_gem_init(struct eth_device *dev, bd_t * bis) 312185f7d9aSMichal Simek { 31397598fcfSSoren Brinkmann u32 i; 31497598fcfSSoren Brinkmann unsigned long clk_rate = 0; 315185f7d9aSMichal Simek struct phy_device *phydev; 316185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 317185f7d9aSMichal Simek struct zynq_gem_priv *priv = dev->priv; 318603ff008SEdgar E. Iglesias struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 319603ff008SEdgar E. Iglesias struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 320185f7d9aSMichal Simek const u32 supported = SUPPORTED_10baseT_Half | 321185f7d9aSMichal Simek SUPPORTED_10baseT_Full | 322185f7d9aSMichal Simek SUPPORTED_100baseT_Half | 323185f7d9aSMichal Simek SUPPORTED_100baseT_Full | 324185f7d9aSMichal Simek SUPPORTED_1000baseT_Half | 325185f7d9aSMichal Simek SUPPORTED_1000baseT_Full; 326185f7d9aSMichal Simek 32705868759SMichal Simek if (!priv->init) { 328185f7d9aSMichal Simek /* Disable all interrupts */ 329185f7d9aSMichal Simek writel(0xFFFFFFFF, ®s->idr); 330185f7d9aSMichal Simek 331185f7d9aSMichal Simek /* Disable the receiver & transmitter */ 332185f7d9aSMichal Simek writel(0, ®s->nwctrl); 333185f7d9aSMichal Simek writel(0, ®s->txsr); 334185f7d9aSMichal Simek writel(0, ®s->rxsr); 335185f7d9aSMichal Simek writel(0, ®s->phymntnc); 336185f7d9aSMichal Simek 33705868759SMichal Simek /* Clear the Hash registers for the mac address 33805868759SMichal Simek * pointed by AddressPtr 33905868759SMichal Simek */ 340185f7d9aSMichal Simek writel(0x0, ®s->hashl); 341185f7d9aSMichal Simek /* Write bits [63:32] in TOP */ 342185f7d9aSMichal Simek writel(0x0, ®s->hashh); 343185f7d9aSMichal Simek 344185f7d9aSMichal Simek /* Clear all counters */ 3450ebf4041SMichal Simek for (i = 0; i < STAT_SIZE; i++) 346185f7d9aSMichal Simek readl(®s->stat[i]); 347185f7d9aSMichal Simek 348185f7d9aSMichal Simek /* Setup RxBD space */ 349a5144237SSrikanth Thokala memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 350185f7d9aSMichal Simek 351185f7d9aSMichal Simek for (i = 0; i < RX_BUF; i++) { 352185f7d9aSMichal Simek priv->rx_bd[i].status = 0xF0000000; 35305868759SMichal Simek priv->rx_bd[i].addr = 3545b47d407SPrabhakar Kushwaha ((ulong)(priv->rxbuffers) + 355185f7d9aSMichal Simek (i * PKTSIZE_ALIGN)); 356185f7d9aSMichal Simek } 357185f7d9aSMichal Simek /* WRAP bit to last BD */ 358185f7d9aSMichal Simek priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 359185f7d9aSMichal Simek /* Write RxBDs to IP */ 3605b47d407SPrabhakar Kushwaha writel((ulong)priv->rx_bd, ®s->rxqbase); 361185f7d9aSMichal Simek 362185f7d9aSMichal Simek /* Setup for DMA Configuration register */ 363185f7d9aSMichal Simek writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 364185f7d9aSMichal Simek 365185f7d9aSMichal Simek /* Setup for Network Control register, MDIO, Rx and Tx enable */ 36680243528SMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 367185f7d9aSMichal Simek 368603ff008SEdgar E. Iglesias /* Disable the second priority queue */ 369603ff008SEdgar E. Iglesias dummy_tx_bd->addr = 0; 370603ff008SEdgar E. Iglesias dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 371603ff008SEdgar E. Iglesias ZYNQ_GEM_TXBUF_LAST_MASK| 372603ff008SEdgar E. Iglesias ZYNQ_GEM_TXBUF_USED_MASK; 373603ff008SEdgar E. Iglesias 374603ff008SEdgar E. Iglesias dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 375603ff008SEdgar E. Iglesias ZYNQ_GEM_RXBUF_NEW_MASK; 376603ff008SEdgar E. Iglesias dummy_rx_bd->status = 0; 377603ff008SEdgar E. Iglesias flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + 378603ff008SEdgar E. Iglesias sizeof(dummy_tx_bd)); 379603ff008SEdgar E. Iglesias flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + 380603ff008SEdgar E. Iglesias sizeof(dummy_rx_bd)); 381603ff008SEdgar E. Iglesias 382603ff008SEdgar E. Iglesias writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 383603ff008SEdgar E. Iglesias writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 384603ff008SEdgar E. Iglesias 38505868759SMichal Simek priv->init++; 38605868759SMichal Simek } 38705868759SMichal Simek 388f97d7e8bSMichal Simek phy_detection(dev); 389f97d7e8bSMichal Simek 390185f7d9aSMichal Simek /* interface - look at tsec */ 391c1a9fa4bSMichal Simek phydev = phy_connect(priv->bus, priv->phyaddr, dev, 39216ce6de8SMichal Simek priv->interface); 393185f7d9aSMichal Simek 39480243528SMichal Simek phydev->supported = supported | ADVERTISED_Pause | 39580243528SMichal Simek ADVERTISED_Asym_Pause; 396185f7d9aSMichal Simek phydev->advertising = phydev->supported; 397185f7d9aSMichal Simek priv->phydev = phydev; 398185f7d9aSMichal Simek phy_config(phydev); 399185f7d9aSMichal Simek phy_startup(phydev); 400185f7d9aSMichal Simek 4014ed4aa20SMichal Simek if (!phydev->link) { 4024ed4aa20SMichal Simek printf("%s: No link.\n", phydev->dev->name); 4034ed4aa20SMichal Simek return -1; 4044ed4aa20SMichal Simek } 4054ed4aa20SMichal Simek 40680243528SMichal Simek switch (phydev->speed) { 40780243528SMichal Simek case SPEED_1000: 40880243528SMichal Simek writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 40980243528SMichal Simek ®s->nwcfg); 41097598fcfSSoren Brinkmann clk_rate = ZYNQ_GEM_FREQUENCY_1000; 41180243528SMichal Simek break; 41280243528SMichal Simek case SPEED_100: 41380243528SMichal Simek clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, 41480243528SMichal Simek ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); 41597598fcfSSoren Brinkmann clk_rate = ZYNQ_GEM_FREQUENCY_100; 41680243528SMichal Simek break; 41780243528SMichal Simek case SPEED_10: 41897598fcfSSoren Brinkmann clk_rate = ZYNQ_GEM_FREQUENCY_10; 41980243528SMichal Simek break; 42080243528SMichal Simek } 42101fbf310SDavid Andrey 42201fbf310SDavid Andrey /* Change the rclk and clk only not using EMIO interface */ 42301fbf310SDavid Andrey if (!priv->emio) 42401fbf310SDavid Andrey zynq_slcr_gem_clk_setup(dev->iobase != 42597598fcfSSoren Brinkmann ZYNQ_GEM_BASEADDR0, clk_rate); 42680243528SMichal Simek 42780243528SMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 42880243528SMichal Simek ZYNQ_GEM_NWCTRL_TXEN_MASK); 42980243528SMichal Simek 430185f7d9aSMichal Simek return 0; 431185f7d9aSMichal Simek } 432185f7d9aSMichal Simek 433*e4d2318aSMichal Simek static int wait_for_bit(const char *func, u32 *reg, const u32 mask, 434*e4d2318aSMichal Simek bool set, unsigned int timeout) 435*e4d2318aSMichal Simek { 436*e4d2318aSMichal Simek u32 val; 437*e4d2318aSMichal Simek unsigned long start = get_timer(0); 438*e4d2318aSMichal Simek 439*e4d2318aSMichal Simek while (1) { 440*e4d2318aSMichal Simek val = readl(reg); 441*e4d2318aSMichal Simek 442*e4d2318aSMichal Simek if (!set) 443*e4d2318aSMichal Simek val = ~val; 444*e4d2318aSMichal Simek 445*e4d2318aSMichal Simek if ((val & mask) == mask) 446*e4d2318aSMichal Simek return 0; 447*e4d2318aSMichal Simek 448*e4d2318aSMichal Simek if (get_timer(start) > timeout) 449*e4d2318aSMichal Simek break; 450*e4d2318aSMichal Simek 451*e4d2318aSMichal Simek udelay(1); 452*e4d2318aSMichal Simek } 453*e4d2318aSMichal Simek 454*e4d2318aSMichal Simek debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", 455*e4d2318aSMichal Simek func, reg, mask, set); 456*e4d2318aSMichal Simek 457*e4d2318aSMichal Simek return -ETIMEDOUT; 458*e4d2318aSMichal Simek } 459*e4d2318aSMichal Simek 460185f7d9aSMichal Simek static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) 461185f7d9aSMichal Simek { 462a5144237SSrikanth Thokala u32 addr, size; 463185f7d9aSMichal Simek struct zynq_gem_priv *priv = dev->priv; 464185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 46523a598f7SMichal Simek struct emac_bd *current_bd = &priv->tx_bd[1]; 466185f7d9aSMichal Simek 467185f7d9aSMichal Simek /* Setup Tx BD */ 468a5144237SSrikanth Thokala memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 469185f7d9aSMichal Simek 4705b47d407SPrabhakar Kushwaha priv->tx_bd->addr = (ulong)ptr; 471a5144237SSrikanth Thokala priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 47223a598f7SMichal Simek ZYNQ_GEM_TXBUF_LAST_MASK; 47323a598f7SMichal Simek /* Dummy descriptor to mark it as the last in descriptor chain */ 47423a598f7SMichal Simek current_bd->addr = 0x0; 47523a598f7SMichal Simek current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 476e65d33cfSMichal Simek ZYNQ_GEM_TXBUF_LAST_MASK| 47723a598f7SMichal Simek ZYNQ_GEM_TXBUF_USED_MASK; 478a5144237SSrikanth Thokala 47945c07741SMichal Simek /* setup BD */ 48045c07741SMichal Simek writel((ulong)priv->tx_bd, ®s->txqbase); 48145c07741SMichal Simek 4825b47d407SPrabhakar Kushwaha addr = (ulong) ptr; 483a5144237SSrikanth Thokala addr &= ~(ARCH_DMA_MINALIGN - 1); 484a5144237SSrikanth Thokala size = roundup(len, ARCH_DMA_MINALIGN); 485a5144237SSrikanth Thokala flush_dcache_range(addr, addr + size); 48696f4f149SSiva Durga Prasad Paladugu 4875b47d407SPrabhakar Kushwaha addr = (ulong)priv->rxbuffers; 48896f4f149SSiva Durga Prasad Paladugu addr &= ~(ARCH_DMA_MINALIGN - 1); 48996f4f149SSiva Durga Prasad Paladugu size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 49096f4f149SSiva Durga Prasad Paladugu flush_dcache_range(addr, addr + size); 491a5144237SSrikanth Thokala barrier(); 492185f7d9aSMichal Simek 493185f7d9aSMichal Simek /* Start transmit */ 494185f7d9aSMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 495185f7d9aSMichal Simek 496a5144237SSrikanth Thokala /* Read TX BD status */ 497a5144237SSrikanth Thokala if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 498a5144237SSrikanth Thokala printf("TX buffers exhausted in mid frame\n"); 499185f7d9aSMichal Simek 500*e4d2318aSMichal Simek return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, 501*e4d2318aSMichal Simek true, 20000); 502185f7d9aSMichal Simek } 503185f7d9aSMichal Simek 504185f7d9aSMichal Simek /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 505185f7d9aSMichal Simek static int zynq_gem_recv(struct eth_device *dev) 506185f7d9aSMichal Simek { 507185f7d9aSMichal Simek int frame_len; 508185f7d9aSMichal Simek struct zynq_gem_priv *priv = dev->priv; 509185f7d9aSMichal Simek struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 510185f7d9aSMichal Simek struct emac_bd *first_bd; 511185f7d9aSMichal Simek 512185f7d9aSMichal Simek if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 513185f7d9aSMichal Simek return 0; 514185f7d9aSMichal Simek 515185f7d9aSMichal Simek if (!(current_bd->status & 516185f7d9aSMichal Simek (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 517185f7d9aSMichal Simek printf("GEM: SOF or EOF not set for last buffer received!\n"); 518185f7d9aSMichal Simek return 0; 519185f7d9aSMichal Simek } 520185f7d9aSMichal Simek 521185f7d9aSMichal Simek frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 522185f7d9aSMichal Simek if (frame_len) { 523a5144237SSrikanth Thokala u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 524a5144237SSrikanth Thokala addr &= ~(ARCH_DMA_MINALIGN - 1); 525a5144237SSrikanth Thokala 5265b47d407SPrabhakar Kushwaha net_process_received_packet((u8 *)(ulong)addr, frame_len); 527185f7d9aSMichal Simek 528185f7d9aSMichal Simek if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 529185f7d9aSMichal Simek priv->rx_first_buf = priv->rxbd_current; 530185f7d9aSMichal Simek else { 531185f7d9aSMichal Simek current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 532185f7d9aSMichal Simek current_bd->status = 0xF0000000; /* FIXME */ 533185f7d9aSMichal Simek } 534185f7d9aSMichal Simek 535185f7d9aSMichal Simek if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 536185f7d9aSMichal Simek first_bd = &priv->rx_bd[priv->rx_first_buf]; 537185f7d9aSMichal Simek first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 538185f7d9aSMichal Simek first_bd->status = 0xF0000000; 539185f7d9aSMichal Simek } 540185f7d9aSMichal Simek 541185f7d9aSMichal Simek if ((++priv->rxbd_current) >= RX_BUF) 542185f7d9aSMichal Simek priv->rxbd_current = 0; 543185f7d9aSMichal Simek } 544185f7d9aSMichal Simek 5453b90d0afSMichal Simek return frame_len; 546185f7d9aSMichal Simek } 547185f7d9aSMichal Simek 548185f7d9aSMichal Simek static void zynq_gem_halt(struct eth_device *dev) 549185f7d9aSMichal Simek { 550185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 551185f7d9aSMichal Simek 55280243528SMichal Simek clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 55380243528SMichal Simek ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 554185f7d9aSMichal Simek } 555185f7d9aSMichal Simek 556185f7d9aSMichal Simek static int zynq_gem_miiphyread(const char *devname, uchar addr, 557185f7d9aSMichal Simek uchar reg, ushort *val) 558185f7d9aSMichal Simek { 559185f7d9aSMichal Simek struct eth_device *dev = eth_get_dev(); 560185f7d9aSMichal Simek int ret; 561185f7d9aSMichal Simek 562185f7d9aSMichal Simek ret = phyread(dev, addr, reg, val); 563185f7d9aSMichal Simek debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); 564185f7d9aSMichal Simek return ret; 565185f7d9aSMichal Simek } 566185f7d9aSMichal Simek 567185f7d9aSMichal Simek static int zynq_gem_miiphy_write(const char *devname, uchar addr, 568185f7d9aSMichal Simek uchar reg, ushort val) 569185f7d9aSMichal Simek { 570185f7d9aSMichal Simek struct eth_device *dev = eth_get_dev(); 571185f7d9aSMichal Simek 572185f7d9aSMichal Simek debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); 573185f7d9aSMichal Simek return phywrite(dev, addr, reg, val); 574185f7d9aSMichal Simek } 575185f7d9aSMichal Simek 57658405378SMichal Simek int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, 57758405378SMichal Simek int phy_addr, u32 emio) 578185f7d9aSMichal Simek { 579185f7d9aSMichal Simek struct eth_device *dev; 580185f7d9aSMichal Simek struct zynq_gem_priv *priv; 581a5144237SSrikanth Thokala void *bd_space; 582185f7d9aSMichal Simek 583185f7d9aSMichal Simek dev = calloc(1, sizeof(*dev)); 584185f7d9aSMichal Simek if (dev == NULL) 585185f7d9aSMichal Simek return -1; 586185f7d9aSMichal Simek 587185f7d9aSMichal Simek dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); 588185f7d9aSMichal Simek if (dev->priv == NULL) { 589185f7d9aSMichal Simek free(dev); 590185f7d9aSMichal Simek return -1; 591185f7d9aSMichal Simek } 592185f7d9aSMichal Simek priv = dev->priv; 593185f7d9aSMichal Simek 594a5144237SSrikanth Thokala /* Align rxbuffers to ARCH_DMA_MINALIGN */ 595a5144237SSrikanth Thokala priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 596a5144237SSrikanth Thokala memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 597a5144237SSrikanth Thokala 59896f4f149SSiva Durga Prasad Paladugu /* Align bd_space to MMU_SECTION_SHIFT */ 599a5144237SSrikanth Thokala bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 6009ce1edc8SMichal Simek mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 6019ce1edc8SMichal Simek BD_SPACE, DCACHE_OFF); 602a5144237SSrikanth Thokala 603a5144237SSrikanth Thokala /* Initialize the bd spaces for tx and rx bd's */ 604a5144237SSrikanth Thokala priv->tx_bd = (struct emac_bd *)bd_space; 6055b47d407SPrabhakar Kushwaha priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 606a5144237SSrikanth Thokala 607117cd4ccSDavid Andrey priv->phyaddr = phy_addr; 60801fbf310SDavid Andrey priv->emio = emio; 609185f7d9aSMichal Simek 61016ce6de8SMichal Simek #ifndef CONFIG_ZYNQ_GEM_INTERFACE 61116ce6de8SMichal Simek priv->interface = PHY_INTERFACE_MODE_MII; 61216ce6de8SMichal Simek #else 61316ce6de8SMichal Simek priv->interface = CONFIG_ZYNQ_GEM_INTERFACE; 61416ce6de8SMichal Simek #endif 61516ce6de8SMichal Simek 61658405378SMichal Simek sprintf(dev->name, "Gem.%lx", base_addr); 617185f7d9aSMichal Simek 618185f7d9aSMichal Simek dev->iobase = base_addr; 619185f7d9aSMichal Simek 620185f7d9aSMichal Simek dev->init = zynq_gem_init; 621185f7d9aSMichal Simek dev->halt = zynq_gem_halt; 622185f7d9aSMichal Simek dev->send = zynq_gem_send; 623185f7d9aSMichal Simek dev->recv = zynq_gem_recv; 624185f7d9aSMichal Simek dev->write_hwaddr = zynq_gem_setup_mac; 625185f7d9aSMichal Simek 626185f7d9aSMichal Simek eth_register(dev); 627185f7d9aSMichal Simek 628185f7d9aSMichal Simek miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); 629185f7d9aSMichal Simek priv->bus = miiphy_get_dev_by_name(dev->name); 630185f7d9aSMichal Simek 631185f7d9aSMichal Simek return 1; 632185f7d9aSMichal Simek } 633f88a6869SMichal Simek 6340f925822SMasahiro Yamada #if CONFIG_IS_ENABLED(OF_CONTROL) 635f88a6869SMichal Simek int zynq_gem_of_init(const void *blob) 636f88a6869SMichal Simek { 637f88a6869SMichal Simek int offset = 0; 638f88a6869SMichal Simek u32 ret = 0; 639f88a6869SMichal Simek u32 reg, phy_reg; 640f88a6869SMichal Simek 641f88a6869SMichal Simek debug("ZYNQ GEM: Initialization\n"); 642f88a6869SMichal Simek 643f88a6869SMichal Simek do { 644f88a6869SMichal Simek offset = fdt_node_offset_by_compatible(blob, offset, 645f88a6869SMichal Simek "xlnx,ps7-ethernet-1.00.a"); 646f88a6869SMichal Simek if (offset != -1) { 647f88a6869SMichal Simek reg = fdtdec_get_addr(blob, offset, "reg"); 648f88a6869SMichal Simek if (reg != FDT_ADDR_T_NONE) { 649f88a6869SMichal Simek offset = fdtdec_lookup_phandle(blob, offset, 650f88a6869SMichal Simek "phy-handle"); 651f88a6869SMichal Simek if (offset != -1) 652f88a6869SMichal Simek phy_reg = fdtdec_get_addr(blob, offset, 653f88a6869SMichal Simek "reg"); 654f88a6869SMichal Simek else 655f88a6869SMichal Simek phy_reg = 0; 656f88a6869SMichal Simek 657f88a6869SMichal Simek debug("ZYNQ GEM: addr %x, phyaddr %x\n", 658f88a6869SMichal Simek reg, phy_reg); 659f88a6869SMichal Simek 660f88a6869SMichal Simek ret |= zynq_gem_initialize(NULL, reg, 661f88a6869SMichal Simek phy_reg, 0); 662f88a6869SMichal Simek 663f88a6869SMichal Simek } else { 664f88a6869SMichal Simek debug("ZYNQ GEM: Can't get base address\n"); 665f88a6869SMichal Simek return -1; 666f88a6869SMichal Simek } 667f88a6869SMichal Simek } 668f88a6869SMichal Simek } while (offset != -1); 669f88a6869SMichal Simek 670f88a6869SMichal Simek return ret; 671f88a6869SMichal Simek } 672f88a6869SMichal Simek #endif 673