1185f7d9aSMichal Simek /* 2185f7d9aSMichal Simek * (C) Copyright 2011 Michal Simek 3185f7d9aSMichal Simek * 4185f7d9aSMichal Simek * Michal SIMEK <monstr@monstr.eu> 5185f7d9aSMichal Simek * 6185f7d9aSMichal Simek * Based on Xilinx gmac driver: 7185f7d9aSMichal Simek * (C) Copyright 2011 Xilinx 8185f7d9aSMichal Simek * 91a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 10185f7d9aSMichal Simek */ 11185f7d9aSMichal Simek 12185f7d9aSMichal Simek #include <common.h> 13185f7d9aSMichal Simek #include <net.h> 14185f7d9aSMichal Simek #include <config.h> 15185f7d9aSMichal Simek #include <malloc.h> 16185f7d9aSMichal Simek #include <asm/io.h> 17185f7d9aSMichal Simek #include <phy.h> 18185f7d9aSMichal Simek #include <miiphy.h> 19185f7d9aSMichal Simek #include <watchdog.h> 2001fbf310SDavid Andrey #include <asm/arch/hardware.h> 2180243528SMichal Simek #include <asm/arch/sys_proto.h> 22185f7d9aSMichal Simek 23185f7d9aSMichal Simek #if !defined(CONFIG_PHYLIB) 24185f7d9aSMichal Simek # error XILINX_GEM_ETHERNET requires PHYLIB 25185f7d9aSMichal Simek #endif 26185f7d9aSMichal Simek 27185f7d9aSMichal Simek /* Bit/mask specification */ 28185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 29185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 30185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 31185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 32185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 33185f7d9aSMichal Simek 34185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 35185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 36185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 37185f7d9aSMichal Simek 38185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 39185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 40185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 41185f7d9aSMichal Simek 42185f7d9aSMichal Simek /* Wrap bit, last descriptor */ 43185f7d9aSMichal Simek #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 44185f7d9aSMichal Simek #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 45185f7d9aSMichal Simek 46185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 47185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 48185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 49185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 50185f7d9aSMichal Simek 5180243528SMichal Simek #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 5280243528SMichal Simek #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 5380243528SMichal Simek #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 5480243528SMichal Simek #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 55185f7d9aSMichal Simek #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ 5680243528SMichal Simek #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ 57185f7d9aSMichal Simek 5880243528SMichal Simek #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \ 59185f7d9aSMichal Simek ZYNQ_GEM_NWCFG_FSREM | \ 60185f7d9aSMichal Simek ZYNQ_GEM_NWCFG_MDCCLKDIV) 61185f7d9aSMichal Simek 62185f7d9aSMichal Simek #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 63185f7d9aSMichal Simek 64185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 65185f7d9aSMichal Simek /* Use full configured addressable space (8 Kb) */ 66185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 67185f7d9aSMichal Simek /* Use full configured addressable space (4 Kb) */ 68185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 69185f7d9aSMichal Simek /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 70185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 71185f7d9aSMichal Simek 72185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 73185f7d9aSMichal Simek ZYNQ_GEM_DMACR_RXSIZE | \ 74185f7d9aSMichal Simek ZYNQ_GEM_DMACR_TXSIZE | \ 75185f7d9aSMichal Simek ZYNQ_GEM_DMACR_RXBUF) 76185f7d9aSMichal Simek 77f97d7e8bSMichal Simek /* Use MII register 1 (MII status register) to detect PHY */ 78f97d7e8bSMichal Simek #define PHY_DETECT_REG 1 79f97d7e8bSMichal Simek 80f97d7e8bSMichal Simek /* Mask used to verify certain PHY features (or register contents) 81f97d7e8bSMichal Simek * in the register above: 82f97d7e8bSMichal Simek * 0x1000: 10Mbps full duplex support 83f97d7e8bSMichal Simek * 0x0800: 10Mbps half duplex support 84f97d7e8bSMichal Simek * 0x0008: Auto-negotiation support 85f97d7e8bSMichal Simek */ 86f97d7e8bSMichal Simek #define PHY_DETECT_MASK 0x1808 87f97d7e8bSMichal Simek 88*a5144237SSrikanth Thokala /* TX BD status masks */ 89*a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 90*a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 91*a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 92*a5144237SSrikanth Thokala 93185f7d9aSMichal Simek /* Device registers */ 94185f7d9aSMichal Simek struct zynq_gem_regs { 95185f7d9aSMichal Simek u32 nwctrl; /* Network Control reg */ 96185f7d9aSMichal Simek u32 nwcfg; /* Network Config reg */ 97185f7d9aSMichal Simek u32 nwsr; /* Network Status reg */ 98185f7d9aSMichal Simek u32 reserved1; 99185f7d9aSMichal Simek u32 dmacr; /* DMA Control reg */ 100185f7d9aSMichal Simek u32 txsr; /* TX Status reg */ 101185f7d9aSMichal Simek u32 rxqbase; /* RX Q Base address reg */ 102185f7d9aSMichal Simek u32 txqbase; /* TX Q Base address reg */ 103185f7d9aSMichal Simek u32 rxsr; /* RX Status reg */ 104185f7d9aSMichal Simek u32 reserved2[2]; 105185f7d9aSMichal Simek u32 idr; /* Interrupt Disable reg */ 106185f7d9aSMichal Simek u32 reserved3; 107185f7d9aSMichal Simek u32 phymntnc; /* Phy Maintaince reg */ 108185f7d9aSMichal Simek u32 reserved4[18]; 109185f7d9aSMichal Simek u32 hashl; /* Hash Low address reg */ 110185f7d9aSMichal Simek u32 hashh; /* Hash High address reg */ 111185f7d9aSMichal Simek #define LADDR_LOW 0 112185f7d9aSMichal Simek #define LADDR_HIGH 1 113185f7d9aSMichal Simek u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */ 114185f7d9aSMichal Simek u32 match[4]; /* Type ID1 Match reg */ 115185f7d9aSMichal Simek u32 reserved6[18]; 116185f7d9aSMichal Simek u32 stat[44]; /* Octects transmitted Low reg - stat start */ 117185f7d9aSMichal Simek }; 118185f7d9aSMichal Simek 119185f7d9aSMichal Simek /* BD descriptors */ 120185f7d9aSMichal Simek struct emac_bd { 121185f7d9aSMichal Simek u32 addr; /* Next descriptor pointer */ 122185f7d9aSMichal Simek u32 status; 123185f7d9aSMichal Simek }; 124185f7d9aSMichal Simek 125185f7d9aSMichal Simek #define RX_BUF 3 126*a5144237SSrikanth Thokala /* Page table entries are set to 1MB, or multiples of 1MB 127*a5144237SSrikanth Thokala * (not < 1MB). driver uses less bd's so use 1MB bdspace. 128*a5144237SSrikanth Thokala */ 129*a5144237SSrikanth Thokala #define BD_SPACE 0x100000 130*a5144237SSrikanth Thokala /* BD separation space */ 131*a5144237SSrikanth Thokala #define BD_SEPRN_SPACE 64 132185f7d9aSMichal Simek 133185f7d9aSMichal Simek /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 134185f7d9aSMichal Simek struct zynq_gem_priv { 135*a5144237SSrikanth Thokala struct emac_bd *tx_bd; 136*a5144237SSrikanth Thokala struct emac_bd *rx_bd; 137*a5144237SSrikanth Thokala char *rxbuffers; 138185f7d9aSMichal Simek u32 rxbd_current; 139185f7d9aSMichal Simek u32 rx_first_buf; 140185f7d9aSMichal Simek int phyaddr; 14101fbf310SDavid Andrey u32 emio; 14205868759SMichal Simek int init; 143185f7d9aSMichal Simek struct phy_device *phydev; 144185f7d9aSMichal Simek struct mii_dev *bus; 145185f7d9aSMichal Simek }; 146185f7d9aSMichal Simek 147185f7d9aSMichal Simek static inline int mdio_wait(struct eth_device *dev) 148185f7d9aSMichal Simek { 149185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 150185f7d9aSMichal Simek u32 timeout = 200; 151185f7d9aSMichal Simek 152185f7d9aSMichal Simek /* Wait till MDIO interface is ready to accept a new transaction. */ 153185f7d9aSMichal Simek while (--timeout) { 154185f7d9aSMichal Simek if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 155185f7d9aSMichal Simek break; 156185f7d9aSMichal Simek WATCHDOG_RESET(); 157185f7d9aSMichal Simek } 158185f7d9aSMichal Simek 159185f7d9aSMichal Simek if (!timeout) { 160185f7d9aSMichal Simek printf("%s: Timeout\n", __func__); 161185f7d9aSMichal Simek return 1; 162185f7d9aSMichal Simek } 163185f7d9aSMichal Simek 164185f7d9aSMichal Simek return 0; 165185f7d9aSMichal Simek } 166185f7d9aSMichal Simek 167185f7d9aSMichal Simek static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, 168185f7d9aSMichal Simek u32 op, u16 *data) 169185f7d9aSMichal Simek { 170185f7d9aSMichal Simek u32 mgtcr; 171185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 172185f7d9aSMichal Simek 173185f7d9aSMichal Simek if (mdio_wait(dev)) 174185f7d9aSMichal Simek return 1; 175185f7d9aSMichal Simek 176185f7d9aSMichal Simek /* Construct mgtcr mask for the operation */ 177185f7d9aSMichal Simek mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 178185f7d9aSMichal Simek (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 179185f7d9aSMichal Simek (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 180185f7d9aSMichal Simek 181185f7d9aSMichal Simek /* Write mgtcr and wait for completion */ 182185f7d9aSMichal Simek writel(mgtcr, ®s->phymntnc); 183185f7d9aSMichal Simek 184185f7d9aSMichal Simek if (mdio_wait(dev)) 185185f7d9aSMichal Simek return 1; 186185f7d9aSMichal Simek 187185f7d9aSMichal Simek if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 188185f7d9aSMichal Simek *data = readl(®s->phymntnc); 189185f7d9aSMichal Simek 190185f7d9aSMichal Simek return 0; 191185f7d9aSMichal Simek } 192185f7d9aSMichal Simek 193185f7d9aSMichal Simek static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) 194185f7d9aSMichal Simek { 195185f7d9aSMichal Simek return phy_setup_op(dev, phy_addr, regnum, 196185f7d9aSMichal Simek ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 197185f7d9aSMichal Simek } 198185f7d9aSMichal Simek 199185f7d9aSMichal Simek static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) 200185f7d9aSMichal Simek { 201185f7d9aSMichal Simek return phy_setup_op(dev, phy_addr, regnum, 202185f7d9aSMichal Simek ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 203185f7d9aSMichal Simek } 204185f7d9aSMichal Simek 205f97d7e8bSMichal Simek static void phy_detection(struct eth_device *dev) 206f97d7e8bSMichal Simek { 207f97d7e8bSMichal Simek int i; 208f97d7e8bSMichal Simek u16 phyreg; 209f97d7e8bSMichal Simek struct zynq_gem_priv *priv = dev->priv; 210f97d7e8bSMichal Simek 211f97d7e8bSMichal Simek if (priv->phyaddr != -1) { 212f97d7e8bSMichal Simek phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); 213f97d7e8bSMichal Simek if ((phyreg != 0xFFFF) && 214f97d7e8bSMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 215f97d7e8bSMichal Simek /* Found a valid PHY address */ 216f97d7e8bSMichal Simek debug("Default phy address %d is valid\n", 217f97d7e8bSMichal Simek priv->phyaddr); 218f97d7e8bSMichal Simek return; 219f97d7e8bSMichal Simek } else { 220f97d7e8bSMichal Simek debug("PHY address is not setup correctly %d\n", 221f97d7e8bSMichal Simek priv->phyaddr); 222f97d7e8bSMichal Simek priv->phyaddr = -1; 223f97d7e8bSMichal Simek } 224f97d7e8bSMichal Simek } 225f97d7e8bSMichal Simek 226f97d7e8bSMichal Simek debug("detecting phy address\n"); 227f97d7e8bSMichal Simek if (priv->phyaddr == -1) { 228f97d7e8bSMichal Simek /* detect the PHY address */ 229f97d7e8bSMichal Simek for (i = 31; i >= 0; i--) { 230f97d7e8bSMichal Simek phyread(dev, i, PHY_DETECT_REG, &phyreg); 231f97d7e8bSMichal Simek if ((phyreg != 0xFFFF) && 232f97d7e8bSMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 233f97d7e8bSMichal Simek /* Found a valid PHY address */ 234f97d7e8bSMichal Simek priv->phyaddr = i; 235f97d7e8bSMichal Simek debug("Found valid phy address, %d\n", i); 236f97d7e8bSMichal Simek return; 237f97d7e8bSMichal Simek } 238f97d7e8bSMichal Simek } 239f97d7e8bSMichal Simek } 240f97d7e8bSMichal Simek printf("PHY is not detected\n"); 241f97d7e8bSMichal Simek } 242f97d7e8bSMichal Simek 243185f7d9aSMichal Simek static int zynq_gem_setup_mac(struct eth_device *dev) 244185f7d9aSMichal Simek { 245185f7d9aSMichal Simek u32 i, macaddrlow, macaddrhigh; 246185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 247185f7d9aSMichal Simek 248185f7d9aSMichal Simek /* Set the MAC bits [31:0] in BOT */ 249185f7d9aSMichal Simek macaddrlow = dev->enetaddr[0]; 250185f7d9aSMichal Simek macaddrlow |= dev->enetaddr[1] << 8; 251185f7d9aSMichal Simek macaddrlow |= dev->enetaddr[2] << 16; 252185f7d9aSMichal Simek macaddrlow |= dev->enetaddr[3] << 24; 253185f7d9aSMichal Simek 254185f7d9aSMichal Simek /* Set MAC bits [47:32] in TOP */ 255185f7d9aSMichal Simek macaddrhigh = dev->enetaddr[4]; 256185f7d9aSMichal Simek macaddrhigh |= dev->enetaddr[5] << 8; 257185f7d9aSMichal Simek 258185f7d9aSMichal Simek for (i = 0; i < 4; i++) { 259185f7d9aSMichal Simek writel(0, ®s->laddr[i][LADDR_LOW]); 260185f7d9aSMichal Simek writel(0, ®s->laddr[i][LADDR_HIGH]); 261185f7d9aSMichal Simek /* Do not use MATCHx register */ 262185f7d9aSMichal Simek writel(0, ®s->match[i]); 263185f7d9aSMichal Simek } 264185f7d9aSMichal Simek 265185f7d9aSMichal Simek writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 266185f7d9aSMichal Simek writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 267185f7d9aSMichal Simek 268185f7d9aSMichal Simek return 0; 269185f7d9aSMichal Simek } 270185f7d9aSMichal Simek 271185f7d9aSMichal Simek static int zynq_gem_init(struct eth_device *dev, bd_t * bis) 272185f7d9aSMichal Simek { 27380243528SMichal Simek u32 i, rclk, clk = 0; 274185f7d9aSMichal Simek struct phy_device *phydev; 275185f7d9aSMichal Simek const u32 stat_size = (sizeof(struct zynq_gem_regs) - 276185f7d9aSMichal Simek offsetof(struct zynq_gem_regs, stat)) / 4; 277185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 278185f7d9aSMichal Simek struct zynq_gem_priv *priv = dev->priv; 279185f7d9aSMichal Simek const u32 supported = SUPPORTED_10baseT_Half | 280185f7d9aSMichal Simek SUPPORTED_10baseT_Full | 281185f7d9aSMichal Simek SUPPORTED_100baseT_Half | 282185f7d9aSMichal Simek SUPPORTED_100baseT_Full | 283185f7d9aSMichal Simek SUPPORTED_1000baseT_Half | 284185f7d9aSMichal Simek SUPPORTED_1000baseT_Full; 285185f7d9aSMichal Simek 28605868759SMichal Simek if (!priv->init) { 287185f7d9aSMichal Simek /* Disable all interrupts */ 288185f7d9aSMichal Simek writel(0xFFFFFFFF, ®s->idr); 289185f7d9aSMichal Simek 290185f7d9aSMichal Simek /* Disable the receiver & transmitter */ 291185f7d9aSMichal Simek writel(0, ®s->nwctrl); 292185f7d9aSMichal Simek writel(0, ®s->txsr); 293185f7d9aSMichal Simek writel(0, ®s->rxsr); 294185f7d9aSMichal Simek writel(0, ®s->phymntnc); 295185f7d9aSMichal Simek 29605868759SMichal Simek /* Clear the Hash registers for the mac address 29705868759SMichal Simek * pointed by AddressPtr 29805868759SMichal Simek */ 299185f7d9aSMichal Simek writel(0x0, ®s->hashl); 300185f7d9aSMichal Simek /* Write bits [63:32] in TOP */ 301185f7d9aSMichal Simek writel(0x0, ®s->hashh); 302185f7d9aSMichal Simek 303185f7d9aSMichal Simek /* Clear all counters */ 304185f7d9aSMichal Simek for (i = 0; i <= stat_size; i++) 305185f7d9aSMichal Simek readl(®s->stat[i]); 306185f7d9aSMichal Simek 307185f7d9aSMichal Simek /* Setup RxBD space */ 308*a5144237SSrikanth Thokala memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 309185f7d9aSMichal Simek 310185f7d9aSMichal Simek for (i = 0; i < RX_BUF; i++) { 311185f7d9aSMichal Simek priv->rx_bd[i].status = 0xF0000000; 31205868759SMichal Simek priv->rx_bd[i].addr = 313*a5144237SSrikanth Thokala ((u32)(priv->rxbuffers) + 314185f7d9aSMichal Simek (i * PKTSIZE_ALIGN)); 315185f7d9aSMichal Simek } 316185f7d9aSMichal Simek /* WRAP bit to last BD */ 317185f7d9aSMichal Simek priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 318185f7d9aSMichal Simek /* Write RxBDs to IP */ 319*a5144237SSrikanth Thokala writel((u32)priv->rx_bd, ®s->rxqbase); 320185f7d9aSMichal Simek 321185f7d9aSMichal Simek /* Setup for DMA Configuration register */ 322185f7d9aSMichal Simek writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 323185f7d9aSMichal Simek 324185f7d9aSMichal Simek /* Setup for Network Control register, MDIO, Rx and Tx enable */ 32580243528SMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 326185f7d9aSMichal Simek 32705868759SMichal Simek priv->init++; 32805868759SMichal Simek } 32905868759SMichal Simek 330f97d7e8bSMichal Simek phy_detection(dev); 331f97d7e8bSMichal Simek 332185f7d9aSMichal Simek /* interface - look at tsec */ 333185f7d9aSMichal Simek phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); 334185f7d9aSMichal Simek 33580243528SMichal Simek phydev->supported = supported | ADVERTISED_Pause | 33680243528SMichal Simek ADVERTISED_Asym_Pause; 337185f7d9aSMichal Simek phydev->advertising = phydev->supported; 338185f7d9aSMichal Simek priv->phydev = phydev; 339185f7d9aSMichal Simek phy_config(phydev); 340185f7d9aSMichal Simek phy_startup(phydev); 341185f7d9aSMichal Simek 34280243528SMichal Simek switch (phydev->speed) { 34380243528SMichal Simek case SPEED_1000: 34480243528SMichal Simek writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 34580243528SMichal Simek ®s->nwcfg); 34680243528SMichal Simek rclk = (0 << 4) | (1 << 0); 34780243528SMichal Simek clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0); 34880243528SMichal Simek break; 34980243528SMichal Simek case SPEED_100: 35080243528SMichal Simek clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, 35180243528SMichal Simek ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); 35280243528SMichal Simek rclk = 1 << 0; 35380243528SMichal Simek clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); 35480243528SMichal Simek break; 35580243528SMichal Simek case SPEED_10: 35680243528SMichal Simek rclk = 1 << 0; 35780243528SMichal Simek /* FIXME untested */ 35880243528SMichal Simek clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); 35980243528SMichal Simek break; 36080243528SMichal Simek } 36101fbf310SDavid Andrey 36201fbf310SDavid Andrey /* Change the rclk and clk only not using EMIO interface */ 36301fbf310SDavid Andrey if (!priv->emio) 36401fbf310SDavid Andrey zynq_slcr_gem_clk_setup(dev->iobase != 36501fbf310SDavid Andrey ZYNQ_GEM_BASEADDR0, rclk, clk); 36680243528SMichal Simek 36780243528SMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 36880243528SMichal Simek ZYNQ_GEM_NWCTRL_TXEN_MASK); 36980243528SMichal Simek 370185f7d9aSMichal Simek return 0; 371185f7d9aSMichal Simek } 372185f7d9aSMichal Simek 373185f7d9aSMichal Simek static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) 374185f7d9aSMichal Simek { 375*a5144237SSrikanth Thokala u32 addr, size; 376185f7d9aSMichal Simek struct zynq_gem_priv *priv = dev->priv; 377185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 378185f7d9aSMichal Simek 379185f7d9aSMichal Simek /* setup BD */ 380*a5144237SSrikanth Thokala writel((u32)priv->tx_bd, ®s->txqbase); 381185f7d9aSMichal Simek 382185f7d9aSMichal Simek /* Setup Tx BD */ 383*a5144237SSrikanth Thokala memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 384185f7d9aSMichal Simek 385*a5144237SSrikanth Thokala priv->tx_bd->addr = (u32)ptr; 386*a5144237SSrikanth Thokala priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 387*a5144237SSrikanth Thokala ZYNQ_GEM_TXBUF_LAST_MASK; 388*a5144237SSrikanth Thokala 389*a5144237SSrikanth Thokala addr = (u32) ptr; 390*a5144237SSrikanth Thokala addr &= ~(ARCH_DMA_MINALIGN - 1); 391*a5144237SSrikanth Thokala size = roundup(len, ARCH_DMA_MINALIGN); 392*a5144237SSrikanth Thokala flush_dcache_range(addr, addr + size); 393*a5144237SSrikanth Thokala barrier(); 394185f7d9aSMichal Simek 395185f7d9aSMichal Simek /* Start transmit */ 396185f7d9aSMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 397185f7d9aSMichal Simek 398*a5144237SSrikanth Thokala /* Read TX BD status */ 399*a5144237SSrikanth Thokala if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN) 400*a5144237SSrikanth Thokala printf("TX underrun\n"); 401*a5144237SSrikanth Thokala if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 402*a5144237SSrikanth Thokala printf("TX buffers exhausted in mid frame\n"); 403185f7d9aSMichal Simek 404185f7d9aSMichal Simek return 0; 405185f7d9aSMichal Simek } 406185f7d9aSMichal Simek 407185f7d9aSMichal Simek /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 408185f7d9aSMichal Simek static int zynq_gem_recv(struct eth_device *dev) 409185f7d9aSMichal Simek { 410185f7d9aSMichal Simek int frame_len; 411185f7d9aSMichal Simek struct zynq_gem_priv *priv = dev->priv; 412185f7d9aSMichal Simek struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 413185f7d9aSMichal Simek struct emac_bd *first_bd; 414185f7d9aSMichal Simek 415185f7d9aSMichal Simek if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 416185f7d9aSMichal Simek return 0; 417185f7d9aSMichal Simek 418185f7d9aSMichal Simek if (!(current_bd->status & 419185f7d9aSMichal Simek (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 420185f7d9aSMichal Simek printf("GEM: SOF or EOF not set for last buffer received!\n"); 421185f7d9aSMichal Simek return 0; 422185f7d9aSMichal Simek } 423185f7d9aSMichal Simek 424185f7d9aSMichal Simek frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 425185f7d9aSMichal Simek if (frame_len) { 426*a5144237SSrikanth Thokala u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 427*a5144237SSrikanth Thokala addr &= ~(ARCH_DMA_MINALIGN - 1); 428*a5144237SSrikanth Thokala u32 size = roundup(frame_len, ARCH_DMA_MINALIGN); 429*a5144237SSrikanth Thokala invalidate_dcache_range(addr, addr + size); 430*a5144237SSrikanth Thokala 431*a5144237SSrikanth Thokala NetReceive((u8 *)addr, frame_len); 432185f7d9aSMichal Simek 433185f7d9aSMichal Simek if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 434185f7d9aSMichal Simek priv->rx_first_buf = priv->rxbd_current; 435185f7d9aSMichal Simek else { 436185f7d9aSMichal Simek current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 437185f7d9aSMichal Simek current_bd->status = 0xF0000000; /* FIXME */ 438185f7d9aSMichal Simek } 439185f7d9aSMichal Simek 440185f7d9aSMichal Simek if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 441185f7d9aSMichal Simek first_bd = &priv->rx_bd[priv->rx_first_buf]; 442185f7d9aSMichal Simek first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 443185f7d9aSMichal Simek first_bd->status = 0xF0000000; 444185f7d9aSMichal Simek } 445185f7d9aSMichal Simek 446185f7d9aSMichal Simek if ((++priv->rxbd_current) >= RX_BUF) 447185f7d9aSMichal Simek priv->rxbd_current = 0; 448185f7d9aSMichal Simek } 449185f7d9aSMichal Simek 4503b90d0afSMichal Simek return frame_len; 451185f7d9aSMichal Simek } 452185f7d9aSMichal Simek 453185f7d9aSMichal Simek static void zynq_gem_halt(struct eth_device *dev) 454185f7d9aSMichal Simek { 455185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 456185f7d9aSMichal Simek 45780243528SMichal Simek clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 45880243528SMichal Simek ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 459185f7d9aSMichal Simek } 460185f7d9aSMichal Simek 461185f7d9aSMichal Simek static int zynq_gem_miiphyread(const char *devname, uchar addr, 462185f7d9aSMichal Simek uchar reg, ushort *val) 463185f7d9aSMichal Simek { 464185f7d9aSMichal Simek struct eth_device *dev = eth_get_dev(); 465185f7d9aSMichal Simek int ret; 466185f7d9aSMichal Simek 467185f7d9aSMichal Simek ret = phyread(dev, addr, reg, val); 468185f7d9aSMichal Simek debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); 469185f7d9aSMichal Simek return ret; 470185f7d9aSMichal Simek } 471185f7d9aSMichal Simek 472185f7d9aSMichal Simek static int zynq_gem_miiphy_write(const char *devname, uchar addr, 473185f7d9aSMichal Simek uchar reg, ushort val) 474185f7d9aSMichal Simek { 475185f7d9aSMichal Simek struct eth_device *dev = eth_get_dev(); 476185f7d9aSMichal Simek 477185f7d9aSMichal Simek debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); 478185f7d9aSMichal Simek return phywrite(dev, addr, reg, val); 479185f7d9aSMichal Simek } 480185f7d9aSMichal Simek 48101fbf310SDavid Andrey int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio) 482185f7d9aSMichal Simek { 483185f7d9aSMichal Simek struct eth_device *dev; 484185f7d9aSMichal Simek struct zynq_gem_priv *priv; 485*a5144237SSrikanth Thokala void *bd_space; 486185f7d9aSMichal Simek 487185f7d9aSMichal Simek dev = calloc(1, sizeof(*dev)); 488185f7d9aSMichal Simek if (dev == NULL) 489185f7d9aSMichal Simek return -1; 490185f7d9aSMichal Simek 491185f7d9aSMichal Simek dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); 492185f7d9aSMichal Simek if (dev->priv == NULL) { 493185f7d9aSMichal Simek free(dev); 494185f7d9aSMichal Simek return -1; 495185f7d9aSMichal Simek } 496185f7d9aSMichal Simek priv = dev->priv; 497185f7d9aSMichal Simek 498*a5144237SSrikanth Thokala /* Align rxbuffers to ARCH_DMA_MINALIGN */ 499*a5144237SSrikanth Thokala priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 500*a5144237SSrikanth Thokala memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 501*a5144237SSrikanth Thokala 502*a5144237SSrikanth Thokala /* Align bd_space to 1MB */ 503*a5144237SSrikanth Thokala bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 504*a5144237SSrikanth Thokala mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF); 505*a5144237SSrikanth Thokala 506*a5144237SSrikanth Thokala /* Initialize the bd spaces for tx and rx bd's */ 507*a5144237SSrikanth Thokala priv->tx_bd = (struct emac_bd *)bd_space; 508*a5144237SSrikanth Thokala priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE); 509*a5144237SSrikanth Thokala 510117cd4ccSDavid Andrey priv->phyaddr = phy_addr; 51101fbf310SDavid Andrey priv->emio = emio; 512185f7d9aSMichal Simek 513185f7d9aSMichal Simek sprintf(dev->name, "Gem.%x", base_addr); 514185f7d9aSMichal Simek 515185f7d9aSMichal Simek dev->iobase = base_addr; 516185f7d9aSMichal Simek 517185f7d9aSMichal Simek dev->init = zynq_gem_init; 518185f7d9aSMichal Simek dev->halt = zynq_gem_halt; 519185f7d9aSMichal Simek dev->send = zynq_gem_send; 520185f7d9aSMichal Simek dev->recv = zynq_gem_recv; 521185f7d9aSMichal Simek dev->write_hwaddr = zynq_gem_setup_mac; 522185f7d9aSMichal Simek 523185f7d9aSMichal Simek eth_register(dev); 524185f7d9aSMichal Simek 525185f7d9aSMichal Simek miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); 526185f7d9aSMichal Simek priv->bus = miiphy_get_dev_by_name(dev->name); 527185f7d9aSMichal Simek 528185f7d9aSMichal Simek return 1; 529185f7d9aSMichal Simek } 530