1185f7d9aSMichal Simek /* 2185f7d9aSMichal Simek * (C) Copyright 2011 Michal Simek 3185f7d9aSMichal Simek * 4185f7d9aSMichal Simek * Michal SIMEK <monstr@monstr.eu> 5185f7d9aSMichal Simek * 6185f7d9aSMichal Simek * Based on Xilinx gmac driver: 7185f7d9aSMichal Simek * (C) Copyright 2011 Xilinx 8185f7d9aSMichal Simek * 91a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 10185f7d9aSMichal Simek */ 11185f7d9aSMichal Simek 12185f7d9aSMichal Simek #include <common.h> 136889ca71SMichal Simek #include <dm.h> 14185f7d9aSMichal Simek #include <net.h> 152fd2489bSMichal Simek #include <netdev.h> 16185f7d9aSMichal Simek #include <config.h> 17b8de29feSMichal Simek #include <console.h> 18185f7d9aSMichal Simek #include <malloc.h> 19185f7d9aSMichal Simek #include <asm/io.h> 20185f7d9aSMichal Simek #include <phy.h> 21185f7d9aSMichal Simek #include <miiphy.h> 22e7138b34SMateusz Kulikowski #include <wait_bit.h> 23185f7d9aSMichal Simek #include <watchdog.h> 2496f4f149SSiva Durga Prasad Paladugu #include <asm/system.h> 2501fbf310SDavid Andrey #include <asm/arch/hardware.h> 2680243528SMichal Simek #include <asm/arch/sys_proto.h> 27e4d2318aSMichal Simek #include <asm-generic/errno.h> 28185f7d9aSMichal Simek 296889ca71SMichal Simek DECLARE_GLOBAL_DATA_PTR; 306889ca71SMichal Simek 31185f7d9aSMichal Simek /* Bit/mask specification */ 32185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 33185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 34185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 35185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 36185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 37185f7d9aSMichal Simek 38185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 39185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 40185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 41185f7d9aSMichal Simek 42185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 43185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 44185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 45185f7d9aSMichal Simek 46185f7d9aSMichal Simek /* Wrap bit, last descriptor */ 47185f7d9aSMichal Simek #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 48185f7d9aSMichal Simek #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 4923a598f7SMichal Simek #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 50185f7d9aSMichal Simek 51185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 52185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 53185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 54185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 55185f7d9aSMichal Simek 5680243528SMichal Simek #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 5780243528SMichal Simek #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 5880243528SMichal Simek #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 5980243528SMichal Simek #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 60a06c341fSSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x080000000 /* SGMII Enable */ 61a06c341fSSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_PCS_SEL 0x000000800 /* PCS select */ 62f17ea71dSMichal Simek #ifdef CONFIG_ARM64 63f17ea71dSMichal Simek #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */ 64f17ea71dSMichal Simek #else 656777f386SMichal Simek #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ 66f17ea71dSMichal Simek #endif 67185f7d9aSMichal Simek 688a584c8aSSiva Durga Prasad Paladugu #ifdef CONFIG_ARM64 698a584c8aSSiva Durga Prasad Paladugu # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 708a584c8aSSiva Durga Prasad Paladugu #else 718a584c8aSSiva Durga Prasad Paladugu # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 728a584c8aSSiva Durga Prasad Paladugu #endif 738a584c8aSSiva Durga Prasad Paladugu 748a584c8aSSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 758a584c8aSSiva Durga Prasad Paladugu ZYNQ_GEM_NWCFG_FDEN | \ 76185f7d9aSMichal Simek ZYNQ_GEM_NWCFG_FSREM | \ 77185f7d9aSMichal Simek ZYNQ_GEM_NWCFG_MDCCLKDIV) 78185f7d9aSMichal Simek 79185f7d9aSMichal Simek #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 80185f7d9aSMichal Simek 81185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 82185f7d9aSMichal Simek /* Use full configured addressable space (8 Kb) */ 83185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 84185f7d9aSMichal Simek /* Use full configured addressable space (4 Kb) */ 85185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 86185f7d9aSMichal Simek /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 87185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 88185f7d9aSMichal Simek 89185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 90185f7d9aSMichal Simek ZYNQ_GEM_DMACR_RXSIZE | \ 91185f7d9aSMichal Simek ZYNQ_GEM_DMACR_TXSIZE | \ 92185f7d9aSMichal Simek ZYNQ_GEM_DMACR_RXBUF) 93185f7d9aSMichal Simek 94e4d2318aSMichal Simek #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 95e4d2318aSMichal Simek 96*845ee5f6SSiva Durga Prasad Paladugu #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 97*845ee5f6SSiva Durga Prasad Paladugu 98f97d7e8bSMichal Simek /* Use MII register 1 (MII status register) to detect PHY */ 99f97d7e8bSMichal Simek #define PHY_DETECT_REG 1 100f97d7e8bSMichal Simek 101f97d7e8bSMichal Simek /* Mask used to verify certain PHY features (or register contents) 102f97d7e8bSMichal Simek * in the register above: 103f97d7e8bSMichal Simek * 0x1000: 10Mbps full duplex support 104f97d7e8bSMichal Simek * 0x0800: 10Mbps half duplex support 105f97d7e8bSMichal Simek * 0x0008: Auto-negotiation support 106f97d7e8bSMichal Simek */ 107f97d7e8bSMichal Simek #define PHY_DETECT_MASK 0x1808 108f97d7e8bSMichal Simek 109a5144237SSrikanth Thokala /* TX BD status masks */ 110a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 111a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 112a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 113a5144237SSrikanth Thokala 11497598fcfSSoren Brinkmann /* Clock frequencies for different speeds */ 11597598fcfSSoren Brinkmann #define ZYNQ_GEM_FREQUENCY_10 2500000UL 11697598fcfSSoren Brinkmann #define ZYNQ_GEM_FREQUENCY_100 25000000UL 11797598fcfSSoren Brinkmann #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 11897598fcfSSoren Brinkmann 119185f7d9aSMichal Simek /* Device registers */ 120185f7d9aSMichal Simek struct zynq_gem_regs { 12197a51a03SMichal Simek u32 nwctrl; /* 0x0 - Network Control reg */ 12297a51a03SMichal Simek u32 nwcfg; /* 0x4 - Network Config reg */ 12397a51a03SMichal Simek u32 nwsr; /* 0x8 - Network Status reg */ 124185f7d9aSMichal Simek u32 reserved1; 12597a51a03SMichal Simek u32 dmacr; /* 0x10 - DMA Control reg */ 12697a51a03SMichal Simek u32 txsr; /* 0x14 - TX Status reg */ 12797a51a03SMichal Simek u32 rxqbase; /* 0x18 - RX Q Base address reg */ 12897a51a03SMichal Simek u32 txqbase; /* 0x1c - TX Q Base address reg */ 12997a51a03SMichal Simek u32 rxsr; /* 0x20 - RX Status reg */ 130185f7d9aSMichal Simek u32 reserved2[2]; 13197a51a03SMichal Simek u32 idr; /* 0x2c - Interrupt Disable reg */ 132185f7d9aSMichal Simek u32 reserved3; 13397a51a03SMichal Simek u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 134185f7d9aSMichal Simek u32 reserved4[18]; 13597a51a03SMichal Simek u32 hashl; /* 0x80 - Hash Low address reg */ 13697a51a03SMichal Simek u32 hashh; /* 0x84 - Hash High address reg */ 137185f7d9aSMichal Simek #define LADDR_LOW 0 138185f7d9aSMichal Simek #define LADDR_HIGH 1 13997a51a03SMichal Simek u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 14097a51a03SMichal Simek u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 141185f7d9aSMichal Simek u32 reserved6[18]; 1420ebf4041SMichal Simek #define STAT_SIZE 44 1430ebf4041SMichal Simek u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 144*845ee5f6SSiva Durga Prasad Paladugu u32 reserved9[20]; 145*845ee5f6SSiva Durga Prasad Paladugu u32 pcscntrl; 146*845ee5f6SSiva Durga Prasad Paladugu u32 reserved7[143]; 147603ff008SEdgar E. Iglesias u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 148603ff008SEdgar E. Iglesias u32 reserved8[15]; 149603ff008SEdgar E. Iglesias u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 150185f7d9aSMichal Simek }; 151185f7d9aSMichal Simek 152185f7d9aSMichal Simek /* BD descriptors */ 153185f7d9aSMichal Simek struct emac_bd { 154185f7d9aSMichal Simek u32 addr; /* Next descriptor pointer */ 155185f7d9aSMichal Simek u32 status; 156185f7d9aSMichal Simek }; 157185f7d9aSMichal Simek 158eda9d307SSiva Durga Prasad Paladugu #define RX_BUF 32 159a5144237SSrikanth Thokala /* Page table entries are set to 1MB, or multiples of 1MB 160a5144237SSrikanth Thokala * (not < 1MB). driver uses less bd's so use 1MB bdspace. 161a5144237SSrikanth Thokala */ 162a5144237SSrikanth Thokala #define BD_SPACE 0x100000 163a5144237SSrikanth Thokala /* BD separation space */ 164ff475878SMichal Simek #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 165185f7d9aSMichal Simek 166603ff008SEdgar E. Iglesias /* Setup the first free TX descriptor */ 167603ff008SEdgar E. Iglesias #define TX_FREE_DESC 2 168603ff008SEdgar E. Iglesias 169185f7d9aSMichal Simek /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 170185f7d9aSMichal Simek struct zynq_gem_priv { 171a5144237SSrikanth Thokala struct emac_bd *tx_bd; 172a5144237SSrikanth Thokala struct emac_bd *rx_bd; 173a5144237SSrikanth Thokala char *rxbuffers; 174185f7d9aSMichal Simek u32 rxbd_current; 175185f7d9aSMichal Simek u32 rx_first_buf; 176185f7d9aSMichal Simek int phyaddr; 17701fbf310SDavid Andrey u32 emio; 17805868759SMichal Simek int init; 179f2fc2768SMichal Simek struct zynq_gem_regs *iobase; 18016ce6de8SMichal Simek phy_interface_t interface; 181185f7d9aSMichal Simek struct phy_device *phydev; 182185f7d9aSMichal Simek struct mii_dev *bus; 183185f7d9aSMichal Simek }; 184185f7d9aSMichal Simek 1853fac2724SMichal Simek static inline int mdio_wait(struct zynq_gem_regs *regs) 186185f7d9aSMichal Simek { 1874c8b7bf4SMichal Simek u32 timeout = 20000; 188185f7d9aSMichal Simek 189185f7d9aSMichal Simek /* Wait till MDIO interface is ready to accept a new transaction. */ 190185f7d9aSMichal Simek while (--timeout) { 191185f7d9aSMichal Simek if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 192185f7d9aSMichal Simek break; 193185f7d9aSMichal Simek WATCHDOG_RESET(); 194185f7d9aSMichal Simek } 195185f7d9aSMichal Simek 196185f7d9aSMichal Simek if (!timeout) { 197185f7d9aSMichal Simek printf("%s: Timeout\n", __func__); 198185f7d9aSMichal Simek return 1; 199185f7d9aSMichal Simek } 200185f7d9aSMichal Simek 201185f7d9aSMichal Simek return 0; 202185f7d9aSMichal Simek } 203185f7d9aSMichal Simek 204f2fc2768SMichal Simek static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, 205185f7d9aSMichal Simek u32 op, u16 *data) 206185f7d9aSMichal Simek { 207185f7d9aSMichal Simek u32 mgtcr; 208f2fc2768SMichal Simek struct zynq_gem_regs *regs = priv->iobase; 209185f7d9aSMichal Simek 2103fac2724SMichal Simek if (mdio_wait(regs)) 211185f7d9aSMichal Simek return 1; 212185f7d9aSMichal Simek 213185f7d9aSMichal Simek /* Construct mgtcr mask for the operation */ 214185f7d9aSMichal Simek mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 215185f7d9aSMichal Simek (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 216185f7d9aSMichal Simek (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 217185f7d9aSMichal Simek 218185f7d9aSMichal Simek /* Write mgtcr and wait for completion */ 219185f7d9aSMichal Simek writel(mgtcr, ®s->phymntnc); 220185f7d9aSMichal Simek 2213fac2724SMichal Simek if (mdio_wait(regs)) 222185f7d9aSMichal Simek return 1; 223185f7d9aSMichal Simek 224185f7d9aSMichal Simek if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 225185f7d9aSMichal Simek *data = readl(®s->phymntnc); 226185f7d9aSMichal Simek 227185f7d9aSMichal Simek return 0; 228185f7d9aSMichal Simek } 229185f7d9aSMichal Simek 230f2fc2768SMichal Simek static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, 231f2fc2768SMichal Simek u32 regnum, u16 *val) 232185f7d9aSMichal Simek { 233198e9a4fSMichal Simek u32 ret; 234198e9a4fSMichal Simek 235f2fc2768SMichal Simek ret = phy_setup_op(priv, phy_addr, regnum, 236185f7d9aSMichal Simek ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 237198e9a4fSMichal Simek 238198e9a4fSMichal Simek if (!ret) 239198e9a4fSMichal Simek debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 240198e9a4fSMichal Simek phy_addr, regnum, *val); 241198e9a4fSMichal Simek 242198e9a4fSMichal Simek return ret; 243185f7d9aSMichal Simek } 244185f7d9aSMichal Simek 245f2fc2768SMichal Simek static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, 246f2fc2768SMichal Simek u32 regnum, u16 data) 247185f7d9aSMichal Simek { 248198e9a4fSMichal Simek debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 249198e9a4fSMichal Simek regnum, data); 250198e9a4fSMichal Simek 251f2fc2768SMichal Simek return phy_setup_op(priv, phy_addr, regnum, 252185f7d9aSMichal Simek ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 253185f7d9aSMichal Simek } 254185f7d9aSMichal Simek 2556889ca71SMichal Simek static int phy_detection(struct udevice *dev) 256f97d7e8bSMichal Simek { 257f97d7e8bSMichal Simek int i; 258f97d7e8bSMichal Simek u16 phyreg; 259f97d7e8bSMichal Simek struct zynq_gem_priv *priv = dev->priv; 260f97d7e8bSMichal Simek 261f97d7e8bSMichal Simek if (priv->phyaddr != -1) { 262f2fc2768SMichal Simek phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); 263f97d7e8bSMichal Simek if ((phyreg != 0xFFFF) && 264f97d7e8bSMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 265f97d7e8bSMichal Simek /* Found a valid PHY address */ 266f97d7e8bSMichal Simek debug("Default phy address %d is valid\n", 267f97d7e8bSMichal Simek priv->phyaddr); 268b904725aSMichal Simek return 0; 269f97d7e8bSMichal Simek } else { 270f97d7e8bSMichal Simek debug("PHY address is not setup correctly %d\n", 271f97d7e8bSMichal Simek priv->phyaddr); 272f97d7e8bSMichal Simek priv->phyaddr = -1; 273f97d7e8bSMichal Simek } 274f97d7e8bSMichal Simek } 275f97d7e8bSMichal Simek 276f97d7e8bSMichal Simek debug("detecting phy address\n"); 277f97d7e8bSMichal Simek if (priv->phyaddr == -1) { 278f97d7e8bSMichal Simek /* detect the PHY address */ 279f97d7e8bSMichal Simek for (i = 31; i >= 0; i--) { 280f2fc2768SMichal Simek phyread(priv, i, PHY_DETECT_REG, &phyreg); 281f97d7e8bSMichal Simek if ((phyreg != 0xFFFF) && 282f97d7e8bSMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 283f97d7e8bSMichal Simek /* Found a valid PHY address */ 284f97d7e8bSMichal Simek priv->phyaddr = i; 285f97d7e8bSMichal Simek debug("Found valid phy address, %d\n", i); 286b904725aSMichal Simek return 0; 287f97d7e8bSMichal Simek } 288f97d7e8bSMichal Simek } 289f97d7e8bSMichal Simek } 290f97d7e8bSMichal Simek printf("PHY is not detected\n"); 291b904725aSMichal Simek return -1; 292f97d7e8bSMichal Simek } 293f97d7e8bSMichal Simek 2946889ca71SMichal Simek static int zynq_gem_setup_mac(struct udevice *dev) 295185f7d9aSMichal Simek { 296185f7d9aSMichal Simek u32 i, macaddrlow, macaddrhigh; 2976889ca71SMichal Simek struct eth_pdata *pdata = dev_get_platdata(dev); 2986889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev); 2996889ca71SMichal Simek struct zynq_gem_regs *regs = priv->iobase; 300185f7d9aSMichal Simek 301185f7d9aSMichal Simek /* Set the MAC bits [31:0] in BOT */ 3026889ca71SMichal Simek macaddrlow = pdata->enetaddr[0]; 3036889ca71SMichal Simek macaddrlow |= pdata->enetaddr[1] << 8; 3046889ca71SMichal Simek macaddrlow |= pdata->enetaddr[2] << 16; 3056889ca71SMichal Simek macaddrlow |= pdata->enetaddr[3] << 24; 306185f7d9aSMichal Simek 307185f7d9aSMichal Simek /* Set MAC bits [47:32] in TOP */ 3086889ca71SMichal Simek macaddrhigh = pdata->enetaddr[4]; 3096889ca71SMichal Simek macaddrhigh |= pdata->enetaddr[5] << 8; 310185f7d9aSMichal Simek 311185f7d9aSMichal Simek for (i = 0; i < 4; i++) { 312185f7d9aSMichal Simek writel(0, ®s->laddr[i][LADDR_LOW]); 313185f7d9aSMichal Simek writel(0, ®s->laddr[i][LADDR_HIGH]); 314185f7d9aSMichal Simek /* Do not use MATCHx register */ 315185f7d9aSMichal Simek writel(0, ®s->match[i]); 316185f7d9aSMichal Simek } 317185f7d9aSMichal Simek 318185f7d9aSMichal Simek writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 319185f7d9aSMichal Simek writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 320185f7d9aSMichal Simek 321185f7d9aSMichal Simek return 0; 322185f7d9aSMichal Simek } 323185f7d9aSMichal Simek 3246889ca71SMichal Simek static int zynq_phy_init(struct udevice *dev) 32568cc3bd8SMichal Simek { 32668cc3bd8SMichal Simek int ret; 3276889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev); 3286889ca71SMichal Simek struct zynq_gem_regs *regs = priv->iobase; 32968cc3bd8SMichal Simek const u32 supported = SUPPORTED_10baseT_Half | 33068cc3bd8SMichal Simek SUPPORTED_10baseT_Full | 33168cc3bd8SMichal Simek SUPPORTED_100baseT_Half | 33268cc3bd8SMichal Simek SUPPORTED_100baseT_Full | 33368cc3bd8SMichal Simek SUPPORTED_1000baseT_Half | 33468cc3bd8SMichal Simek SUPPORTED_1000baseT_Full; 33568cc3bd8SMichal Simek 336c8e29271SMichal Simek /* Enable only MDIO bus */ 337c8e29271SMichal Simek writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); 338c8e29271SMichal Simek 339a06c341fSSiva Durga Prasad Paladugu if (priv->interface != PHY_INTERFACE_MODE_SGMII) { 34068cc3bd8SMichal Simek ret = phy_detection(dev); 34168cc3bd8SMichal Simek if (ret) { 34268cc3bd8SMichal Simek printf("GEM PHY init failed\n"); 34368cc3bd8SMichal Simek return ret; 34468cc3bd8SMichal Simek } 345a06c341fSSiva Durga Prasad Paladugu } 34668cc3bd8SMichal Simek 34768cc3bd8SMichal Simek priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, 34868cc3bd8SMichal Simek priv->interface); 34990c6f2e2SMichal Simek if (!priv->phydev) 35090c6f2e2SMichal Simek return -ENODEV; 35168cc3bd8SMichal Simek 35268cc3bd8SMichal Simek priv->phydev->supported = supported | ADVERTISED_Pause | 35368cc3bd8SMichal Simek ADVERTISED_Asym_Pause; 35468cc3bd8SMichal Simek priv->phydev->advertising = priv->phydev->supported; 35568cc3bd8SMichal Simek phy_config(priv->phydev); 35668cc3bd8SMichal Simek 35768cc3bd8SMichal Simek return 0; 35868cc3bd8SMichal Simek } 35968cc3bd8SMichal Simek 3606889ca71SMichal Simek static int zynq_gem_init(struct udevice *dev) 361185f7d9aSMichal Simek { 362a06c341fSSiva Durga Prasad Paladugu u32 i, nwconfig; 36397598fcfSSoren Brinkmann unsigned long clk_rate = 0; 3646889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev); 3656889ca71SMichal Simek struct zynq_gem_regs *regs = priv->iobase; 366603ff008SEdgar E. Iglesias struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 367603ff008SEdgar E. Iglesias struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 368185f7d9aSMichal Simek 36905868759SMichal Simek if (!priv->init) { 370185f7d9aSMichal Simek /* Disable all interrupts */ 371185f7d9aSMichal Simek writel(0xFFFFFFFF, ®s->idr); 372185f7d9aSMichal Simek 373185f7d9aSMichal Simek /* Disable the receiver & transmitter */ 374185f7d9aSMichal Simek writel(0, ®s->nwctrl); 375185f7d9aSMichal Simek writel(0, ®s->txsr); 376185f7d9aSMichal Simek writel(0, ®s->rxsr); 377185f7d9aSMichal Simek writel(0, ®s->phymntnc); 378185f7d9aSMichal Simek 37905868759SMichal Simek /* Clear the Hash registers for the mac address 38005868759SMichal Simek * pointed by AddressPtr 38105868759SMichal Simek */ 382185f7d9aSMichal Simek writel(0x0, ®s->hashl); 383185f7d9aSMichal Simek /* Write bits [63:32] in TOP */ 384185f7d9aSMichal Simek writel(0x0, ®s->hashh); 385185f7d9aSMichal Simek 386185f7d9aSMichal Simek /* Clear all counters */ 3870ebf4041SMichal Simek for (i = 0; i < STAT_SIZE; i++) 388185f7d9aSMichal Simek readl(®s->stat[i]); 389185f7d9aSMichal Simek 390185f7d9aSMichal Simek /* Setup RxBD space */ 391a5144237SSrikanth Thokala memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 392185f7d9aSMichal Simek 393185f7d9aSMichal Simek for (i = 0; i < RX_BUF; i++) { 394185f7d9aSMichal Simek priv->rx_bd[i].status = 0xF0000000; 39505868759SMichal Simek priv->rx_bd[i].addr = 3965b47d407SPrabhakar Kushwaha ((ulong)(priv->rxbuffers) + 397185f7d9aSMichal Simek (i * PKTSIZE_ALIGN)); 398185f7d9aSMichal Simek } 399185f7d9aSMichal Simek /* WRAP bit to last BD */ 400185f7d9aSMichal Simek priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 401185f7d9aSMichal Simek /* Write RxBDs to IP */ 4025b47d407SPrabhakar Kushwaha writel((ulong)priv->rx_bd, ®s->rxqbase); 403185f7d9aSMichal Simek 404185f7d9aSMichal Simek /* Setup for DMA Configuration register */ 405185f7d9aSMichal Simek writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 406185f7d9aSMichal Simek 407185f7d9aSMichal Simek /* Setup for Network Control register, MDIO, Rx and Tx enable */ 40880243528SMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 409185f7d9aSMichal Simek 410603ff008SEdgar E. Iglesias /* Disable the second priority queue */ 411603ff008SEdgar E. Iglesias dummy_tx_bd->addr = 0; 412603ff008SEdgar E. Iglesias dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 413603ff008SEdgar E. Iglesias ZYNQ_GEM_TXBUF_LAST_MASK| 414603ff008SEdgar E. Iglesias ZYNQ_GEM_TXBUF_USED_MASK; 415603ff008SEdgar E. Iglesias 416603ff008SEdgar E. Iglesias dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 417603ff008SEdgar E. Iglesias ZYNQ_GEM_RXBUF_NEW_MASK; 418603ff008SEdgar E. Iglesias dummy_rx_bd->status = 0; 419603ff008SEdgar E. Iglesias flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + 420603ff008SEdgar E. Iglesias sizeof(dummy_tx_bd)); 421603ff008SEdgar E. Iglesias flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + 422603ff008SEdgar E. Iglesias sizeof(dummy_rx_bd)); 423603ff008SEdgar E. Iglesias 424603ff008SEdgar E. Iglesias writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 425603ff008SEdgar E. Iglesias writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 426603ff008SEdgar E. Iglesias 42705868759SMichal Simek priv->init++; 42805868759SMichal Simek } 42905868759SMichal Simek 43064a7ead6SMichal Simek phy_startup(priv->phydev); 431185f7d9aSMichal Simek 43264a7ead6SMichal Simek if (!priv->phydev->link) { 43364a7ead6SMichal Simek printf("%s: No link.\n", priv->phydev->dev->name); 4344ed4aa20SMichal Simek return -1; 4354ed4aa20SMichal Simek } 4364ed4aa20SMichal Simek 437a06c341fSSiva Durga Prasad Paladugu nwconfig = ZYNQ_GEM_NWCFG_INIT; 438a06c341fSSiva Durga Prasad Paladugu 439*845ee5f6SSiva Durga Prasad Paladugu if (priv->interface == PHY_INTERFACE_MODE_SGMII) { 440a06c341fSSiva Durga Prasad Paladugu nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | 441a06c341fSSiva Durga Prasad Paladugu ZYNQ_GEM_NWCFG_PCS_SEL; 442*845ee5f6SSiva Durga Prasad Paladugu #ifdef CONFIG_ARM64 443*845ee5f6SSiva Durga Prasad Paladugu writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, 444*845ee5f6SSiva Durga Prasad Paladugu ®s->pcscntrl); 445*845ee5f6SSiva Durga Prasad Paladugu #endif 446*845ee5f6SSiva Durga Prasad Paladugu } 447a06c341fSSiva Durga Prasad Paladugu 44864a7ead6SMichal Simek switch (priv->phydev->speed) { 44980243528SMichal Simek case SPEED_1000: 450a06c341fSSiva Durga Prasad Paladugu writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, 45180243528SMichal Simek ®s->nwcfg); 45297598fcfSSoren Brinkmann clk_rate = ZYNQ_GEM_FREQUENCY_1000; 45380243528SMichal Simek break; 45480243528SMichal Simek case SPEED_100: 455a06c341fSSiva Durga Prasad Paladugu writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, 456242b1547SMichal Simek ®s->nwcfg); 45797598fcfSSoren Brinkmann clk_rate = ZYNQ_GEM_FREQUENCY_100; 45880243528SMichal Simek break; 45980243528SMichal Simek case SPEED_10: 46097598fcfSSoren Brinkmann clk_rate = ZYNQ_GEM_FREQUENCY_10; 46180243528SMichal Simek break; 46280243528SMichal Simek } 46301fbf310SDavid Andrey 46401fbf310SDavid Andrey /* Change the rclk and clk only not using EMIO interface */ 46501fbf310SDavid Andrey if (!priv->emio) 4666889ca71SMichal Simek zynq_slcr_gem_clk_setup((ulong)priv->iobase != 46797598fcfSSoren Brinkmann ZYNQ_GEM_BASEADDR0, clk_rate); 46880243528SMichal Simek 46980243528SMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 47080243528SMichal Simek ZYNQ_GEM_NWCTRL_TXEN_MASK); 47180243528SMichal Simek 472185f7d9aSMichal Simek return 0; 473185f7d9aSMichal Simek } 474185f7d9aSMichal Simek 4756889ca71SMichal Simek static int zynq_gem_send(struct udevice *dev, void *ptr, int len) 476185f7d9aSMichal Simek { 477a5144237SSrikanth Thokala u32 addr, size; 4786889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev); 4796889ca71SMichal Simek struct zynq_gem_regs *regs = priv->iobase; 48023a598f7SMichal Simek struct emac_bd *current_bd = &priv->tx_bd[1]; 481185f7d9aSMichal Simek 482185f7d9aSMichal Simek /* Setup Tx BD */ 483a5144237SSrikanth Thokala memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 484185f7d9aSMichal Simek 4855b47d407SPrabhakar Kushwaha priv->tx_bd->addr = (ulong)ptr; 486a5144237SSrikanth Thokala priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 48723a598f7SMichal Simek ZYNQ_GEM_TXBUF_LAST_MASK; 48823a598f7SMichal Simek /* Dummy descriptor to mark it as the last in descriptor chain */ 48923a598f7SMichal Simek current_bd->addr = 0x0; 49023a598f7SMichal Simek current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 491e65d33cfSMichal Simek ZYNQ_GEM_TXBUF_LAST_MASK| 49223a598f7SMichal Simek ZYNQ_GEM_TXBUF_USED_MASK; 493a5144237SSrikanth Thokala 49445c07741SMichal Simek /* setup BD */ 49545c07741SMichal Simek writel((ulong)priv->tx_bd, ®s->txqbase); 49645c07741SMichal Simek 4975b47d407SPrabhakar Kushwaha addr = (ulong) ptr; 498a5144237SSrikanth Thokala addr &= ~(ARCH_DMA_MINALIGN - 1); 499a5144237SSrikanth Thokala size = roundup(len, ARCH_DMA_MINALIGN); 500a5144237SSrikanth Thokala flush_dcache_range(addr, addr + size); 50196f4f149SSiva Durga Prasad Paladugu 5025b47d407SPrabhakar Kushwaha addr = (ulong)priv->rxbuffers; 50396f4f149SSiva Durga Prasad Paladugu addr &= ~(ARCH_DMA_MINALIGN - 1); 50496f4f149SSiva Durga Prasad Paladugu size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 50596f4f149SSiva Durga Prasad Paladugu flush_dcache_range(addr, addr + size); 506a5144237SSrikanth Thokala barrier(); 507185f7d9aSMichal Simek 508185f7d9aSMichal Simek /* Start transmit */ 509185f7d9aSMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 510185f7d9aSMichal Simek 511a5144237SSrikanth Thokala /* Read TX BD status */ 512a5144237SSrikanth Thokala if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 513a5144237SSrikanth Thokala printf("TX buffers exhausted in mid frame\n"); 514185f7d9aSMichal Simek 515e4d2318aSMichal Simek return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, 516e7138b34SMateusz Kulikowski true, 20000, true); 517185f7d9aSMichal Simek } 518185f7d9aSMichal Simek 519185f7d9aSMichal Simek /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 5206889ca71SMichal Simek static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) 521185f7d9aSMichal Simek { 522185f7d9aSMichal Simek int frame_len; 5239d9211acSMichal Simek u32 addr; 5246889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev); 525185f7d9aSMichal Simek struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 526185f7d9aSMichal Simek 527185f7d9aSMichal Simek if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 5289d9211acSMichal Simek return -1; 529185f7d9aSMichal Simek 530185f7d9aSMichal Simek if (!(current_bd->status & 531185f7d9aSMichal Simek (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 532185f7d9aSMichal Simek printf("GEM: SOF or EOF not set for last buffer received!\n"); 5339d9211acSMichal Simek return -1; 534185f7d9aSMichal Simek } 535185f7d9aSMichal Simek 536185f7d9aSMichal Simek frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 5379d9211acSMichal Simek if (!frame_len) { 5389d9211acSMichal Simek printf("%s: Zero size packet?\n", __func__); 5399d9211acSMichal Simek return -1; 5409d9211acSMichal Simek } 5419d9211acSMichal Simek 5429d9211acSMichal Simek addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 543a5144237SSrikanth Thokala addr &= ~(ARCH_DMA_MINALIGN - 1); 5449d9211acSMichal Simek *packetp = (uchar *)(uintptr_t)addr; 545a5144237SSrikanth Thokala 5469d9211acSMichal Simek return frame_len; 5479d9211acSMichal Simek } 548185f7d9aSMichal Simek 5499d9211acSMichal Simek static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) 5509d9211acSMichal Simek { 5519d9211acSMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev); 5529d9211acSMichal Simek struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 5539d9211acSMichal Simek struct emac_bd *first_bd; 5549d9211acSMichal Simek 5559d9211acSMichal Simek if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { 556185f7d9aSMichal Simek priv->rx_first_buf = priv->rxbd_current; 5579d9211acSMichal Simek } else { 558185f7d9aSMichal Simek current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 559185f7d9aSMichal Simek current_bd->status = 0xF0000000; /* FIXME */ 560185f7d9aSMichal Simek } 561185f7d9aSMichal Simek 562185f7d9aSMichal Simek if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 563185f7d9aSMichal Simek first_bd = &priv->rx_bd[priv->rx_first_buf]; 564185f7d9aSMichal Simek first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 565185f7d9aSMichal Simek first_bd->status = 0xF0000000; 566185f7d9aSMichal Simek } 567185f7d9aSMichal Simek 568185f7d9aSMichal Simek if ((++priv->rxbd_current) >= RX_BUF) 569185f7d9aSMichal Simek priv->rxbd_current = 0; 570185f7d9aSMichal Simek 571da872d7cSMichal Simek return 0; 572185f7d9aSMichal Simek } 573185f7d9aSMichal Simek 5746889ca71SMichal Simek static void zynq_gem_halt(struct udevice *dev) 575185f7d9aSMichal Simek { 5766889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev); 5776889ca71SMichal Simek struct zynq_gem_regs *regs = priv->iobase; 578185f7d9aSMichal Simek 57980243528SMichal Simek clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 58080243528SMichal Simek ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 581185f7d9aSMichal Simek } 582185f7d9aSMichal Simek 583a509a1d4SJoe Hershberger __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 584a509a1d4SJoe Hershberger { 585a509a1d4SJoe Hershberger return -ENOSYS; 586a509a1d4SJoe Hershberger } 587a509a1d4SJoe Hershberger 588a509a1d4SJoe Hershberger static int zynq_gem_read_rom_mac(struct udevice *dev) 589a509a1d4SJoe Hershberger { 590a509a1d4SJoe Hershberger int retval; 591a509a1d4SJoe Hershberger struct eth_pdata *pdata = dev_get_platdata(dev); 592a509a1d4SJoe Hershberger 593a509a1d4SJoe Hershberger retval = zynq_board_read_rom_ethaddr(pdata->enetaddr); 594a509a1d4SJoe Hershberger if (retval == -ENOSYS) 595a509a1d4SJoe Hershberger retval = 0; 596a509a1d4SJoe Hershberger 597a509a1d4SJoe Hershberger return retval; 598a509a1d4SJoe Hershberger } 599a509a1d4SJoe Hershberger 6006889ca71SMichal Simek static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, 6016889ca71SMichal Simek int devad, int reg) 602185f7d9aSMichal Simek { 6036889ca71SMichal Simek struct zynq_gem_priv *priv = bus->priv; 604185f7d9aSMichal Simek int ret; 6056889ca71SMichal Simek u16 val; 606185f7d9aSMichal Simek 6076889ca71SMichal Simek ret = phyread(priv, addr, reg, &val); 6086889ca71SMichal Simek debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); 6096889ca71SMichal Simek return val; 610185f7d9aSMichal Simek } 611185f7d9aSMichal Simek 6126889ca71SMichal Simek static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, 6136889ca71SMichal Simek int reg, u16 value) 614185f7d9aSMichal Simek { 6156889ca71SMichal Simek struct zynq_gem_priv *priv = bus->priv; 616185f7d9aSMichal Simek 6176889ca71SMichal Simek debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); 6186889ca71SMichal Simek return phywrite(priv, addr, reg, value); 619185f7d9aSMichal Simek } 620185f7d9aSMichal Simek 6216889ca71SMichal Simek static int zynq_gem_probe(struct udevice *dev) 622185f7d9aSMichal Simek { 623a5144237SSrikanth Thokala void *bd_space; 6246889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev); 6256889ca71SMichal Simek int ret; 626185f7d9aSMichal Simek 627a5144237SSrikanth Thokala /* Align rxbuffers to ARCH_DMA_MINALIGN */ 628a5144237SSrikanth Thokala priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 629a5144237SSrikanth Thokala memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 630a5144237SSrikanth Thokala 63196f4f149SSiva Durga Prasad Paladugu /* Align bd_space to MMU_SECTION_SHIFT */ 632a5144237SSrikanth Thokala bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 6339ce1edc8SMichal Simek mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 6349ce1edc8SMichal Simek BD_SPACE, DCACHE_OFF); 635a5144237SSrikanth Thokala 636a5144237SSrikanth Thokala /* Initialize the bd spaces for tx and rx bd's */ 637a5144237SSrikanth Thokala priv->tx_bd = (struct emac_bd *)bd_space; 6385b47d407SPrabhakar Kushwaha priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 639a5144237SSrikanth Thokala 6406889ca71SMichal Simek priv->bus = mdio_alloc(); 6416889ca71SMichal Simek priv->bus->read = zynq_gem_miiphy_read; 6426889ca71SMichal Simek priv->bus->write = zynq_gem_miiphy_write; 6436889ca71SMichal Simek priv->bus->priv = priv; 6446889ca71SMichal Simek strcpy(priv->bus->name, "gem"); 645185f7d9aSMichal Simek 6466889ca71SMichal Simek ret = mdio_register(priv->bus); 647c8e29271SMichal Simek if (ret) 648c8e29271SMichal Simek return ret; 649c8e29271SMichal Simek 650e76d2dcaSSiva Durga Prasad Paladugu return zynq_phy_init(dev); 651185f7d9aSMichal Simek } 6526889ca71SMichal Simek 6536889ca71SMichal Simek static int zynq_gem_remove(struct udevice *dev) 6546889ca71SMichal Simek { 6556889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev); 6566889ca71SMichal Simek 6576889ca71SMichal Simek free(priv->phydev); 6586889ca71SMichal Simek mdio_unregister(priv->bus); 6596889ca71SMichal Simek mdio_free(priv->bus); 6606889ca71SMichal Simek 6616889ca71SMichal Simek return 0; 6626889ca71SMichal Simek } 6636889ca71SMichal Simek 6646889ca71SMichal Simek static const struct eth_ops zynq_gem_ops = { 6656889ca71SMichal Simek .start = zynq_gem_init, 6666889ca71SMichal Simek .send = zynq_gem_send, 6676889ca71SMichal Simek .recv = zynq_gem_recv, 6689d9211acSMichal Simek .free_pkt = zynq_gem_free_pkt, 6696889ca71SMichal Simek .stop = zynq_gem_halt, 6706889ca71SMichal Simek .write_hwaddr = zynq_gem_setup_mac, 671a509a1d4SJoe Hershberger .read_rom_hwaddr = zynq_gem_read_rom_mac, 6726889ca71SMichal Simek }; 6736889ca71SMichal Simek 6746889ca71SMichal Simek static int zynq_gem_ofdata_to_platdata(struct udevice *dev) 6756889ca71SMichal Simek { 6766889ca71SMichal Simek struct eth_pdata *pdata = dev_get_platdata(dev); 6776889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev); 6786889ca71SMichal Simek int offset = 0; 6793cdb1450SMichal Simek const char *phy_mode; 6806889ca71SMichal Simek 6816889ca71SMichal Simek pdata->iobase = (phys_addr_t)dev_get_addr(dev); 6826889ca71SMichal Simek priv->iobase = (struct zynq_gem_regs *)pdata->iobase; 6836889ca71SMichal Simek /* Hardcode for now */ 6846889ca71SMichal Simek priv->emio = 0; 685bcdfef7aSMichal Simek priv->phyaddr = -1; 6866889ca71SMichal Simek 6876889ca71SMichal Simek offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, 6886889ca71SMichal Simek "phy-handle"); 6896889ca71SMichal Simek if (offset > 0) 690bcdfef7aSMichal Simek priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); 6916889ca71SMichal Simek 6923cdb1450SMichal Simek phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 6933cdb1450SMichal Simek if (phy_mode) 6943cdb1450SMichal Simek pdata->phy_interface = phy_get_interface_by_name(phy_mode); 6953cdb1450SMichal Simek if (pdata->phy_interface == -1) { 6963cdb1450SMichal Simek debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 6973cdb1450SMichal Simek return -EINVAL; 6983cdb1450SMichal Simek } 6993cdb1450SMichal Simek priv->interface = pdata->phy_interface; 7003cdb1450SMichal Simek 701a06c341fSSiva Durga Prasad Paladugu priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio"); 702a06c341fSSiva Durga Prasad Paladugu 7033cdb1450SMichal Simek printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, 7043cdb1450SMichal Simek priv->phyaddr, phy_string_for_interface(priv->interface)); 7056889ca71SMichal Simek 7066889ca71SMichal Simek return 0; 7076889ca71SMichal Simek } 7086889ca71SMichal Simek 7096889ca71SMichal Simek static const struct udevice_id zynq_gem_ids[] = { 7106889ca71SMichal Simek { .compatible = "cdns,zynqmp-gem" }, 7116889ca71SMichal Simek { .compatible = "cdns,zynq-gem" }, 7126889ca71SMichal Simek { .compatible = "cdns,gem" }, 7136889ca71SMichal Simek { } 7146889ca71SMichal Simek }; 7156889ca71SMichal Simek 7166889ca71SMichal Simek U_BOOT_DRIVER(zynq_gem) = { 7176889ca71SMichal Simek .name = "zynq_gem", 7186889ca71SMichal Simek .id = UCLASS_ETH, 7196889ca71SMichal Simek .of_match = zynq_gem_ids, 7206889ca71SMichal Simek .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, 7216889ca71SMichal Simek .probe = zynq_gem_probe, 7226889ca71SMichal Simek .remove = zynq_gem_remove, 7236889ca71SMichal Simek .ops = &zynq_gem_ops, 7246889ca71SMichal Simek .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), 7256889ca71SMichal Simek .platdata_auto_alloc_size = sizeof(struct eth_pdata), 7266889ca71SMichal Simek }; 727