1185f7d9aSMichal Simek /* 2185f7d9aSMichal Simek * (C) Copyright 2011 Michal Simek 3185f7d9aSMichal Simek * 4185f7d9aSMichal Simek * Michal SIMEK <monstr@monstr.eu> 5185f7d9aSMichal Simek * 6185f7d9aSMichal Simek * Based on Xilinx gmac driver: 7185f7d9aSMichal Simek * (C) Copyright 2011 Xilinx 8185f7d9aSMichal Simek * 9185f7d9aSMichal Simek * See file CREDITS for list of people who contributed to this 10185f7d9aSMichal Simek * project. 11185f7d9aSMichal Simek * 12185f7d9aSMichal Simek * This program is free software; you can redistribute it and/or 13185f7d9aSMichal Simek * modify it under the terms of the GNU General Public License as 14185f7d9aSMichal Simek * published by the Free Software Foundation; either version 2 of 15185f7d9aSMichal Simek * the License, or (at your option) any later version. 16185f7d9aSMichal Simek * 17185f7d9aSMichal Simek * This program is distributed in the hope that it will be useful, 18185f7d9aSMichal Simek * but WITHOUT ANY WARRANTY; without even the implied warranty of 19185f7d9aSMichal Simek * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20185f7d9aSMichal Simek * GNU General Public License for more details. 21185f7d9aSMichal Simek * 22185f7d9aSMichal Simek * You should have received a copy of the GNU General Public License 23185f7d9aSMichal Simek * along with this program; if not, write to the Free Software 24185f7d9aSMichal Simek * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25185f7d9aSMichal Simek * MA 02111-1307 USA 26185f7d9aSMichal Simek */ 27185f7d9aSMichal Simek 28185f7d9aSMichal Simek #include <common.h> 29185f7d9aSMichal Simek #include <net.h> 30185f7d9aSMichal Simek #include <config.h> 31185f7d9aSMichal Simek #include <malloc.h> 32185f7d9aSMichal Simek #include <asm/io.h> 33185f7d9aSMichal Simek #include <phy.h> 34185f7d9aSMichal Simek #include <miiphy.h> 35185f7d9aSMichal Simek #include <watchdog.h> 36*80243528SMichal Simek #include <asm/arch/sys_proto.h> 37185f7d9aSMichal Simek 38185f7d9aSMichal Simek #if !defined(CONFIG_PHYLIB) 39185f7d9aSMichal Simek # error XILINX_GEM_ETHERNET requires PHYLIB 40185f7d9aSMichal Simek #endif 41185f7d9aSMichal Simek 42185f7d9aSMichal Simek /* Bit/mask specification */ 43185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 44185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 45185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 46185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 47185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 48185f7d9aSMichal Simek 49185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 50185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 51185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 52185f7d9aSMichal Simek 53185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 54185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 55185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 56185f7d9aSMichal Simek 57185f7d9aSMichal Simek /* Wrap bit, last descriptor */ 58185f7d9aSMichal Simek #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 59185f7d9aSMichal Simek #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 60185f7d9aSMichal Simek 61185f7d9aSMichal Simek #define ZYNQ_GEM_TXSR_HRESPNOK_MASK 0x00000100 /* Transmit hresp not OK */ 62185f7d9aSMichal Simek #define ZYNQ_GEM_TXSR_URUN_MASK 0x00000040 /* Transmit underrun */ 63185f7d9aSMichal Simek /* Transmit buffs exhausted mid frame */ 64185f7d9aSMichal Simek #define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x00000010 65185f7d9aSMichal Simek 66185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 67185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 68185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 69185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 70185f7d9aSMichal Simek 71*80243528SMichal Simek #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 72*80243528SMichal Simek #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 73*80243528SMichal Simek #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 74*80243528SMichal Simek #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 75185f7d9aSMichal Simek #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ 76*80243528SMichal Simek #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ 77185f7d9aSMichal Simek 78*80243528SMichal Simek #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \ 79185f7d9aSMichal Simek ZYNQ_GEM_NWCFG_FSREM | \ 80185f7d9aSMichal Simek ZYNQ_GEM_NWCFG_MDCCLKDIV) 81185f7d9aSMichal Simek 82185f7d9aSMichal Simek #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 83185f7d9aSMichal Simek 84185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 85185f7d9aSMichal Simek /* Use full configured addressable space (8 Kb) */ 86185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 87185f7d9aSMichal Simek /* Use full configured addressable space (4 Kb) */ 88185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 89185f7d9aSMichal Simek /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 90185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 91185f7d9aSMichal Simek 92185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 93185f7d9aSMichal Simek ZYNQ_GEM_DMACR_RXSIZE | \ 94185f7d9aSMichal Simek ZYNQ_GEM_DMACR_TXSIZE | \ 95185f7d9aSMichal Simek ZYNQ_GEM_DMACR_RXBUF) 96185f7d9aSMichal Simek 97185f7d9aSMichal Simek /* Device registers */ 98185f7d9aSMichal Simek struct zynq_gem_regs { 99185f7d9aSMichal Simek u32 nwctrl; /* Network Control reg */ 100185f7d9aSMichal Simek u32 nwcfg; /* Network Config reg */ 101185f7d9aSMichal Simek u32 nwsr; /* Network Status reg */ 102185f7d9aSMichal Simek u32 reserved1; 103185f7d9aSMichal Simek u32 dmacr; /* DMA Control reg */ 104185f7d9aSMichal Simek u32 txsr; /* TX Status reg */ 105185f7d9aSMichal Simek u32 rxqbase; /* RX Q Base address reg */ 106185f7d9aSMichal Simek u32 txqbase; /* TX Q Base address reg */ 107185f7d9aSMichal Simek u32 rxsr; /* RX Status reg */ 108185f7d9aSMichal Simek u32 reserved2[2]; 109185f7d9aSMichal Simek u32 idr; /* Interrupt Disable reg */ 110185f7d9aSMichal Simek u32 reserved3; 111185f7d9aSMichal Simek u32 phymntnc; /* Phy Maintaince reg */ 112185f7d9aSMichal Simek u32 reserved4[18]; 113185f7d9aSMichal Simek u32 hashl; /* Hash Low address reg */ 114185f7d9aSMichal Simek u32 hashh; /* Hash High address reg */ 115185f7d9aSMichal Simek #define LADDR_LOW 0 116185f7d9aSMichal Simek #define LADDR_HIGH 1 117185f7d9aSMichal Simek u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */ 118185f7d9aSMichal Simek u32 match[4]; /* Type ID1 Match reg */ 119185f7d9aSMichal Simek u32 reserved6[18]; 120185f7d9aSMichal Simek u32 stat[44]; /* Octects transmitted Low reg - stat start */ 121185f7d9aSMichal Simek }; 122185f7d9aSMichal Simek 123185f7d9aSMichal Simek /* BD descriptors */ 124185f7d9aSMichal Simek struct emac_bd { 125185f7d9aSMichal Simek u32 addr; /* Next descriptor pointer */ 126185f7d9aSMichal Simek u32 status; 127185f7d9aSMichal Simek }; 128185f7d9aSMichal Simek 129185f7d9aSMichal Simek #define RX_BUF 3 130185f7d9aSMichal Simek 131185f7d9aSMichal Simek /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 132185f7d9aSMichal Simek struct zynq_gem_priv { 133185f7d9aSMichal Simek struct emac_bd tx_bd; 134185f7d9aSMichal Simek struct emac_bd rx_bd[RX_BUF]; 135185f7d9aSMichal Simek char rxbuffers[RX_BUF * PKTSIZE_ALIGN]; 136185f7d9aSMichal Simek u32 rxbd_current; 137185f7d9aSMichal Simek u32 rx_first_buf; 138185f7d9aSMichal Simek int phyaddr; 13905868759SMichal Simek int init; 140185f7d9aSMichal Simek struct phy_device *phydev; 141185f7d9aSMichal Simek struct mii_dev *bus; 142185f7d9aSMichal Simek }; 143185f7d9aSMichal Simek 144185f7d9aSMichal Simek static inline int mdio_wait(struct eth_device *dev) 145185f7d9aSMichal Simek { 146185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 147185f7d9aSMichal Simek u32 timeout = 200; 148185f7d9aSMichal Simek 149185f7d9aSMichal Simek /* Wait till MDIO interface is ready to accept a new transaction. */ 150185f7d9aSMichal Simek while (--timeout) { 151185f7d9aSMichal Simek if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 152185f7d9aSMichal Simek break; 153185f7d9aSMichal Simek WATCHDOG_RESET(); 154185f7d9aSMichal Simek } 155185f7d9aSMichal Simek 156185f7d9aSMichal Simek if (!timeout) { 157185f7d9aSMichal Simek printf("%s: Timeout\n", __func__); 158185f7d9aSMichal Simek return 1; 159185f7d9aSMichal Simek } 160185f7d9aSMichal Simek 161185f7d9aSMichal Simek return 0; 162185f7d9aSMichal Simek } 163185f7d9aSMichal Simek 164185f7d9aSMichal Simek static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, 165185f7d9aSMichal Simek u32 op, u16 *data) 166185f7d9aSMichal Simek { 167185f7d9aSMichal Simek u32 mgtcr; 168185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 169185f7d9aSMichal Simek 170185f7d9aSMichal Simek if (mdio_wait(dev)) 171185f7d9aSMichal Simek return 1; 172185f7d9aSMichal Simek 173185f7d9aSMichal Simek /* Construct mgtcr mask for the operation */ 174185f7d9aSMichal Simek mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 175185f7d9aSMichal Simek (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 176185f7d9aSMichal Simek (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 177185f7d9aSMichal Simek 178185f7d9aSMichal Simek /* Write mgtcr and wait for completion */ 179185f7d9aSMichal Simek writel(mgtcr, ®s->phymntnc); 180185f7d9aSMichal Simek 181185f7d9aSMichal Simek if (mdio_wait(dev)) 182185f7d9aSMichal Simek return 1; 183185f7d9aSMichal Simek 184185f7d9aSMichal Simek if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 185185f7d9aSMichal Simek *data = readl(®s->phymntnc); 186185f7d9aSMichal Simek 187185f7d9aSMichal Simek return 0; 188185f7d9aSMichal Simek } 189185f7d9aSMichal Simek 190185f7d9aSMichal Simek static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) 191185f7d9aSMichal Simek { 192185f7d9aSMichal Simek return phy_setup_op(dev, phy_addr, regnum, 193185f7d9aSMichal Simek ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 194185f7d9aSMichal Simek } 195185f7d9aSMichal Simek 196185f7d9aSMichal Simek static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) 197185f7d9aSMichal Simek { 198185f7d9aSMichal Simek return phy_setup_op(dev, phy_addr, regnum, 199185f7d9aSMichal Simek ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 200185f7d9aSMichal Simek } 201185f7d9aSMichal Simek 202185f7d9aSMichal Simek static int zynq_gem_setup_mac(struct eth_device *dev) 203185f7d9aSMichal Simek { 204185f7d9aSMichal Simek u32 i, macaddrlow, macaddrhigh; 205185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 206185f7d9aSMichal Simek 207185f7d9aSMichal Simek /* Set the MAC bits [31:0] in BOT */ 208185f7d9aSMichal Simek macaddrlow = dev->enetaddr[0]; 209185f7d9aSMichal Simek macaddrlow |= dev->enetaddr[1] << 8; 210185f7d9aSMichal Simek macaddrlow |= dev->enetaddr[2] << 16; 211185f7d9aSMichal Simek macaddrlow |= dev->enetaddr[3] << 24; 212185f7d9aSMichal Simek 213185f7d9aSMichal Simek /* Set MAC bits [47:32] in TOP */ 214185f7d9aSMichal Simek macaddrhigh = dev->enetaddr[4]; 215185f7d9aSMichal Simek macaddrhigh |= dev->enetaddr[5] << 8; 216185f7d9aSMichal Simek 217185f7d9aSMichal Simek for (i = 0; i < 4; i++) { 218185f7d9aSMichal Simek writel(0, ®s->laddr[i][LADDR_LOW]); 219185f7d9aSMichal Simek writel(0, ®s->laddr[i][LADDR_HIGH]); 220185f7d9aSMichal Simek /* Do not use MATCHx register */ 221185f7d9aSMichal Simek writel(0, ®s->match[i]); 222185f7d9aSMichal Simek } 223185f7d9aSMichal Simek 224185f7d9aSMichal Simek writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 225185f7d9aSMichal Simek writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 226185f7d9aSMichal Simek 227185f7d9aSMichal Simek return 0; 228185f7d9aSMichal Simek } 229185f7d9aSMichal Simek 230185f7d9aSMichal Simek static int zynq_gem_init(struct eth_device *dev, bd_t * bis) 231185f7d9aSMichal Simek { 232*80243528SMichal Simek u32 i, rclk, clk = 0; 233185f7d9aSMichal Simek struct phy_device *phydev; 234185f7d9aSMichal Simek const u32 stat_size = (sizeof(struct zynq_gem_regs) - 235185f7d9aSMichal Simek offsetof(struct zynq_gem_regs, stat)) / 4; 236185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 237185f7d9aSMichal Simek struct zynq_gem_priv *priv = dev->priv; 238185f7d9aSMichal Simek const u32 supported = SUPPORTED_10baseT_Half | 239185f7d9aSMichal Simek SUPPORTED_10baseT_Full | 240185f7d9aSMichal Simek SUPPORTED_100baseT_Half | 241185f7d9aSMichal Simek SUPPORTED_100baseT_Full | 242185f7d9aSMichal Simek SUPPORTED_1000baseT_Half | 243185f7d9aSMichal Simek SUPPORTED_1000baseT_Full; 244185f7d9aSMichal Simek 24505868759SMichal Simek if (!priv->init) { 246185f7d9aSMichal Simek /* Disable all interrupts */ 247185f7d9aSMichal Simek writel(0xFFFFFFFF, ®s->idr); 248185f7d9aSMichal Simek 249185f7d9aSMichal Simek /* Disable the receiver & transmitter */ 250185f7d9aSMichal Simek writel(0, ®s->nwctrl); 251185f7d9aSMichal Simek writel(0, ®s->txsr); 252185f7d9aSMichal Simek writel(0, ®s->rxsr); 253185f7d9aSMichal Simek writel(0, ®s->phymntnc); 254185f7d9aSMichal Simek 25505868759SMichal Simek /* Clear the Hash registers for the mac address 25605868759SMichal Simek * pointed by AddressPtr 25705868759SMichal Simek */ 258185f7d9aSMichal Simek writel(0x0, ®s->hashl); 259185f7d9aSMichal Simek /* Write bits [63:32] in TOP */ 260185f7d9aSMichal Simek writel(0x0, ®s->hashh); 261185f7d9aSMichal Simek 262185f7d9aSMichal Simek /* Clear all counters */ 263185f7d9aSMichal Simek for (i = 0; i <= stat_size; i++) 264185f7d9aSMichal Simek readl(®s->stat[i]); 265185f7d9aSMichal Simek 266185f7d9aSMichal Simek /* Setup RxBD space */ 267185f7d9aSMichal Simek memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd)); 268185f7d9aSMichal Simek /* Create the RxBD ring */ 269185f7d9aSMichal Simek memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers)); 270185f7d9aSMichal Simek 271185f7d9aSMichal Simek for (i = 0; i < RX_BUF; i++) { 272185f7d9aSMichal Simek priv->rx_bd[i].status = 0xF0000000; 27305868759SMichal Simek priv->rx_bd[i].addr = 27405868759SMichal Simek (u32)((char *)&(priv->rxbuffers) + 275185f7d9aSMichal Simek (i * PKTSIZE_ALIGN)); 276185f7d9aSMichal Simek } 277185f7d9aSMichal Simek /* WRAP bit to last BD */ 278185f7d9aSMichal Simek priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 279185f7d9aSMichal Simek /* Write RxBDs to IP */ 280185f7d9aSMichal Simek writel((u32)&(priv->rx_bd), ®s->rxqbase); 281185f7d9aSMichal Simek 282185f7d9aSMichal Simek /* Setup for DMA Configuration register */ 283185f7d9aSMichal Simek writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 284185f7d9aSMichal Simek 285185f7d9aSMichal Simek /* Setup for Network Control register, MDIO, Rx and Tx enable */ 286*80243528SMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 287185f7d9aSMichal Simek 28805868759SMichal Simek priv->init++; 28905868759SMichal Simek } 29005868759SMichal Simek 291185f7d9aSMichal Simek /* interface - look at tsec */ 292185f7d9aSMichal Simek phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); 293185f7d9aSMichal Simek 294*80243528SMichal Simek phydev->supported = supported | ADVERTISED_Pause | 295*80243528SMichal Simek ADVERTISED_Asym_Pause; 296185f7d9aSMichal Simek phydev->advertising = phydev->supported; 297185f7d9aSMichal Simek priv->phydev = phydev; 298185f7d9aSMichal Simek phy_config(phydev); 299185f7d9aSMichal Simek phy_startup(phydev); 300185f7d9aSMichal Simek 301*80243528SMichal Simek switch (phydev->speed) { 302*80243528SMichal Simek case SPEED_1000: 303*80243528SMichal Simek writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 304*80243528SMichal Simek ®s->nwcfg); 305*80243528SMichal Simek rclk = (0 << 4) | (1 << 0); 306*80243528SMichal Simek clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0); 307*80243528SMichal Simek break; 308*80243528SMichal Simek case SPEED_100: 309*80243528SMichal Simek clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, 310*80243528SMichal Simek ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); 311*80243528SMichal Simek rclk = 1 << 0; 312*80243528SMichal Simek clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); 313*80243528SMichal Simek break; 314*80243528SMichal Simek case SPEED_10: 315*80243528SMichal Simek rclk = 1 << 0; 316*80243528SMichal Simek /* FIXME untested */ 317*80243528SMichal Simek clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); 318*80243528SMichal Simek break; 319*80243528SMichal Simek } 320*80243528SMichal Simek /* FIXME maybe better to define gem address in hardware.h */ 321*80243528SMichal Simek zynq_slcr_gem_clk_setup(dev->iobase != 0xE000B000, rclk, clk); 322*80243528SMichal Simek 323*80243528SMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 324*80243528SMichal Simek ZYNQ_GEM_NWCTRL_TXEN_MASK); 325*80243528SMichal Simek 326185f7d9aSMichal Simek return 0; 327185f7d9aSMichal Simek } 328185f7d9aSMichal Simek 329185f7d9aSMichal Simek static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) 330185f7d9aSMichal Simek { 331185f7d9aSMichal Simek u32 status; 332185f7d9aSMichal Simek struct zynq_gem_priv *priv = dev->priv; 333185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 334185f7d9aSMichal Simek const u32 mask = ZYNQ_GEM_TXSR_HRESPNOK_MASK | \ 335185f7d9aSMichal Simek ZYNQ_GEM_TXSR_URUN_MASK | ZYNQ_GEM_TXSR_BUFEXH_MASK; 336185f7d9aSMichal Simek 337185f7d9aSMichal Simek /* setup BD */ 338185f7d9aSMichal Simek writel((u32)&(priv->tx_bd), ®s->txqbase); 339185f7d9aSMichal Simek 340185f7d9aSMichal Simek /* Setup Tx BD */ 341185f7d9aSMichal Simek memset((void *)&(priv->tx_bd), 0, sizeof(struct emac_bd)); 342185f7d9aSMichal Simek 343185f7d9aSMichal Simek priv->tx_bd.addr = (u32)ptr; 344986f0000SMichal Simek priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK; 345185f7d9aSMichal Simek 346185f7d9aSMichal Simek /* Start transmit */ 347185f7d9aSMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 348185f7d9aSMichal Simek 349185f7d9aSMichal Simek /* Read the stat register to know if the packet has been transmitted */ 350185f7d9aSMichal Simek status = readl(®s->txsr); 351185f7d9aSMichal Simek if (status & mask) 352185f7d9aSMichal Simek printf("Something has gone wrong here!? Status is 0x%x.\n", 353185f7d9aSMichal Simek status); 354185f7d9aSMichal Simek 355185f7d9aSMichal Simek /* Clear Tx status register before leaving . */ 356185f7d9aSMichal Simek writel(status, ®s->txsr); 357185f7d9aSMichal Simek return 0; 358185f7d9aSMichal Simek } 359185f7d9aSMichal Simek 360185f7d9aSMichal Simek /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 361185f7d9aSMichal Simek static int zynq_gem_recv(struct eth_device *dev) 362185f7d9aSMichal Simek { 363185f7d9aSMichal Simek int frame_len; 364185f7d9aSMichal Simek struct zynq_gem_priv *priv = dev->priv; 365185f7d9aSMichal Simek struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 366185f7d9aSMichal Simek struct emac_bd *first_bd; 367185f7d9aSMichal Simek 368185f7d9aSMichal Simek if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 369185f7d9aSMichal Simek return 0; 370185f7d9aSMichal Simek 371185f7d9aSMichal Simek if (!(current_bd->status & 372185f7d9aSMichal Simek (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 373185f7d9aSMichal Simek printf("GEM: SOF or EOF not set for last buffer received!\n"); 374185f7d9aSMichal Simek return 0; 375185f7d9aSMichal Simek } 376185f7d9aSMichal Simek 377185f7d9aSMichal Simek frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 378185f7d9aSMichal Simek if (frame_len) { 379185f7d9aSMichal Simek NetReceive((u8 *) (current_bd->addr & 380185f7d9aSMichal Simek ZYNQ_GEM_RXBUF_ADD_MASK), frame_len); 381185f7d9aSMichal Simek 382185f7d9aSMichal Simek if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 383185f7d9aSMichal Simek priv->rx_first_buf = priv->rxbd_current; 384185f7d9aSMichal Simek else { 385185f7d9aSMichal Simek current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 386185f7d9aSMichal Simek current_bd->status = 0xF0000000; /* FIXME */ 387185f7d9aSMichal Simek } 388185f7d9aSMichal Simek 389185f7d9aSMichal Simek if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 390185f7d9aSMichal Simek first_bd = &priv->rx_bd[priv->rx_first_buf]; 391185f7d9aSMichal Simek first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 392185f7d9aSMichal Simek first_bd->status = 0xF0000000; 393185f7d9aSMichal Simek } 394185f7d9aSMichal Simek 395185f7d9aSMichal Simek if ((++priv->rxbd_current) >= RX_BUF) 396185f7d9aSMichal Simek priv->rxbd_current = 0; 397185f7d9aSMichal Simek } 398185f7d9aSMichal Simek 3993b90d0afSMichal Simek return frame_len; 400185f7d9aSMichal Simek } 401185f7d9aSMichal Simek 402185f7d9aSMichal Simek static void zynq_gem_halt(struct eth_device *dev) 403185f7d9aSMichal Simek { 404185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 405185f7d9aSMichal Simek 406*80243528SMichal Simek clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 407*80243528SMichal Simek ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 408185f7d9aSMichal Simek } 409185f7d9aSMichal Simek 410185f7d9aSMichal Simek static int zynq_gem_miiphyread(const char *devname, uchar addr, 411185f7d9aSMichal Simek uchar reg, ushort *val) 412185f7d9aSMichal Simek { 413185f7d9aSMichal Simek struct eth_device *dev = eth_get_dev(); 414185f7d9aSMichal Simek int ret; 415185f7d9aSMichal Simek 416185f7d9aSMichal Simek ret = phyread(dev, addr, reg, val); 417185f7d9aSMichal Simek debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); 418185f7d9aSMichal Simek return ret; 419185f7d9aSMichal Simek } 420185f7d9aSMichal Simek 421185f7d9aSMichal Simek static int zynq_gem_miiphy_write(const char *devname, uchar addr, 422185f7d9aSMichal Simek uchar reg, ushort val) 423185f7d9aSMichal Simek { 424185f7d9aSMichal Simek struct eth_device *dev = eth_get_dev(); 425185f7d9aSMichal Simek 426185f7d9aSMichal Simek debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); 427185f7d9aSMichal Simek return phywrite(dev, addr, reg, val); 428185f7d9aSMichal Simek } 429185f7d9aSMichal Simek 430185f7d9aSMichal Simek int zynq_gem_initialize(bd_t *bis, int base_addr) 431185f7d9aSMichal Simek { 432185f7d9aSMichal Simek struct eth_device *dev; 433185f7d9aSMichal Simek struct zynq_gem_priv *priv; 434185f7d9aSMichal Simek 435185f7d9aSMichal Simek dev = calloc(1, sizeof(*dev)); 436185f7d9aSMichal Simek if (dev == NULL) 437185f7d9aSMichal Simek return -1; 438185f7d9aSMichal Simek 439185f7d9aSMichal Simek dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); 440185f7d9aSMichal Simek if (dev->priv == NULL) { 441185f7d9aSMichal Simek free(dev); 442185f7d9aSMichal Simek return -1; 443185f7d9aSMichal Simek } 444185f7d9aSMichal Simek priv = dev->priv; 445185f7d9aSMichal Simek 446185f7d9aSMichal Simek #ifdef CONFIG_PHY_ADDR 447185f7d9aSMichal Simek priv->phyaddr = CONFIG_PHY_ADDR; 448185f7d9aSMichal Simek #else 449185f7d9aSMichal Simek priv->phyaddr = -1; 450185f7d9aSMichal Simek #endif 451185f7d9aSMichal Simek 452185f7d9aSMichal Simek sprintf(dev->name, "Gem.%x", base_addr); 453185f7d9aSMichal Simek 454185f7d9aSMichal Simek dev->iobase = base_addr; 455185f7d9aSMichal Simek 456185f7d9aSMichal Simek dev->init = zynq_gem_init; 457185f7d9aSMichal Simek dev->halt = zynq_gem_halt; 458185f7d9aSMichal Simek dev->send = zynq_gem_send; 459185f7d9aSMichal Simek dev->recv = zynq_gem_recv; 460185f7d9aSMichal Simek dev->write_hwaddr = zynq_gem_setup_mac; 461185f7d9aSMichal Simek 462185f7d9aSMichal Simek eth_register(dev); 463185f7d9aSMichal Simek 464185f7d9aSMichal Simek miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); 465185f7d9aSMichal Simek priv->bus = miiphy_get_dev_by_name(dev->name); 466185f7d9aSMichal Simek 467185f7d9aSMichal Simek return 1; 468185f7d9aSMichal Simek } 469