1185f7d9aSMichal Simek /* 2185f7d9aSMichal Simek * (C) Copyright 2011 Michal Simek 3185f7d9aSMichal Simek * 4185f7d9aSMichal Simek * Michal SIMEK <monstr@monstr.eu> 5185f7d9aSMichal Simek * 6185f7d9aSMichal Simek * Based on Xilinx gmac driver: 7185f7d9aSMichal Simek * (C) Copyright 2011 Xilinx 8185f7d9aSMichal Simek * 91a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 10185f7d9aSMichal Simek */ 11185f7d9aSMichal Simek 12185f7d9aSMichal Simek #include <common.h> 13185f7d9aSMichal Simek #include <net.h> 142fd2489bSMichal Simek #include <netdev.h> 15185f7d9aSMichal Simek #include <config.h> 16f88a6869SMichal Simek #include <fdtdec.h> 17f88a6869SMichal Simek #include <libfdt.h> 18185f7d9aSMichal Simek #include <malloc.h> 19185f7d9aSMichal Simek #include <asm/io.h> 20185f7d9aSMichal Simek #include <phy.h> 21185f7d9aSMichal Simek #include <miiphy.h> 22185f7d9aSMichal Simek #include <watchdog.h> 2301fbf310SDavid Andrey #include <asm/arch/hardware.h> 2480243528SMichal Simek #include <asm/arch/sys_proto.h> 25185f7d9aSMichal Simek 26185f7d9aSMichal Simek #if !defined(CONFIG_PHYLIB) 27185f7d9aSMichal Simek # error XILINX_GEM_ETHERNET requires PHYLIB 28185f7d9aSMichal Simek #endif 29185f7d9aSMichal Simek 30185f7d9aSMichal Simek /* Bit/mask specification */ 31185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 32185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 33185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 34185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 35185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 36185f7d9aSMichal Simek 37185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 38185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 39185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 40185f7d9aSMichal Simek 41185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 42185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 43185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 44185f7d9aSMichal Simek 45185f7d9aSMichal Simek /* Wrap bit, last descriptor */ 46185f7d9aSMichal Simek #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 47185f7d9aSMichal Simek #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 48185f7d9aSMichal Simek 49185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 50185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 51185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 52185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 53185f7d9aSMichal Simek 5480243528SMichal Simek #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 5580243528SMichal Simek #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 5680243528SMichal Simek #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 5780243528SMichal Simek #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 58185f7d9aSMichal Simek #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ 5980243528SMichal Simek #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ 60185f7d9aSMichal Simek 6180243528SMichal Simek #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \ 62185f7d9aSMichal Simek ZYNQ_GEM_NWCFG_FSREM | \ 63185f7d9aSMichal Simek ZYNQ_GEM_NWCFG_MDCCLKDIV) 64185f7d9aSMichal Simek 65185f7d9aSMichal Simek #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 66185f7d9aSMichal Simek 67185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 68185f7d9aSMichal Simek /* Use full configured addressable space (8 Kb) */ 69185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 70185f7d9aSMichal Simek /* Use full configured addressable space (4 Kb) */ 71185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 72185f7d9aSMichal Simek /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 73185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 74185f7d9aSMichal Simek 75185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 76185f7d9aSMichal Simek ZYNQ_GEM_DMACR_RXSIZE | \ 77185f7d9aSMichal Simek ZYNQ_GEM_DMACR_TXSIZE | \ 78185f7d9aSMichal Simek ZYNQ_GEM_DMACR_RXBUF) 79185f7d9aSMichal Simek 80f97d7e8bSMichal Simek /* Use MII register 1 (MII status register) to detect PHY */ 81f97d7e8bSMichal Simek #define PHY_DETECT_REG 1 82f97d7e8bSMichal Simek 83f97d7e8bSMichal Simek /* Mask used to verify certain PHY features (or register contents) 84f97d7e8bSMichal Simek * in the register above: 85f97d7e8bSMichal Simek * 0x1000: 10Mbps full duplex support 86f97d7e8bSMichal Simek * 0x0800: 10Mbps half duplex support 87f97d7e8bSMichal Simek * 0x0008: Auto-negotiation support 88f97d7e8bSMichal Simek */ 89f97d7e8bSMichal Simek #define PHY_DETECT_MASK 0x1808 90f97d7e8bSMichal Simek 91a5144237SSrikanth Thokala /* TX BD status masks */ 92a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 93a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 94a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 95a5144237SSrikanth Thokala 9697598fcfSSoren Brinkmann /* Clock frequencies for different speeds */ 9797598fcfSSoren Brinkmann #define ZYNQ_GEM_FREQUENCY_10 2500000UL 9897598fcfSSoren Brinkmann #define ZYNQ_GEM_FREQUENCY_100 25000000UL 9997598fcfSSoren Brinkmann #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 10097598fcfSSoren Brinkmann 101185f7d9aSMichal Simek /* Device registers */ 102185f7d9aSMichal Simek struct zynq_gem_regs { 103185f7d9aSMichal Simek u32 nwctrl; /* Network Control reg */ 104185f7d9aSMichal Simek u32 nwcfg; /* Network Config reg */ 105185f7d9aSMichal Simek u32 nwsr; /* Network Status reg */ 106185f7d9aSMichal Simek u32 reserved1; 107185f7d9aSMichal Simek u32 dmacr; /* DMA Control reg */ 108185f7d9aSMichal Simek u32 txsr; /* TX Status reg */ 109185f7d9aSMichal Simek u32 rxqbase; /* RX Q Base address reg */ 110185f7d9aSMichal Simek u32 txqbase; /* TX Q Base address reg */ 111185f7d9aSMichal Simek u32 rxsr; /* RX Status reg */ 112185f7d9aSMichal Simek u32 reserved2[2]; 113185f7d9aSMichal Simek u32 idr; /* Interrupt Disable reg */ 114185f7d9aSMichal Simek u32 reserved3; 115185f7d9aSMichal Simek u32 phymntnc; /* Phy Maintaince reg */ 116185f7d9aSMichal Simek u32 reserved4[18]; 117185f7d9aSMichal Simek u32 hashl; /* Hash Low address reg */ 118185f7d9aSMichal Simek u32 hashh; /* Hash High address reg */ 119185f7d9aSMichal Simek #define LADDR_LOW 0 120185f7d9aSMichal Simek #define LADDR_HIGH 1 121185f7d9aSMichal Simek u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */ 122185f7d9aSMichal Simek u32 match[4]; /* Type ID1 Match reg */ 123185f7d9aSMichal Simek u32 reserved6[18]; 124185f7d9aSMichal Simek u32 stat[44]; /* Octects transmitted Low reg - stat start */ 125185f7d9aSMichal Simek }; 126185f7d9aSMichal Simek 127185f7d9aSMichal Simek /* BD descriptors */ 128185f7d9aSMichal Simek struct emac_bd { 129185f7d9aSMichal Simek u32 addr; /* Next descriptor pointer */ 130185f7d9aSMichal Simek u32 status; 131185f7d9aSMichal Simek }; 132185f7d9aSMichal Simek 133185f7d9aSMichal Simek #define RX_BUF 3 134a5144237SSrikanth Thokala /* Page table entries are set to 1MB, or multiples of 1MB 135a5144237SSrikanth Thokala * (not < 1MB). driver uses less bd's so use 1MB bdspace. 136a5144237SSrikanth Thokala */ 137a5144237SSrikanth Thokala #define BD_SPACE 0x100000 138a5144237SSrikanth Thokala /* BD separation space */ 139a5144237SSrikanth Thokala #define BD_SEPRN_SPACE 64 140185f7d9aSMichal Simek 141185f7d9aSMichal Simek /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 142185f7d9aSMichal Simek struct zynq_gem_priv { 143a5144237SSrikanth Thokala struct emac_bd *tx_bd; 144a5144237SSrikanth Thokala struct emac_bd *rx_bd; 145a5144237SSrikanth Thokala char *rxbuffers; 146185f7d9aSMichal Simek u32 rxbd_current; 147185f7d9aSMichal Simek u32 rx_first_buf; 148185f7d9aSMichal Simek int phyaddr; 14901fbf310SDavid Andrey u32 emio; 15005868759SMichal Simek int init; 151185f7d9aSMichal Simek struct phy_device *phydev; 152185f7d9aSMichal Simek struct mii_dev *bus; 153185f7d9aSMichal Simek }; 154185f7d9aSMichal Simek 155185f7d9aSMichal Simek static inline int mdio_wait(struct eth_device *dev) 156185f7d9aSMichal Simek { 157185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 158185f7d9aSMichal Simek u32 timeout = 200; 159185f7d9aSMichal Simek 160185f7d9aSMichal Simek /* Wait till MDIO interface is ready to accept a new transaction. */ 161185f7d9aSMichal Simek while (--timeout) { 162185f7d9aSMichal Simek if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 163185f7d9aSMichal Simek break; 164185f7d9aSMichal Simek WATCHDOG_RESET(); 165185f7d9aSMichal Simek } 166185f7d9aSMichal Simek 167185f7d9aSMichal Simek if (!timeout) { 168185f7d9aSMichal Simek printf("%s: Timeout\n", __func__); 169185f7d9aSMichal Simek return 1; 170185f7d9aSMichal Simek } 171185f7d9aSMichal Simek 172185f7d9aSMichal Simek return 0; 173185f7d9aSMichal Simek } 174185f7d9aSMichal Simek 175185f7d9aSMichal Simek static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, 176185f7d9aSMichal Simek u32 op, u16 *data) 177185f7d9aSMichal Simek { 178185f7d9aSMichal Simek u32 mgtcr; 179185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 180185f7d9aSMichal Simek 181185f7d9aSMichal Simek if (mdio_wait(dev)) 182185f7d9aSMichal Simek return 1; 183185f7d9aSMichal Simek 184185f7d9aSMichal Simek /* Construct mgtcr mask for the operation */ 185185f7d9aSMichal Simek mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 186185f7d9aSMichal Simek (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 187185f7d9aSMichal Simek (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 188185f7d9aSMichal Simek 189185f7d9aSMichal Simek /* Write mgtcr and wait for completion */ 190185f7d9aSMichal Simek writel(mgtcr, ®s->phymntnc); 191185f7d9aSMichal Simek 192185f7d9aSMichal Simek if (mdio_wait(dev)) 193185f7d9aSMichal Simek return 1; 194185f7d9aSMichal Simek 195185f7d9aSMichal Simek if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 196185f7d9aSMichal Simek *data = readl(®s->phymntnc); 197185f7d9aSMichal Simek 198185f7d9aSMichal Simek return 0; 199185f7d9aSMichal Simek } 200185f7d9aSMichal Simek 201185f7d9aSMichal Simek static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) 202185f7d9aSMichal Simek { 203185f7d9aSMichal Simek return phy_setup_op(dev, phy_addr, regnum, 204185f7d9aSMichal Simek ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 205185f7d9aSMichal Simek } 206185f7d9aSMichal Simek 207185f7d9aSMichal Simek static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) 208185f7d9aSMichal Simek { 209185f7d9aSMichal Simek return phy_setup_op(dev, phy_addr, regnum, 210185f7d9aSMichal Simek ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 211185f7d9aSMichal Simek } 212185f7d9aSMichal Simek 213f97d7e8bSMichal Simek static void phy_detection(struct eth_device *dev) 214f97d7e8bSMichal Simek { 215f97d7e8bSMichal Simek int i; 216f97d7e8bSMichal Simek u16 phyreg; 217f97d7e8bSMichal Simek struct zynq_gem_priv *priv = dev->priv; 218f97d7e8bSMichal Simek 219f97d7e8bSMichal Simek if (priv->phyaddr != -1) { 220f97d7e8bSMichal Simek phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); 221f97d7e8bSMichal Simek if ((phyreg != 0xFFFF) && 222f97d7e8bSMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 223f97d7e8bSMichal Simek /* Found a valid PHY address */ 224f97d7e8bSMichal Simek debug("Default phy address %d is valid\n", 225f97d7e8bSMichal Simek priv->phyaddr); 226f97d7e8bSMichal Simek return; 227f97d7e8bSMichal Simek } else { 228f97d7e8bSMichal Simek debug("PHY address is not setup correctly %d\n", 229f97d7e8bSMichal Simek priv->phyaddr); 230f97d7e8bSMichal Simek priv->phyaddr = -1; 231f97d7e8bSMichal Simek } 232f97d7e8bSMichal Simek } 233f97d7e8bSMichal Simek 234f97d7e8bSMichal Simek debug("detecting phy address\n"); 235f97d7e8bSMichal Simek if (priv->phyaddr == -1) { 236f97d7e8bSMichal Simek /* detect the PHY address */ 237f97d7e8bSMichal Simek for (i = 31; i >= 0; i--) { 238f97d7e8bSMichal Simek phyread(dev, i, PHY_DETECT_REG, &phyreg); 239f97d7e8bSMichal Simek if ((phyreg != 0xFFFF) && 240f97d7e8bSMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 241f97d7e8bSMichal Simek /* Found a valid PHY address */ 242f97d7e8bSMichal Simek priv->phyaddr = i; 243f97d7e8bSMichal Simek debug("Found valid phy address, %d\n", i); 244f97d7e8bSMichal Simek return; 245f97d7e8bSMichal Simek } 246f97d7e8bSMichal Simek } 247f97d7e8bSMichal Simek } 248f97d7e8bSMichal Simek printf("PHY is not detected\n"); 249f97d7e8bSMichal Simek } 250f97d7e8bSMichal Simek 251185f7d9aSMichal Simek static int zynq_gem_setup_mac(struct eth_device *dev) 252185f7d9aSMichal Simek { 253185f7d9aSMichal Simek u32 i, macaddrlow, macaddrhigh; 254185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 255185f7d9aSMichal Simek 256185f7d9aSMichal Simek /* Set the MAC bits [31:0] in BOT */ 257185f7d9aSMichal Simek macaddrlow = dev->enetaddr[0]; 258185f7d9aSMichal Simek macaddrlow |= dev->enetaddr[1] << 8; 259185f7d9aSMichal Simek macaddrlow |= dev->enetaddr[2] << 16; 260185f7d9aSMichal Simek macaddrlow |= dev->enetaddr[3] << 24; 261185f7d9aSMichal Simek 262185f7d9aSMichal Simek /* Set MAC bits [47:32] in TOP */ 263185f7d9aSMichal Simek macaddrhigh = dev->enetaddr[4]; 264185f7d9aSMichal Simek macaddrhigh |= dev->enetaddr[5] << 8; 265185f7d9aSMichal Simek 266185f7d9aSMichal Simek for (i = 0; i < 4; i++) { 267185f7d9aSMichal Simek writel(0, ®s->laddr[i][LADDR_LOW]); 268185f7d9aSMichal Simek writel(0, ®s->laddr[i][LADDR_HIGH]); 269185f7d9aSMichal Simek /* Do not use MATCHx register */ 270185f7d9aSMichal Simek writel(0, ®s->match[i]); 271185f7d9aSMichal Simek } 272185f7d9aSMichal Simek 273185f7d9aSMichal Simek writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 274185f7d9aSMichal Simek writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 275185f7d9aSMichal Simek 276185f7d9aSMichal Simek return 0; 277185f7d9aSMichal Simek } 278185f7d9aSMichal Simek 279185f7d9aSMichal Simek static int zynq_gem_init(struct eth_device *dev, bd_t * bis) 280185f7d9aSMichal Simek { 28197598fcfSSoren Brinkmann u32 i; 28297598fcfSSoren Brinkmann unsigned long clk_rate = 0; 283185f7d9aSMichal Simek struct phy_device *phydev; 284185f7d9aSMichal Simek const u32 stat_size = (sizeof(struct zynq_gem_regs) - 285185f7d9aSMichal Simek offsetof(struct zynq_gem_regs, stat)) / 4; 286185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 287185f7d9aSMichal Simek struct zynq_gem_priv *priv = dev->priv; 288185f7d9aSMichal Simek const u32 supported = SUPPORTED_10baseT_Half | 289185f7d9aSMichal Simek SUPPORTED_10baseT_Full | 290185f7d9aSMichal Simek SUPPORTED_100baseT_Half | 291185f7d9aSMichal Simek SUPPORTED_100baseT_Full | 292185f7d9aSMichal Simek SUPPORTED_1000baseT_Half | 293185f7d9aSMichal Simek SUPPORTED_1000baseT_Full; 294185f7d9aSMichal Simek 29505868759SMichal Simek if (!priv->init) { 296185f7d9aSMichal Simek /* Disable all interrupts */ 297185f7d9aSMichal Simek writel(0xFFFFFFFF, ®s->idr); 298185f7d9aSMichal Simek 299185f7d9aSMichal Simek /* Disable the receiver & transmitter */ 300185f7d9aSMichal Simek writel(0, ®s->nwctrl); 301185f7d9aSMichal Simek writel(0, ®s->txsr); 302185f7d9aSMichal Simek writel(0, ®s->rxsr); 303185f7d9aSMichal Simek writel(0, ®s->phymntnc); 304185f7d9aSMichal Simek 30505868759SMichal Simek /* Clear the Hash registers for the mac address 30605868759SMichal Simek * pointed by AddressPtr 30705868759SMichal Simek */ 308185f7d9aSMichal Simek writel(0x0, ®s->hashl); 309185f7d9aSMichal Simek /* Write bits [63:32] in TOP */ 310185f7d9aSMichal Simek writel(0x0, ®s->hashh); 311185f7d9aSMichal Simek 312185f7d9aSMichal Simek /* Clear all counters */ 313185f7d9aSMichal Simek for (i = 0; i <= stat_size; i++) 314185f7d9aSMichal Simek readl(®s->stat[i]); 315185f7d9aSMichal Simek 316185f7d9aSMichal Simek /* Setup RxBD space */ 317a5144237SSrikanth Thokala memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 318185f7d9aSMichal Simek 319185f7d9aSMichal Simek for (i = 0; i < RX_BUF; i++) { 320185f7d9aSMichal Simek priv->rx_bd[i].status = 0xF0000000; 32105868759SMichal Simek priv->rx_bd[i].addr = 322a5144237SSrikanth Thokala ((u32)(priv->rxbuffers) + 323185f7d9aSMichal Simek (i * PKTSIZE_ALIGN)); 324185f7d9aSMichal Simek } 325185f7d9aSMichal Simek /* WRAP bit to last BD */ 326185f7d9aSMichal Simek priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 327185f7d9aSMichal Simek /* Write RxBDs to IP */ 328a5144237SSrikanth Thokala writel((u32)priv->rx_bd, ®s->rxqbase); 329185f7d9aSMichal Simek 330185f7d9aSMichal Simek /* Setup for DMA Configuration register */ 331185f7d9aSMichal Simek writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 332185f7d9aSMichal Simek 333185f7d9aSMichal Simek /* Setup for Network Control register, MDIO, Rx and Tx enable */ 33480243528SMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 335185f7d9aSMichal Simek 33605868759SMichal Simek priv->init++; 33705868759SMichal Simek } 33805868759SMichal Simek 339f97d7e8bSMichal Simek phy_detection(dev); 340f97d7e8bSMichal Simek 341185f7d9aSMichal Simek /* interface - look at tsec */ 342c1a9fa4bSMichal Simek phydev = phy_connect(priv->bus, priv->phyaddr, dev, 343c1a9fa4bSMichal Simek PHY_INTERFACE_MODE_MII); 344185f7d9aSMichal Simek 34580243528SMichal Simek phydev->supported = supported | ADVERTISED_Pause | 34680243528SMichal Simek ADVERTISED_Asym_Pause; 347185f7d9aSMichal Simek phydev->advertising = phydev->supported; 348185f7d9aSMichal Simek priv->phydev = phydev; 349185f7d9aSMichal Simek phy_config(phydev); 350185f7d9aSMichal Simek phy_startup(phydev); 351185f7d9aSMichal Simek 3524ed4aa20SMichal Simek if (!phydev->link) { 3534ed4aa20SMichal Simek printf("%s: No link.\n", phydev->dev->name); 3544ed4aa20SMichal Simek return -1; 3554ed4aa20SMichal Simek } 3564ed4aa20SMichal Simek 35780243528SMichal Simek switch (phydev->speed) { 35880243528SMichal Simek case SPEED_1000: 35980243528SMichal Simek writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 36080243528SMichal Simek ®s->nwcfg); 36197598fcfSSoren Brinkmann clk_rate = ZYNQ_GEM_FREQUENCY_1000; 36280243528SMichal Simek break; 36380243528SMichal Simek case SPEED_100: 36480243528SMichal Simek clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, 36580243528SMichal Simek ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); 36697598fcfSSoren Brinkmann clk_rate = ZYNQ_GEM_FREQUENCY_100; 36780243528SMichal Simek break; 36880243528SMichal Simek case SPEED_10: 36997598fcfSSoren Brinkmann clk_rate = ZYNQ_GEM_FREQUENCY_10; 37080243528SMichal Simek break; 37180243528SMichal Simek } 37201fbf310SDavid Andrey 37301fbf310SDavid Andrey /* Change the rclk and clk only not using EMIO interface */ 37401fbf310SDavid Andrey if (!priv->emio) 37501fbf310SDavid Andrey zynq_slcr_gem_clk_setup(dev->iobase != 37697598fcfSSoren Brinkmann ZYNQ_GEM_BASEADDR0, clk_rate); 37780243528SMichal Simek 37880243528SMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 37980243528SMichal Simek ZYNQ_GEM_NWCTRL_TXEN_MASK); 38080243528SMichal Simek 381185f7d9aSMichal Simek return 0; 382185f7d9aSMichal Simek } 383185f7d9aSMichal Simek 384185f7d9aSMichal Simek static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) 385185f7d9aSMichal Simek { 386a5144237SSrikanth Thokala u32 addr, size; 387185f7d9aSMichal Simek struct zynq_gem_priv *priv = dev->priv; 388185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 389185f7d9aSMichal Simek 390185f7d9aSMichal Simek /* setup BD */ 391a5144237SSrikanth Thokala writel((u32)priv->tx_bd, ®s->txqbase); 392185f7d9aSMichal Simek 393185f7d9aSMichal Simek /* Setup Tx BD */ 394a5144237SSrikanth Thokala memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 395185f7d9aSMichal Simek 396a5144237SSrikanth Thokala priv->tx_bd->addr = (u32)ptr; 397a5144237SSrikanth Thokala priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 398a5144237SSrikanth Thokala ZYNQ_GEM_TXBUF_LAST_MASK; 399a5144237SSrikanth Thokala 400a5144237SSrikanth Thokala addr = (u32) ptr; 401a5144237SSrikanth Thokala addr &= ~(ARCH_DMA_MINALIGN - 1); 402a5144237SSrikanth Thokala size = roundup(len, ARCH_DMA_MINALIGN); 403a5144237SSrikanth Thokala flush_dcache_range(addr, addr + size); 404a5144237SSrikanth Thokala barrier(); 405185f7d9aSMichal Simek 406185f7d9aSMichal Simek /* Start transmit */ 407185f7d9aSMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 408185f7d9aSMichal Simek 409a5144237SSrikanth Thokala /* Read TX BD status */ 410a5144237SSrikanth Thokala if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN) 411a5144237SSrikanth Thokala printf("TX underrun\n"); 412a5144237SSrikanth Thokala if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 413a5144237SSrikanth Thokala printf("TX buffers exhausted in mid frame\n"); 414185f7d9aSMichal Simek 415185f7d9aSMichal Simek return 0; 416185f7d9aSMichal Simek } 417185f7d9aSMichal Simek 418185f7d9aSMichal Simek /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 419185f7d9aSMichal Simek static int zynq_gem_recv(struct eth_device *dev) 420185f7d9aSMichal Simek { 421185f7d9aSMichal Simek int frame_len; 422185f7d9aSMichal Simek struct zynq_gem_priv *priv = dev->priv; 423185f7d9aSMichal Simek struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 424185f7d9aSMichal Simek struct emac_bd *first_bd; 425185f7d9aSMichal Simek 426185f7d9aSMichal Simek if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 427185f7d9aSMichal Simek return 0; 428185f7d9aSMichal Simek 429185f7d9aSMichal Simek if (!(current_bd->status & 430185f7d9aSMichal Simek (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 431185f7d9aSMichal Simek printf("GEM: SOF or EOF not set for last buffer received!\n"); 432185f7d9aSMichal Simek return 0; 433185f7d9aSMichal Simek } 434185f7d9aSMichal Simek 435185f7d9aSMichal Simek frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 436185f7d9aSMichal Simek if (frame_len) { 437a5144237SSrikanth Thokala u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 438a5144237SSrikanth Thokala addr &= ~(ARCH_DMA_MINALIGN - 1); 439a5144237SSrikanth Thokala u32 size = roundup(frame_len, ARCH_DMA_MINALIGN); 440a5144237SSrikanth Thokala invalidate_dcache_range(addr, addr + size); 441a5144237SSrikanth Thokala 442a5144237SSrikanth Thokala NetReceive((u8 *)addr, frame_len); 443185f7d9aSMichal Simek 444185f7d9aSMichal Simek if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 445185f7d9aSMichal Simek priv->rx_first_buf = priv->rxbd_current; 446185f7d9aSMichal Simek else { 447185f7d9aSMichal Simek current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 448185f7d9aSMichal Simek current_bd->status = 0xF0000000; /* FIXME */ 449185f7d9aSMichal Simek } 450185f7d9aSMichal Simek 451185f7d9aSMichal Simek if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 452185f7d9aSMichal Simek first_bd = &priv->rx_bd[priv->rx_first_buf]; 453185f7d9aSMichal Simek first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 454185f7d9aSMichal Simek first_bd->status = 0xF0000000; 455185f7d9aSMichal Simek } 456185f7d9aSMichal Simek 457185f7d9aSMichal Simek if ((++priv->rxbd_current) >= RX_BUF) 458185f7d9aSMichal Simek priv->rxbd_current = 0; 459185f7d9aSMichal Simek } 460185f7d9aSMichal Simek 4613b90d0afSMichal Simek return frame_len; 462185f7d9aSMichal Simek } 463185f7d9aSMichal Simek 464185f7d9aSMichal Simek static void zynq_gem_halt(struct eth_device *dev) 465185f7d9aSMichal Simek { 466185f7d9aSMichal Simek struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 467185f7d9aSMichal Simek 46880243528SMichal Simek clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 46980243528SMichal Simek ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 470185f7d9aSMichal Simek } 471185f7d9aSMichal Simek 472185f7d9aSMichal Simek static int zynq_gem_miiphyread(const char *devname, uchar addr, 473185f7d9aSMichal Simek uchar reg, ushort *val) 474185f7d9aSMichal Simek { 475185f7d9aSMichal Simek struct eth_device *dev = eth_get_dev(); 476185f7d9aSMichal Simek int ret; 477185f7d9aSMichal Simek 478185f7d9aSMichal Simek ret = phyread(dev, addr, reg, val); 479185f7d9aSMichal Simek debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); 480185f7d9aSMichal Simek return ret; 481185f7d9aSMichal Simek } 482185f7d9aSMichal Simek 483185f7d9aSMichal Simek static int zynq_gem_miiphy_write(const char *devname, uchar addr, 484185f7d9aSMichal Simek uchar reg, ushort val) 485185f7d9aSMichal Simek { 486185f7d9aSMichal Simek struct eth_device *dev = eth_get_dev(); 487185f7d9aSMichal Simek 488185f7d9aSMichal Simek debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); 489185f7d9aSMichal Simek return phywrite(dev, addr, reg, val); 490185f7d9aSMichal Simek } 491185f7d9aSMichal Simek 492*58405378SMichal Simek int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, 493*58405378SMichal Simek int phy_addr, u32 emio) 494185f7d9aSMichal Simek { 495185f7d9aSMichal Simek struct eth_device *dev; 496185f7d9aSMichal Simek struct zynq_gem_priv *priv; 497a5144237SSrikanth Thokala void *bd_space; 498185f7d9aSMichal Simek 499185f7d9aSMichal Simek dev = calloc(1, sizeof(*dev)); 500185f7d9aSMichal Simek if (dev == NULL) 501185f7d9aSMichal Simek return -1; 502185f7d9aSMichal Simek 503185f7d9aSMichal Simek dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); 504185f7d9aSMichal Simek if (dev->priv == NULL) { 505185f7d9aSMichal Simek free(dev); 506185f7d9aSMichal Simek return -1; 507185f7d9aSMichal Simek } 508185f7d9aSMichal Simek priv = dev->priv; 509185f7d9aSMichal Simek 510a5144237SSrikanth Thokala /* Align rxbuffers to ARCH_DMA_MINALIGN */ 511a5144237SSrikanth Thokala priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 512a5144237SSrikanth Thokala memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 513a5144237SSrikanth Thokala 514a5144237SSrikanth Thokala /* Align bd_space to 1MB */ 515a5144237SSrikanth Thokala bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 516a5144237SSrikanth Thokala mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF); 517a5144237SSrikanth Thokala 518a5144237SSrikanth Thokala /* Initialize the bd spaces for tx and rx bd's */ 519a5144237SSrikanth Thokala priv->tx_bd = (struct emac_bd *)bd_space; 520a5144237SSrikanth Thokala priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE); 521a5144237SSrikanth Thokala 522117cd4ccSDavid Andrey priv->phyaddr = phy_addr; 52301fbf310SDavid Andrey priv->emio = emio; 524185f7d9aSMichal Simek 525*58405378SMichal Simek sprintf(dev->name, "Gem.%lx", base_addr); 526185f7d9aSMichal Simek 527185f7d9aSMichal Simek dev->iobase = base_addr; 528185f7d9aSMichal Simek 529185f7d9aSMichal Simek dev->init = zynq_gem_init; 530185f7d9aSMichal Simek dev->halt = zynq_gem_halt; 531185f7d9aSMichal Simek dev->send = zynq_gem_send; 532185f7d9aSMichal Simek dev->recv = zynq_gem_recv; 533185f7d9aSMichal Simek dev->write_hwaddr = zynq_gem_setup_mac; 534185f7d9aSMichal Simek 535185f7d9aSMichal Simek eth_register(dev); 536185f7d9aSMichal Simek 537185f7d9aSMichal Simek miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); 538185f7d9aSMichal Simek priv->bus = miiphy_get_dev_by_name(dev->name); 539185f7d9aSMichal Simek 540185f7d9aSMichal Simek return 1; 541185f7d9aSMichal Simek } 542f88a6869SMichal Simek 543f88a6869SMichal Simek #ifdef CONFIG_OF_CONTROL 544f88a6869SMichal Simek int zynq_gem_of_init(const void *blob) 545f88a6869SMichal Simek { 546f88a6869SMichal Simek int offset = 0; 547f88a6869SMichal Simek u32 ret = 0; 548f88a6869SMichal Simek u32 reg, phy_reg; 549f88a6869SMichal Simek 550f88a6869SMichal Simek debug("ZYNQ GEM: Initialization\n"); 551f88a6869SMichal Simek 552f88a6869SMichal Simek do { 553f88a6869SMichal Simek offset = fdt_node_offset_by_compatible(blob, offset, 554f88a6869SMichal Simek "xlnx,ps7-ethernet-1.00.a"); 555f88a6869SMichal Simek if (offset != -1) { 556f88a6869SMichal Simek reg = fdtdec_get_addr(blob, offset, "reg"); 557f88a6869SMichal Simek if (reg != FDT_ADDR_T_NONE) { 558f88a6869SMichal Simek offset = fdtdec_lookup_phandle(blob, offset, 559f88a6869SMichal Simek "phy-handle"); 560f88a6869SMichal Simek if (offset != -1) 561f88a6869SMichal Simek phy_reg = fdtdec_get_addr(blob, offset, 562f88a6869SMichal Simek "reg"); 563f88a6869SMichal Simek else 564f88a6869SMichal Simek phy_reg = 0; 565f88a6869SMichal Simek 566f88a6869SMichal Simek debug("ZYNQ GEM: addr %x, phyaddr %x\n", 567f88a6869SMichal Simek reg, phy_reg); 568f88a6869SMichal Simek 569f88a6869SMichal Simek ret |= zynq_gem_initialize(NULL, reg, 570f88a6869SMichal Simek phy_reg, 0); 571f88a6869SMichal Simek 572f88a6869SMichal Simek } else { 573f88a6869SMichal Simek debug("ZYNQ GEM: Can't get base address\n"); 574f88a6869SMichal Simek return -1; 575f88a6869SMichal Simek } 576f88a6869SMichal Simek } 577f88a6869SMichal Simek } while (offset != -1); 578f88a6869SMichal Simek 579f88a6869SMichal Simek return ret; 580f88a6869SMichal Simek } 581f88a6869SMichal Simek #endif 582