1 /* 2 * (C) Copyright 2007-2009 Michal Simek 3 * (C) Copyright 2003 Xilinx Inc. 4 * 5 * Michal SIMEK <monstr@monstr.eu> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <net.h> 12 #include <config.h> 13 #include <dm.h> 14 #include <console.h> 15 #include <malloc.h> 16 #include <asm/io.h> 17 #include <phy.h> 18 #include <miiphy.h> 19 #include <fdtdec.h> 20 #include <linux/errno.h> 21 #include <linux/kernel.h> 22 #include <asm/io.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define ENET_ADDR_LENGTH 6 27 #define ETH_FCS_LEN 4 /* Octets in the FCS */ 28 29 /* Xmit complete */ 30 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL 31 /* Xmit interrupt enable bit */ 32 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL 33 /* Program the MAC address */ 34 #define XEL_TSR_PROGRAM_MASK 0x00000002UL 35 /* define for programming the MAC address into the EMAC Lite */ 36 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 37 38 /* Transmit packet length upper byte */ 39 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL 40 /* Transmit packet length lower byte */ 41 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL 42 43 /* Recv complete */ 44 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL 45 /* Recv interrupt enable bit */ 46 #define XEL_RSR_RECV_IE_MASK 0x00000008UL 47 48 /* MDIO Address Register Bit Masks */ 49 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 50 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 51 #define XEL_MDIOADDR_PHYADR_SHIFT 5 52 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 53 54 /* MDIO Write Data Register Bit Masks */ 55 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 56 57 /* MDIO Read Data Register Bit Masks */ 58 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 59 60 /* MDIO Control Register Bit Masks */ 61 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 62 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 63 64 struct emaclite_regs { 65 u32 tx_ping; /* 0x0 - TX Ping buffer */ 66 u32 reserved1[504]; 67 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */ 68 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */ 69 u32 mdiord;/* 0x7ec - MDIO Read Data Register */ 70 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */ 71 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */ 72 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */ 73 u32 tx_ping_tsr; /* 0x7fc - Tx status */ 74 u32 tx_pong; /* 0x800 - TX Pong buffer */ 75 u32 reserved2[508]; 76 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */ 77 u32 reserved3; /* 0xff8 */ 78 u32 tx_pong_tsr; /* 0xffc - Tx status */ 79 u32 rx_ping; /* 0x1000 - Receive Buffer */ 80 u32 reserved4[510]; 81 u32 rx_ping_rsr; /* 0x17fc - Rx status */ 82 u32 rx_pong; /* 0x1800 - Receive Buffer */ 83 u32 reserved5[510]; 84 u32 rx_pong_rsr; /* 0x1ffc - Rx status */ 85 }; 86 87 struct xemaclite { 88 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */ 89 u32 txpp; /* TX ping pong buffer */ 90 u32 rxpp; /* RX ping pong buffer */ 91 int phyaddr; 92 struct emaclite_regs *regs; 93 struct phy_device *phydev; 94 struct mii_dev *bus; 95 }; 96 97 static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ 98 99 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) 100 { 101 u32 i; 102 u32 alignbuffer; 103 u32 *to32ptr; 104 u32 *from32ptr; 105 u8 *to8ptr; 106 u8 *from8ptr; 107 108 from32ptr = (u32 *) srcptr; 109 110 /* Word aligned buffer, no correction needed. */ 111 to32ptr = (u32 *) destptr; 112 while (bytecount > 3) { 113 *to32ptr++ = *from32ptr++; 114 bytecount -= 4; 115 } 116 to8ptr = (u8 *) to32ptr; 117 118 alignbuffer = *from32ptr++; 119 from8ptr = (u8 *) &alignbuffer; 120 121 for (i = 0; i < bytecount; i++) 122 *to8ptr++ = *from8ptr++; 123 } 124 125 static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount) 126 { 127 u32 i; 128 u32 alignbuffer; 129 u32 *to32ptr = (u32 *) destptr; 130 u32 *from32ptr; 131 u8 *to8ptr; 132 u8 *from8ptr; 133 134 from32ptr = (u32 *) srcptr; 135 while (bytecount > 3) { 136 137 *to32ptr++ = *from32ptr++; 138 bytecount -= 4; 139 } 140 141 alignbuffer = 0; 142 to8ptr = (u8 *) &alignbuffer; 143 from8ptr = (u8 *) from32ptr; 144 145 for (i = 0; i < bytecount; i++) 146 *to8ptr++ = *from8ptr++; 147 148 *to32ptr++ = alignbuffer; 149 } 150 151 static int wait_for_bit(const char *func, u32 *reg, const u32 mask, 152 bool set, unsigned int timeout) 153 { 154 u32 val; 155 unsigned long start = get_timer(0); 156 157 while (1) { 158 val = __raw_readl(reg); 159 160 if (!set) 161 val = ~val; 162 163 if ((val & mask) == mask) 164 return 0; 165 166 if (get_timer(start) > timeout) 167 break; 168 169 if (ctrlc()) { 170 puts("Abort\n"); 171 return -EINTR; 172 } 173 174 udelay(1); 175 } 176 177 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", 178 func, reg, mask, set); 179 180 return -ETIMEDOUT; 181 } 182 183 static int mdio_wait(struct emaclite_regs *regs) 184 { 185 return wait_for_bit(__func__, ®s->mdioctrl, 186 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000); 187 } 188 189 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, 190 u16 *data) 191 { 192 struct emaclite_regs *regs = emaclite->regs; 193 194 if (mdio_wait(regs)) 195 return 1; 196 197 u32 ctrl_reg = __raw_readl(®s->mdioctrl); 198 __raw_writel(XEL_MDIOADDR_OP_MASK 199 | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) 200 | registernum), ®s->mdioaddr); 201 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl); 202 203 if (mdio_wait(regs)) 204 return 1; 205 206 /* Read data */ 207 *data = __raw_readl(®s->mdiord); 208 return 0; 209 } 210 211 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, 212 u16 data) 213 { 214 struct emaclite_regs *regs = emaclite->regs; 215 216 if (mdio_wait(regs)) 217 return 1; 218 219 /* 220 * Write the PHY address, register number and clear the OP bit in the 221 * MDIO Address register and then write the value into the MDIO Write 222 * Data register. Finally, set the Status bit in the MDIO Control 223 * register to start a MDIO write transaction. 224 */ 225 u32 ctrl_reg = __raw_readl(®s->mdioctrl); 226 __raw_writel(~XEL_MDIOADDR_OP_MASK 227 & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) 228 | registernum), ®s->mdioaddr); 229 __raw_writel(data, ®s->mdiowr); 230 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl); 231 232 if (mdio_wait(regs)) 233 return 1; 234 235 return 0; 236 } 237 238 static void emaclite_stop(struct udevice *dev) 239 { 240 debug("eth_stop\n"); 241 } 242 243 /* Use MII register 1 (MII status register) to detect PHY */ 244 #define PHY_DETECT_REG 1 245 246 /* Mask used to verify certain PHY features (or register contents) 247 * in the register above: 248 * 0x1000: 10Mbps full duplex support 249 * 0x0800: 10Mbps half duplex support 250 * 0x0008: Auto-negotiation support 251 */ 252 #define PHY_DETECT_MASK 0x1808 253 254 static int setup_phy(struct udevice *dev) 255 { 256 int i, ret; 257 u16 phyreg; 258 struct xemaclite *emaclite = dev_get_priv(dev); 259 struct phy_device *phydev; 260 261 u32 supported = SUPPORTED_10baseT_Half | 262 SUPPORTED_10baseT_Full | 263 SUPPORTED_100baseT_Half | 264 SUPPORTED_100baseT_Full; 265 266 if (emaclite->phyaddr != -1) { 267 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); 268 if ((phyreg != 0xFFFF) && 269 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 270 /* Found a valid PHY address */ 271 debug("Default phy address %d is valid\n", 272 emaclite->phyaddr); 273 } else { 274 debug("PHY address is not setup correctly %d\n", 275 emaclite->phyaddr); 276 emaclite->phyaddr = -1; 277 } 278 } 279 280 if (emaclite->phyaddr == -1) { 281 /* detect the PHY address */ 282 for (i = 31; i >= 0; i--) { 283 phyread(emaclite, i, PHY_DETECT_REG, &phyreg); 284 if ((phyreg != 0xFFFF) && 285 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 286 /* Found a valid PHY address */ 287 emaclite->phyaddr = i; 288 debug("emaclite: Found valid phy address, %d\n", 289 i); 290 break; 291 } 292 } 293 } 294 295 /* interface - look at tsec */ 296 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev, 297 PHY_INTERFACE_MODE_MII); 298 /* 299 * Phy can support 1000baseT but device NOT that's why phydev->supported 300 * must be setup for 1000baseT. phydev->advertising setups what speeds 301 * will be used for autonegotiation where 1000baseT must be disabled. 302 */ 303 phydev->supported = supported | SUPPORTED_1000baseT_Half | 304 SUPPORTED_1000baseT_Full; 305 phydev->advertising = supported; 306 emaclite->phydev = phydev; 307 phy_config(phydev); 308 ret = phy_startup(phydev); 309 if (ret) 310 return ret; 311 312 if (!phydev->link) { 313 printf("%s: No link.\n", phydev->dev->name); 314 return 0; 315 } 316 317 /* Do not setup anything */ 318 return 1; 319 } 320 321 static int emaclite_start(struct udevice *dev) 322 { 323 struct xemaclite *emaclite = dev_get_priv(dev); 324 struct eth_pdata *pdata = dev_get_platdata(dev); 325 struct emaclite_regs *regs = emaclite->regs; 326 327 debug("EmacLite Initialization Started\n"); 328 329 /* 330 * TX - TX_PING & TX_PONG initialization 331 */ 332 /* Restart PING TX */ 333 __raw_writel(0, ®s->tx_ping_tsr); 334 /* Copy MAC address */ 335 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping, 336 ENET_ADDR_LENGTH); 337 /* Set the length */ 338 __raw_writel(ENET_ADDR_LENGTH, ®s->tx_ping_tplr); 339 /* Update the MAC address in the EMAC Lite */ 340 __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_ping_tsr); 341 /* Wait for EMAC Lite to finish with the MAC address update */ 342 while ((__raw_readl(®s->tx_ping_tsr) & 343 XEL_TSR_PROG_MAC_ADDR) != 0) 344 ; 345 346 if (emaclite->txpp) { 347 /* The same operation with PONG TX */ 348 __raw_writel(0, ®s->tx_pong_tsr); 349 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong, 350 ENET_ADDR_LENGTH); 351 __raw_writel(ENET_ADDR_LENGTH, ®s->tx_pong_tplr); 352 __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_pong_tsr); 353 while ((__raw_readl(®s->tx_pong_tsr) & 354 XEL_TSR_PROG_MAC_ADDR) != 0) 355 ; 356 } 357 358 /* 359 * RX - RX_PING & RX_PONG initialization 360 */ 361 /* Write out the value to flush the RX buffer */ 362 __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_ping_rsr); 363 364 if (emaclite->rxpp) 365 __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_pong_rsr); 366 367 __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, ®s->mdioctrl); 368 if (__raw_readl(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) 369 if (!setup_phy(dev)) 370 return -1; 371 372 debug("EmacLite Initialization complete\n"); 373 return 0; 374 } 375 376 static int xemaclite_txbufferavailable(struct xemaclite *emaclite) 377 { 378 u32 tmp; 379 struct emaclite_regs *regs = emaclite->regs; 380 381 /* 382 * Read the other buffer register 383 * and determine if the other buffer is available 384 */ 385 tmp = ~__raw_readl(®s->tx_ping_tsr); 386 if (emaclite->txpp) 387 tmp |= ~__raw_readl(®s->tx_pong_tsr); 388 389 return !(tmp & XEL_TSR_XMIT_BUSY_MASK); 390 } 391 392 static int emaclite_send(struct udevice *dev, void *ptr, int len) 393 { 394 u32 reg; 395 struct xemaclite *emaclite = dev_get_priv(dev); 396 struct emaclite_regs *regs = emaclite->regs; 397 398 u32 maxtry = 1000; 399 400 if (len > PKTSIZE) 401 len = PKTSIZE; 402 403 while (xemaclite_txbufferavailable(emaclite) && maxtry) { 404 udelay(10); 405 maxtry--; 406 } 407 408 if (!maxtry) { 409 printf("Error: Timeout waiting for ethernet TX buffer\n"); 410 /* Restart PING TX */ 411 __raw_writel(0, ®s->tx_ping_tsr); 412 if (emaclite->txpp) { 413 __raw_writel(0, ®s->tx_pong_tsr); 414 } 415 return -1; 416 } 417 418 /* Determine if the expected buffer address is empty */ 419 reg = __raw_readl(®s->tx_ping_tsr); 420 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { 421 debug("Send packet from tx_ping buffer\n"); 422 /* Write the frame to the buffer */ 423 xemaclite_alignedwrite(ptr, ®s->tx_ping, len); 424 __raw_writel(len 425 & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO), 426 ®s->tx_ping_tplr); 427 reg = __raw_readl(®s->tx_ping_tsr); 428 reg |= XEL_TSR_XMIT_BUSY_MASK; 429 __raw_writel(reg, ®s->tx_ping_tsr); 430 return 0; 431 } 432 433 if (emaclite->txpp) { 434 /* Determine if the expected buffer address is empty */ 435 reg = __raw_readl(®s->tx_pong_tsr); 436 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { 437 debug("Send packet from tx_pong buffer\n"); 438 /* Write the frame to the buffer */ 439 xemaclite_alignedwrite(ptr, ®s->tx_pong, len); 440 __raw_writel(len & 441 (XEL_TPLR_LENGTH_MASK_HI | 442 XEL_TPLR_LENGTH_MASK_LO), 443 ®s->tx_pong_tplr); 444 reg = __raw_readl(®s->tx_pong_tsr); 445 reg |= XEL_TSR_XMIT_BUSY_MASK; 446 __raw_writel(reg, ®s->tx_pong_tsr); 447 return 0; 448 } 449 } 450 451 puts("Error while sending frame\n"); 452 return -1; 453 } 454 455 static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp) 456 { 457 u32 length, first_read, reg, attempt = 0; 458 void *addr, *ack; 459 struct xemaclite *emaclite = dev->priv; 460 struct emaclite_regs *regs = emaclite->regs; 461 struct ethernet_hdr *eth; 462 struct ip_udp_hdr *ip; 463 464 try_again: 465 if (!emaclite->use_rx_pong_buffer_next) { 466 reg = __raw_readl(®s->rx_ping_rsr); 467 debug("Testing data at rx_ping\n"); 468 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 469 debug("Data found in rx_ping buffer\n"); 470 addr = ®s->rx_ping; 471 ack = ®s->rx_ping_rsr; 472 } else { 473 debug("Data not found in rx_ping buffer\n"); 474 /* Pong buffer is not available - return immediately */ 475 if (!emaclite->rxpp) 476 return -1; 477 478 /* Try pong buffer if this is first attempt */ 479 if (attempt++) 480 return -1; 481 emaclite->use_rx_pong_buffer_next = 482 !emaclite->use_rx_pong_buffer_next; 483 goto try_again; 484 } 485 } else { 486 reg = __raw_readl(®s->rx_pong_rsr); 487 debug("Testing data at rx_pong\n"); 488 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 489 debug("Data found in rx_pong buffer\n"); 490 addr = ®s->rx_pong; 491 ack = ®s->rx_pong_rsr; 492 } else { 493 debug("Data not found in rx_pong buffer\n"); 494 /* Try ping buffer if this is first attempt */ 495 if (attempt++) 496 return -1; 497 emaclite->use_rx_pong_buffer_next = 498 !emaclite->use_rx_pong_buffer_next; 499 goto try_again; 500 } 501 } 502 503 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */ 504 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4); 505 xemaclite_alignedread(addr, etherrxbuff, first_read); 506 507 /* Detect real packet size */ 508 eth = (struct ethernet_hdr *)etherrxbuff; 509 switch (ntohs(eth->et_protlen)) { 510 case PROT_ARP: 511 length = first_read; 512 debug("ARP Packet %x\n", length); 513 break; 514 case PROT_IP: 515 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE); 516 length = ntohs(ip->ip_len); 517 length += ETHER_HDR_SIZE + ETH_FCS_LEN; 518 debug("IP Packet %x\n", length); 519 break; 520 default: 521 debug("Other Packet\n"); 522 length = PKTSIZE; 523 break; 524 } 525 526 /* Read the rest of the packet which is longer then first read */ 527 if (length != first_read) 528 xemaclite_alignedread(addr + first_read, 529 etherrxbuff + first_read, 530 length - first_read); 531 532 /* Acknowledge the frame */ 533 reg = __raw_readl(ack); 534 reg &= ~XEL_RSR_RECV_DONE_MASK; 535 __raw_writel(reg, ack); 536 537 debug("Packet receive from 0x%p, length %dB\n", addr, length); 538 *packetp = etherrxbuff; 539 return length; 540 } 541 542 static int emaclite_miiphy_read(struct mii_dev *bus, int addr, 543 int devad, int reg) 544 { 545 u32 ret; 546 u16 val = 0; 547 548 ret = phyread(bus->priv, addr, reg, &val); 549 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret); 550 return val; 551 } 552 553 static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad, 554 int reg, u16 value) 555 { 556 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); 557 return phywrite(bus->priv, addr, reg, value); 558 } 559 560 static int emaclite_probe(struct udevice *dev) 561 { 562 struct xemaclite *emaclite = dev_get_priv(dev); 563 int ret; 564 565 emaclite->bus = mdio_alloc(); 566 emaclite->bus->read = emaclite_miiphy_read; 567 emaclite->bus->write = emaclite_miiphy_write; 568 emaclite->bus->priv = emaclite; 569 570 ret = mdio_register_seq(emaclite->bus, dev->seq); 571 if (ret) 572 return ret; 573 574 return 0; 575 } 576 577 static int emaclite_remove(struct udevice *dev) 578 { 579 struct xemaclite *emaclite = dev_get_priv(dev); 580 581 free(emaclite->phydev); 582 mdio_unregister(emaclite->bus); 583 mdio_free(emaclite->bus); 584 585 return 0; 586 } 587 588 static const struct eth_ops emaclite_ops = { 589 .start = emaclite_start, 590 .send = emaclite_send, 591 .recv = emaclite_recv, 592 .stop = emaclite_stop, 593 }; 594 595 static int emaclite_ofdata_to_platdata(struct udevice *dev) 596 { 597 struct eth_pdata *pdata = dev_get_platdata(dev); 598 struct xemaclite *emaclite = dev_get_priv(dev); 599 int offset = 0; 600 601 pdata->iobase = (phys_addr_t)dev_get_addr(dev); 602 emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase, 603 0x10000); 604 605 emaclite->phyaddr = -1; 606 607 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, 608 "phy-handle"); 609 if (offset > 0) 610 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, 611 "reg", -1); 612 613 emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, 614 "xlnx,tx-ping-pong", 0); 615 emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, 616 "xlnx,rx-ping-pong", 0); 617 618 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs, 619 emaclite->phyaddr, emaclite->txpp, emaclite->rxpp); 620 621 return 0; 622 } 623 624 static const struct udevice_id emaclite_ids[] = { 625 { .compatible = "xlnx,xps-ethernetlite-1.00.a" }, 626 { } 627 }; 628 629 U_BOOT_DRIVER(emaclite) = { 630 .name = "emaclite", 631 .id = UCLASS_ETH, 632 .of_match = emaclite_ids, 633 .ofdata_to_platdata = emaclite_ofdata_to_platdata, 634 .probe = emaclite_probe, 635 .remove = emaclite_remove, 636 .ops = &emaclite_ops, 637 .priv_auto_alloc_size = sizeof(struct xemaclite), 638 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 639 }; 640