1 /* 2 * (C) Copyright 2007-2009 Michal Simek 3 * (C) Copyright 2003 Xilinx Inc. 4 * 5 * Michal SIMEK <monstr@monstr.eu> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <net.h> 12 #include <config.h> 13 #include <dm.h> 14 #include <console.h> 15 #include <malloc.h> 16 #include <asm/io.h> 17 #include <phy.h> 18 #include <miiphy.h> 19 #include <fdtdec.h> 20 #include <asm-generic/errno.h> 21 #include <linux/kernel.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define ENET_ADDR_LENGTH 6 26 #define ETH_FCS_LEN 4 /* Octets in the FCS */ 27 28 /* Xmit complete */ 29 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL 30 /* Xmit interrupt enable bit */ 31 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL 32 /* Program the MAC address */ 33 #define XEL_TSR_PROGRAM_MASK 0x00000002UL 34 /* define for programming the MAC address into the EMAC Lite */ 35 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 36 37 /* Transmit packet length upper byte */ 38 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL 39 /* Transmit packet length lower byte */ 40 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL 41 42 /* Recv complete */ 43 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL 44 /* Recv interrupt enable bit */ 45 #define XEL_RSR_RECV_IE_MASK 0x00000008UL 46 47 /* MDIO Address Register Bit Masks */ 48 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 49 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 50 #define XEL_MDIOADDR_PHYADR_SHIFT 5 51 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 52 53 /* MDIO Write Data Register Bit Masks */ 54 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 55 56 /* MDIO Read Data Register Bit Masks */ 57 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 58 59 /* MDIO Control Register Bit Masks */ 60 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 61 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 62 63 struct emaclite_regs { 64 u32 tx_ping; /* 0x0 - TX Ping buffer */ 65 u32 reserved1[504]; 66 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */ 67 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */ 68 u32 mdiord;/* 0x7ec - MDIO Read Data Register */ 69 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */ 70 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */ 71 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */ 72 u32 tx_ping_tsr; /* 0x7fc - Tx status */ 73 u32 tx_pong; /* 0x800 - TX Pong buffer */ 74 u32 reserved2[508]; 75 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */ 76 u32 reserved3; /* 0xff8 */ 77 u32 tx_pong_tsr; /* 0xffc - Tx status */ 78 u32 rx_ping; /* 0x1000 - Receive Buffer */ 79 u32 reserved4[510]; 80 u32 rx_ping_rsr; /* 0x17fc - Rx status */ 81 u32 rx_pong; /* 0x1800 - Receive Buffer */ 82 u32 reserved5[510]; 83 u32 rx_pong_rsr; /* 0x1ffc - Rx status */ 84 }; 85 86 struct xemaclite { 87 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */ 88 u32 txpp; /* TX ping pong buffer */ 89 u32 rxpp; /* RX ping pong buffer */ 90 int phyaddr; 91 struct emaclite_regs *regs; 92 struct phy_device *phydev; 93 struct mii_dev *bus; 94 }; 95 96 static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ 97 98 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) 99 { 100 u32 i; 101 u32 alignbuffer; 102 u32 *to32ptr; 103 u32 *from32ptr; 104 u8 *to8ptr; 105 u8 *from8ptr; 106 107 from32ptr = (u32 *) srcptr; 108 109 /* Word aligned buffer, no correction needed. */ 110 to32ptr = (u32 *) destptr; 111 while (bytecount > 3) { 112 *to32ptr++ = *from32ptr++; 113 bytecount -= 4; 114 } 115 to8ptr = (u8 *) to32ptr; 116 117 alignbuffer = *from32ptr++; 118 from8ptr = (u8 *) &alignbuffer; 119 120 for (i = 0; i < bytecount; i++) 121 *to8ptr++ = *from8ptr++; 122 } 123 124 static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount) 125 { 126 u32 i; 127 u32 alignbuffer; 128 u32 *to32ptr = (u32 *) destptr; 129 u32 *from32ptr; 130 u8 *to8ptr; 131 u8 *from8ptr; 132 133 from32ptr = (u32 *) srcptr; 134 while (bytecount > 3) { 135 136 *to32ptr++ = *from32ptr++; 137 bytecount -= 4; 138 } 139 140 alignbuffer = 0; 141 to8ptr = (u8 *) &alignbuffer; 142 from8ptr = (u8 *) from32ptr; 143 144 for (i = 0; i < bytecount; i++) 145 *to8ptr++ = *from8ptr++; 146 147 *to32ptr++ = alignbuffer; 148 } 149 150 static int wait_for_bit(const char *func, u32 *reg, const u32 mask, 151 bool set, unsigned int timeout) 152 { 153 u32 val; 154 unsigned long start = get_timer(0); 155 156 while (1) { 157 val = readl(reg); 158 159 if (!set) 160 val = ~val; 161 162 if ((val & mask) == mask) 163 return 0; 164 165 if (get_timer(start) > timeout) 166 break; 167 168 if (ctrlc()) { 169 puts("Abort\n"); 170 return -EINTR; 171 } 172 173 udelay(1); 174 } 175 176 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", 177 func, reg, mask, set); 178 179 return -ETIMEDOUT; 180 } 181 182 static int mdio_wait(struct emaclite_regs *regs) 183 { 184 return wait_for_bit(__func__, ®s->mdioctrl, 185 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000); 186 } 187 188 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, 189 u16 *data) 190 { 191 struct emaclite_regs *regs = emaclite->regs; 192 193 if (mdio_wait(regs)) 194 return 1; 195 196 u32 ctrl_reg = in_be32(®s->mdioctrl); 197 out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK | 198 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); 199 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); 200 201 if (mdio_wait(regs)) 202 return 1; 203 204 /* Read data */ 205 *data = in_be32(®s->mdiord); 206 return 0; 207 } 208 209 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, 210 u16 data) 211 { 212 struct emaclite_regs *regs = emaclite->regs; 213 214 if (mdio_wait(regs)) 215 return 1; 216 217 /* 218 * Write the PHY address, register number and clear the OP bit in the 219 * MDIO Address register and then write the value into the MDIO Write 220 * Data register. Finally, set the Status bit in the MDIO Control 221 * register to start a MDIO write transaction. 222 */ 223 u32 ctrl_reg = in_be32(®s->mdioctrl); 224 out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK & 225 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); 226 out_be32(®s->mdiowr, data); 227 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); 228 229 if (mdio_wait(regs)) 230 return 1; 231 232 return 0; 233 } 234 235 static void emaclite_stop(struct udevice *dev) 236 { 237 debug("eth_stop\n"); 238 } 239 240 /* Use MII register 1 (MII status register) to detect PHY */ 241 #define PHY_DETECT_REG 1 242 243 /* Mask used to verify certain PHY features (or register contents) 244 * in the register above: 245 * 0x1000: 10Mbps full duplex support 246 * 0x0800: 10Mbps half duplex support 247 * 0x0008: Auto-negotiation support 248 */ 249 #define PHY_DETECT_MASK 0x1808 250 251 static int setup_phy(struct udevice *dev) 252 { 253 int i, ret; 254 u16 phyreg; 255 struct xemaclite *emaclite = dev_get_priv(dev); 256 struct phy_device *phydev; 257 258 u32 supported = SUPPORTED_10baseT_Half | 259 SUPPORTED_10baseT_Full | 260 SUPPORTED_100baseT_Half | 261 SUPPORTED_100baseT_Full; 262 263 if (emaclite->phyaddr != -1) { 264 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); 265 if ((phyreg != 0xFFFF) && 266 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 267 /* Found a valid PHY address */ 268 debug("Default phy address %d is valid\n", 269 emaclite->phyaddr); 270 } else { 271 debug("PHY address is not setup correctly %d\n", 272 emaclite->phyaddr); 273 emaclite->phyaddr = -1; 274 } 275 } 276 277 if (emaclite->phyaddr == -1) { 278 /* detect the PHY address */ 279 for (i = 31; i >= 0; i--) { 280 phyread(emaclite, i, PHY_DETECT_REG, &phyreg); 281 if ((phyreg != 0xFFFF) && 282 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 283 /* Found a valid PHY address */ 284 emaclite->phyaddr = i; 285 debug("emaclite: Found valid phy address, %d\n", 286 i); 287 break; 288 } 289 } 290 } 291 292 /* interface - look at tsec */ 293 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev, 294 PHY_INTERFACE_MODE_MII); 295 /* 296 * Phy can support 1000baseT but device NOT that's why phydev->supported 297 * must be setup for 1000baseT. phydev->advertising setups what speeds 298 * will be used for autonegotiation where 1000baseT must be disabled. 299 */ 300 phydev->supported = supported | SUPPORTED_1000baseT_Half | 301 SUPPORTED_1000baseT_Full; 302 phydev->advertising = supported; 303 emaclite->phydev = phydev; 304 phy_config(phydev); 305 ret = phy_startup(phydev); 306 if (ret) 307 return ret; 308 309 if (!phydev->link) { 310 printf("%s: No link.\n", phydev->dev->name); 311 return 0; 312 } 313 314 /* Do not setup anything */ 315 return 1; 316 } 317 318 static int emaclite_start(struct udevice *dev) 319 { 320 struct xemaclite *emaclite = dev_get_priv(dev); 321 struct eth_pdata *pdata = dev_get_platdata(dev); 322 struct emaclite_regs *regs = emaclite->regs; 323 324 debug("EmacLite Initialization Started\n"); 325 326 /* 327 * TX - TX_PING & TX_PONG initialization 328 */ 329 /* Restart PING TX */ 330 out_be32(®s->tx_ping_tsr, 0); 331 /* Copy MAC address */ 332 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping, 333 ENET_ADDR_LENGTH); 334 /* Set the length */ 335 out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH); 336 /* Update the MAC address in the EMAC Lite */ 337 out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR); 338 /* Wait for EMAC Lite to finish with the MAC address update */ 339 while ((in_be32 (®s->tx_ping_tsr) & 340 XEL_TSR_PROG_MAC_ADDR) != 0) 341 ; 342 343 if (emaclite->txpp) { 344 /* The same operation with PONG TX */ 345 out_be32(®s->tx_pong_tsr, 0); 346 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong, 347 ENET_ADDR_LENGTH); 348 out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH); 349 out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR); 350 while ((in_be32(®s->tx_pong_tsr) & 351 XEL_TSR_PROG_MAC_ADDR) != 0) 352 ; 353 } 354 355 /* 356 * RX - RX_PING & RX_PONG initialization 357 */ 358 /* Write out the value to flush the RX buffer */ 359 out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK); 360 361 if (emaclite->rxpp) 362 out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK); 363 364 out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); 365 if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) 366 if (!setup_phy(dev)) 367 return -1; 368 369 debug("EmacLite Initialization complete\n"); 370 return 0; 371 } 372 373 static int xemaclite_txbufferavailable(struct xemaclite *emaclite) 374 { 375 u32 tmp; 376 struct emaclite_regs *regs = emaclite->regs; 377 378 /* 379 * Read the other buffer register 380 * and determine if the other buffer is available 381 */ 382 tmp = ~in_be32(®s->tx_ping_tsr); 383 if (emaclite->txpp) 384 tmp |= ~in_be32(®s->tx_pong_tsr); 385 386 return !(tmp & XEL_TSR_XMIT_BUSY_MASK); 387 } 388 389 static int emaclite_send(struct udevice *dev, void *ptr, int len) 390 { 391 u32 reg; 392 struct xemaclite *emaclite = dev_get_priv(dev); 393 struct emaclite_regs *regs = emaclite->regs; 394 395 u32 maxtry = 1000; 396 397 if (len > PKTSIZE) 398 len = PKTSIZE; 399 400 while (xemaclite_txbufferavailable(emaclite) && maxtry) { 401 udelay(10); 402 maxtry--; 403 } 404 405 if (!maxtry) { 406 printf("Error: Timeout waiting for ethernet TX buffer\n"); 407 /* Restart PING TX */ 408 out_be32(®s->tx_ping_tsr, 0); 409 if (emaclite->txpp) { 410 out_be32(®s->tx_pong_tsr, 0); 411 } 412 return -1; 413 } 414 415 /* Determine if the expected buffer address is empty */ 416 reg = in_be32(®s->tx_ping_tsr); 417 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { 418 debug("Send packet from tx_ping buffer\n"); 419 /* Write the frame to the buffer */ 420 xemaclite_alignedwrite(ptr, ®s->tx_ping, len); 421 out_be32(®s->tx_ping_tplr, len & 422 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)); 423 reg = in_be32(®s->tx_ping_tsr); 424 reg |= XEL_TSR_XMIT_BUSY_MASK; 425 out_be32(®s->tx_ping_tsr, reg); 426 return 0; 427 } 428 429 if (emaclite->txpp) { 430 /* Determine if the expected buffer address is empty */ 431 reg = in_be32(®s->tx_pong_tsr); 432 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { 433 debug("Send packet from tx_pong buffer\n"); 434 /* Write the frame to the buffer */ 435 xemaclite_alignedwrite(ptr, ®s->tx_pong, len); 436 out_be32(®s->tx_pong_tplr, len & 437 (XEL_TPLR_LENGTH_MASK_HI | 438 XEL_TPLR_LENGTH_MASK_LO)); 439 reg = in_be32(®s->tx_pong_tsr); 440 reg |= XEL_TSR_XMIT_BUSY_MASK; 441 out_be32(®s->tx_pong_tsr, reg); 442 return 0; 443 } 444 } 445 446 puts("Error while sending frame\n"); 447 return -1; 448 } 449 450 static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp) 451 { 452 u32 length, first_read, reg, attempt = 0; 453 void *addr, *ack; 454 struct xemaclite *emaclite = dev->priv; 455 struct emaclite_regs *regs = emaclite->regs; 456 struct ethernet_hdr *eth; 457 struct ip_udp_hdr *ip; 458 459 try_again: 460 if (!emaclite->use_rx_pong_buffer_next) { 461 reg = in_be32(®s->rx_ping_rsr); 462 debug("Testing data at rx_ping\n"); 463 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 464 debug("Data found in rx_ping buffer\n"); 465 addr = ®s->rx_ping; 466 ack = ®s->rx_ping_rsr; 467 } else { 468 debug("Data not found in rx_ping buffer\n"); 469 /* Pong buffer is not available - return immediately */ 470 if (!emaclite->rxpp) 471 return -1; 472 473 /* Try pong buffer if this is first attempt */ 474 if (attempt++) 475 return -1; 476 emaclite->use_rx_pong_buffer_next = 477 !emaclite->use_rx_pong_buffer_next; 478 goto try_again; 479 } 480 } else { 481 reg = in_be32(®s->rx_pong_rsr); 482 debug("Testing data at rx_pong\n"); 483 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 484 debug("Data found in rx_pong buffer\n"); 485 addr = ®s->rx_pong; 486 ack = ®s->rx_pong_rsr; 487 } else { 488 debug("Data not found in rx_pong buffer\n"); 489 /* Try ping buffer if this is first attempt */ 490 if (attempt++) 491 return -1; 492 emaclite->use_rx_pong_buffer_next = 493 !emaclite->use_rx_pong_buffer_next; 494 goto try_again; 495 } 496 } 497 498 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */ 499 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4); 500 xemaclite_alignedread(addr, etherrxbuff, first_read); 501 502 /* Detect real packet size */ 503 eth = (struct ethernet_hdr *)etherrxbuff; 504 switch (ntohs(eth->et_protlen)) { 505 case PROT_ARP: 506 length = first_read; 507 debug("ARP Packet %x\n", length); 508 break; 509 case PROT_IP: 510 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE); 511 length = ntohs(ip->ip_len); 512 length += ETHER_HDR_SIZE + ETH_FCS_LEN; 513 debug("IP Packet %x\n", length); 514 break; 515 default: 516 debug("Other Packet\n"); 517 length = PKTSIZE; 518 break; 519 } 520 521 /* Read the rest of the packet which is longer then first read */ 522 if (length != first_read) 523 xemaclite_alignedread(addr + first_read, 524 etherrxbuff + first_read, 525 length - first_read); 526 527 /* Acknowledge the frame */ 528 reg = in_be32(ack); 529 reg &= ~XEL_RSR_RECV_DONE_MASK; 530 out_be32(ack, reg); 531 532 debug("Packet receive from 0x%p, length %dB\n", addr, length); 533 *packetp = etherrxbuff; 534 return length; 535 } 536 537 static int emaclite_miiphy_read(struct mii_dev *bus, int addr, 538 int devad, int reg) 539 { 540 u32 ret; 541 u16 val = 0; 542 543 ret = phyread(bus->priv, addr, reg, &val); 544 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret); 545 return val; 546 } 547 548 static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad, 549 int reg, u16 value) 550 { 551 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); 552 return phywrite(bus->priv, addr, reg, value); 553 } 554 555 static int emaclite_probe(struct udevice *dev) 556 { 557 struct xemaclite *emaclite = dev_get_priv(dev); 558 int ret; 559 560 emaclite->bus = mdio_alloc(); 561 emaclite->bus->read = emaclite_miiphy_read; 562 emaclite->bus->write = emaclite_miiphy_write; 563 emaclite->bus->priv = emaclite; 564 strcpy(emaclite->bus->name, "emaclite"); 565 566 ret = mdio_register(emaclite->bus); 567 if (ret) 568 return ret; 569 570 return 0; 571 } 572 573 static int emaclite_remove(struct udevice *dev) 574 { 575 struct xemaclite *emaclite = dev_get_priv(dev); 576 577 free(emaclite->phydev); 578 mdio_unregister(emaclite->bus); 579 mdio_free(emaclite->bus); 580 581 return 0; 582 } 583 584 static const struct eth_ops emaclite_ops = { 585 .start = emaclite_start, 586 .send = emaclite_send, 587 .recv = emaclite_recv, 588 .stop = emaclite_stop, 589 }; 590 591 static int emaclite_ofdata_to_platdata(struct udevice *dev) 592 { 593 struct eth_pdata *pdata = dev_get_platdata(dev); 594 struct xemaclite *emaclite = dev_get_priv(dev); 595 int offset = 0; 596 597 pdata->iobase = (phys_addr_t)dev_get_addr(dev); 598 emaclite->regs = (struct emaclite_regs *)pdata->iobase; 599 600 emaclite->phyaddr = -1; 601 602 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, 603 "phy-handle"); 604 if (offset > 0) 605 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, 606 "reg", -1); 607 608 emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, 609 "xlnx,tx-ping-pong", 0); 610 emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, 611 "xlnx,rx-ping-pong", 0); 612 613 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs, 614 emaclite->phyaddr, emaclite->txpp, emaclite->rxpp); 615 616 return 0; 617 } 618 619 static const struct udevice_id emaclite_ids[] = { 620 { .compatible = "xlnx,xps-ethernetlite-1.00.a" }, 621 { } 622 }; 623 624 U_BOOT_DRIVER(emaclite) = { 625 .name = "emaclite", 626 .id = UCLASS_ETH, 627 .of_match = emaclite_ids, 628 .ofdata_to_platdata = emaclite_ofdata_to_platdata, 629 .probe = emaclite_probe, 630 .remove = emaclite_remove, 631 .ops = &emaclite_ops, 632 .priv_auto_alloc_size = sizeof(struct xemaclite), 633 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 634 }; 635