1 /* 2 * (C) Copyright 2007-2009 Michal Simek 3 * (C) Copyright 2003 Xilinx Inc. 4 * 5 * Michal SIMEK <monstr@monstr.eu> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <net.h> 28 #include <config.h> 29 #include <asm/io.h> 30 31 #undef DEBUG 32 33 #define ENET_MAX_MTU PKTSIZE 34 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN 35 #define ENET_ADDR_LENGTH 6 36 37 /* EmacLite constants */ 38 #define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ 39 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ 40 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ 41 #define XEL_RSR_OFFSET 0x17FC /* Rx status */ 42 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ 43 44 /* Xmit complete */ 45 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL 46 /* Xmit interrupt enable bit */ 47 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL 48 /* Buffer is active, SW bit only */ 49 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL 50 /* Program the MAC address */ 51 #define XEL_TSR_PROGRAM_MASK 0x00000002UL 52 /* define for programming the MAC address into the EMAC Lite */ 53 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 54 55 /* Transmit packet length upper byte */ 56 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL 57 /* Transmit packet length lower byte */ 58 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL 59 60 /* Recv complete */ 61 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL 62 /* Recv interrupt enable bit */ 63 #define XEL_RSR_RECV_IE_MASK 0x00000008UL 64 65 typedef struct { 66 unsigned int baseaddress; /* Base address for device (IPIF) */ 67 unsigned int nexttxbuffertouse; /* Next TX buffer to write to */ 68 unsigned int nextrxbuffertouse; /* Next RX buffer to read from */ 69 unsigned char deviceid; /* Unique ID of device - for future */ 70 } xemaclite; 71 72 static xemaclite emaclite; 73 74 static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ 75 76 /* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/ 77 #ifdef CONFIG_ENV_IS_NOWHERE 78 static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; 79 #else 80 static u8 emacaddr[ENET_ADDR_LENGTH]; 81 #endif 82 83 void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount) 84 { 85 unsigned int i; 86 u32 alignbuffer; 87 u32 *to32ptr; 88 u32 *from32ptr; 89 u8 *to8ptr; 90 u8 *from8ptr; 91 92 from32ptr = (u32 *) srcptr; 93 94 /* Word aligned buffer, no correction needed. */ 95 to32ptr = (u32 *) destptr; 96 while (bytecount > 3) { 97 *to32ptr++ = *from32ptr++; 98 bytecount -= 4; 99 } 100 to8ptr = (u8 *) to32ptr; 101 102 alignbuffer = *from32ptr++; 103 from8ptr = (u8 *) & alignbuffer; 104 105 for (i = 0; i < bytecount; i++) { 106 *to8ptr++ = *from8ptr++; 107 } 108 } 109 110 void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount) 111 { 112 unsigned i; 113 u32 alignbuffer; 114 u32 *to32ptr = (u32 *) destptr; 115 u32 *from32ptr; 116 u8 *to8ptr; 117 u8 *from8ptr; 118 119 from32ptr = (u32 *) srcptr; 120 while (bytecount > 3) { 121 122 *to32ptr++ = *from32ptr++; 123 bytecount -= 4; 124 } 125 126 alignbuffer = 0; 127 to8ptr = (u8 *) & alignbuffer; 128 from8ptr = (u8 *) from32ptr; 129 130 for (i = 0; i < bytecount; i++) { 131 *to8ptr++ = *from8ptr++; 132 } 133 134 *to32ptr++ = alignbuffer; 135 } 136 137 void eth_halt (void) 138 { 139 debug ("eth_halt\n"); 140 } 141 142 int eth_init (bd_t * bis) 143 { 144 uchar enetaddr[6]; 145 146 debug ("EmacLite Initialization Started\n"); 147 memset (&emaclite, 0, sizeof (xemaclite)); 148 emaclite.baseaddress = XILINX_EMACLITE_BASEADDR; 149 150 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { 151 memcpy(enetaddr, emacaddr, ENET_ADDR_LENGTH); 152 eth_setenv_enetaddr("ethaddr", enetaddr); 153 } 154 155 /* 156 * TX - TX_PING & TX_PONG initialization 157 */ 158 /* Restart PING TX */ 159 out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0); 160 /* Copy MAC address */ 161 xemaclite_alignedwrite (enetaddr, 162 emaclite.baseaddress, ENET_ADDR_LENGTH); 163 /* Set the length */ 164 out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); 165 /* Update the MAC address in the EMAC Lite */ 166 out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); 167 /* Wait for EMAC Lite to finish with the MAC address update */ 168 while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET) & 169 XEL_TSR_PROG_MAC_ADDR) != 0) ; 170 171 #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 172 /* The same operation with PONG TX */ 173 out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); 174 xemaclite_alignedwrite (enetaddr, emaclite.baseaddress + 175 XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); 176 out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); 177 out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 178 XEL_TSR_PROG_MAC_ADDR); 179 while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + 180 XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ; 181 #endif 182 183 /* 184 * RX - RX_PING & RX_PONG initialization 185 */ 186 /* Write out the value to flush the RX buffer */ 187 out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); 188 #ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG 189 out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, 190 XEL_RSR_RECV_IE_MASK); 191 #endif 192 193 debug ("EmacLite Initialization complete\n"); 194 return 0; 195 } 196 197 int xemaclite_txbufferavailable (xemaclite * instanceptr) 198 { 199 u32 reg; 200 u32 txpingbusy; 201 u32 txpongbusy; 202 /* 203 * Read the other buffer register 204 * and determine if the other buffer is available 205 */ 206 reg = in_be32 (instanceptr->baseaddress + 207 instanceptr->nexttxbuffertouse + 0); 208 txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == 209 XEL_TSR_XMIT_BUSY_MASK); 210 211 reg = in_be32 (instanceptr->baseaddress + 212 (instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0); 213 txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == 214 XEL_TSR_XMIT_BUSY_MASK); 215 216 return (!(txpingbusy && txpongbusy)); 217 } 218 219 int eth_send (volatile void *ptr, int len) { 220 221 unsigned int reg; 222 unsigned int baseaddress; 223 224 unsigned maxtry = 1000; 225 226 if (len > ENET_MAX_MTU) 227 len = ENET_MAX_MTU; 228 229 while (!xemaclite_txbufferavailable (&emaclite) && maxtry) { 230 udelay (10); 231 maxtry--; 232 } 233 234 if (!maxtry) { 235 printf ("Error: Timeout waiting for ethernet TX buffer\n"); 236 /* Restart PING TX */ 237 out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0); 238 #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 239 out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + 240 XEL_BUFFER_OFFSET, 0); 241 #endif 242 return 0; 243 } 244 245 /* Determine the expected TX buffer address */ 246 baseaddress = (emaclite.baseaddress + emaclite.nexttxbuffertouse); 247 248 /* Determine if the expected buffer address is empty */ 249 reg = in_be32 (baseaddress + XEL_TSR_OFFSET); 250 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) 251 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) 252 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { 253 254 #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 255 emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET; 256 #endif 257 debug ("Send packet from 0x%x\n", baseaddress); 258 /* Write the frame to the buffer */ 259 xemaclite_alignedwrite ((void *) ptr, baseaddress, len); 260 out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & 261 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); 262 reg = in_be32 (baseaddress + XEL_TSR_OFFSET); 263 reg |= XEL_TSR_XMIT_BUSY_MASK; 264 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) { 265 reg |= XEL_TSR_XMIT_ACTIVE_MASK; 266 } 267 out_be32 (baseaddress + XEL_TSR_OFFSET, reg); 268 return 1; 269 } 270 #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 271 /* Switch to second buffer */ 272 baseaddress ^= XEL_BUFFER_OFFSET; 273 /* Determine if the expected buffer address is empty */ 274 reg = in_be32 (baseaddress + XEL_TSR_OFFSET); 275 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) 276 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) 277 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { 278 debug ("Send packet from 0x%x\n", baseaddress); 279 /* Write the frame to the buffer */ 280 xemaclite_alignedwrite ((void *) ptr, baseaddress, len); 281 out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & 282 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); 283 reg = in_be32 (baseaddress + XEL_TSR_OFFSET); 284 reg |= XEL_TSR_XMIT_BUSY_MASK; 285 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) { 286 reg |= XEL_TSR_XMIT_ACTIVE_MASK; 287 } 288 out_be32 (baseaddress + XEL_TSR_OFFSET, reg); 289 return 1; 290 } 291 #endif 292 puts ("Error while sending frame\n"); 293 return 0; 294 } 295 296 int eth_rx (void) 297 { 298 unsigned int length; 299 unsigned int reg; 300 unsigned int baseaddress; 301 302 baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse; 303 reg = in_be32 (baseaddress + XEL_RSR_OFFSET); 304 debug ("Testing data at address 0x%x\n", baseaddress); 305 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 306 #ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG 307 emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET; 308 #endif 309 } else { 310 #ifndef CONFIG_XILINX_EMACLITE_RX_PING_PONG 311 debug ("No data was available - address 0x%x\n", baseaddress); 312 return 0; 313 #else 314 baseaddress ^= XEL_BUFFER_OFFSET; 315 reg = in_be32 (baseaddress + XEL_RSR_OFFSET); 316 if ((reg & XEL_RSR_RECV_DONE_MASK) != 317 XEL_RSR_RECV_DONE_MASK) { 318 debug ("No data was available - address 0x%x\n", 319 baseaddress); 320 return 0; 321 } 322 #endif 323 } 324 /* Get the length of the frame that arrived */ 325 switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) & 326 0xFFFF0000 ) >> 16) { 327 case 0x806: 328 length = 42 + 20; /* FIXME size of ARP */ 329 debug ("ARP Packet\n"); 330 break; 331 case 0x800: 332 length = 14 + 14 + 333 (((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) & 334 0xFFFF0000) >> 16); /* FIXME size of IP packet */ 335 debug ("IP Packet\n"); 336 break; 337 default: 338 debug ("Other Packet\n"); 339 length = ENET_MAX_MTU; 340 break; 341 } 342 343 xemaclite_alignedread ((u32 *) (baseaddress + XEL_RXBUFF_OFFSET), 344 etherrxbuff, length); 345 346 /* Acknowledge the frame */ 347 reg = in_be32 (baseaddress + XEL_RSR_OFFSET); 348 reg &= ~XEL_RSR_RECV_DONE_MASK; 349 out_be32 (baseaddress + XEL_RSR_OFFSET, reg); 350 351 debug ("Packet receive from 0x%x, length %dB\n", baseaddress, length); 352 NetReceive ((uchar *) etherrxbuff, length); 353 return 1; 354 355 } 356