1 /* 2 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2011 PetaLogix 4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <config.h> 10 #include <common.h> 11 #include <dm.h> 12 #include <net.h> 13 #include <malloc.h> 14 #include <asm/io.h> 15 #include <phy.h> 16 #include <miiphy.h> 17 #include <wait_bit.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 /* Link setup */ 22 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ 23 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ 24 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ 25 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ 26 27 /* Interrupt Status/Enable/Mask Registers bit definitions */ 28 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ 29 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ 30 31 /* Receive Configuration Word 1 (RCW1) Register bit definitions */ 32 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ 33 34 /* Transmitter Configuration (TC) Register bit definitions */ 35 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ 36 37 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF 38 39 /* MDIO Management Configuration (MC) Register bit definitions */ 40 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/ 41 42 /* MDIO Management Control Register (MCR) Register bit definitions */ 43 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ 44 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ 45 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ 46 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ 47 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ 48 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ 49 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ 50 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ 51 52 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */ 53 54 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */ 55 56 /* DMA macros */ 57 /* Bitmasks of XAXIDMA_CR_OFFSET register */ 58 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ 59 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ 60 61 /* Bitmasks of XAXIDMA_SR_OFFSET register */ 62 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */ 63 64 /* Bitmask for interrupts */ 65 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ 66 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ 67 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ 68 69 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */ 70 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ 71 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ 72 73 #define DMAALIGN 128 74 75 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); 76 77 /* Reflect dma offsets */ 78 struct axidma_reg { 79 u32 control; /* DMACR */ 80 u32 status; /* DMASR */ 81 u32 current; /* CURDESC low 32 bit */ 82 u32 current_hi; /* CURDESC high 32 bit */ 83 u32 tail; /* TAILDESC low 32 bit */ 84 u32 tail_hi; /* TAILDESC high 32 bit */ 85 }; 86 87 /* Private driver structures */ 88 struct axidma_priv { 89 struct axidma_reg *dmatx; 90 struct axidma_reg *dmarx; 91 int phyaddr; 92 struct axi_regs *iobase; 93 phy_interface_t interface; 94 struct phy_device *phydev; 95 struct mii_dev *bus; 96 u8 eth_hasnobuf; 97 }; 98 99 /* BD descriptors */ 100 struct axidma_bd { 101 u32 next; /* Next descriptor pointer */ 102 u32 reserved1; 103 u32 phys; /* Buffer address */ 104 u32 reserved2; 105 u32 reserved3; 106 u32 reserved4; 107 u32 cntrl; /* Control */ 108 u32 status; /* Status */ 109 u32 app0; 110 u32 app1; /* TX start << 16 | insert */ 111 u32 app2; /* TX csum seed */ 112 u32 app3; 113 u32 app4; 114 u32 sw_id_offset; 115 u32 reserved5; 116 u32 reserved6; 117 }; 118 119 /* Static BDs - driver uses only one BD */ 120 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN))); 121 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN))); 122 123 struct axi_regs { 124 u32 reserved[3]; 125 u32 is; /* 0xC: Interrupt status */ 126 u32 reserved2; 127 u32 ie; /* 0x14: Interrupt enable */ 128 u32 reserved3[251]; 129 u32 rcw1; /* 0x404: Rx Configuration Word 1 */ 130 u32 tc; /* 0x408: Tx Configuration */ 131 u32 reserved4; 132 u32 emmc; /* 0x410: EMAC mode configuration */ 133 u32 reserved5[59]; 134 u32 mdio_mc; /* 0x500: MII Management Config */ 135 u32 mdio_mcr; /* 0x504: MII Management Control */ 136 u32 mdio_mwd; /* 0x508: MII Management Write Data */ 137 u32 mdio_mrd; /* 0x50C: MII Management Read Data */ 138 u32 reserved6[124]; 139 u32 uaw0; /* 0x700: Unicast address word 0 */ 140 u32 uaw1; /* 0x704: Unicast address word 1 */ 141 }; 142 143 /* Use MII register 1 (MII status register) to detect PHY */ 144 #define PHY_DETECT_REG 1 145 146 /* 147 * Mask used to verify certain PHY features (or register contents) 148 * in the register above: 149 * 0x1000: 10Mbps full duplex support 150 * 0x0800: 10Mbps half duplex support 151 * 0x0008: Auto-negotiation support 152 */ 153 #define PHY_DETECT_MASK 0x1808 154 155 static inline int mdio_wait(struct axi_regs *regs) 156 { 157 u32 timeout = 200; 158 159 /* Wait till MDIO interface is ready to accept a new transaction. */ 160 while (timeout && (!(readl(®s->mdio_mcr) 161 & XAE_MDIO_MCR_READY_MASK))) { 162 timeout--; 163 udelay(1); 164 } 165 if (!timeout) { 166 printf("%s: Timeout\n", __func__); 167 return 1; 168 } 169 return 0; 170 } 171 172 /** 173 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write. 174 * @bd: pointer to BD descriptor structure 175 * @desc: Address offset of DMA descriptors 176 * 177 * This function writes the value into the corresponding Axi DMA register. 178 */ 179 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc) 180 { 181 #if defined(CONFIG_PHYS_64BIT) 182 writeq(bd, desc); 183 #else 184 writel((u32)bd, desc); 185 #endif 186 } 187 188 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum, 189 u16 *val) 190 { 191 struct axi_regs *regs = priv->iobase; 192 u32 mdioctrlreg = 0; 193 194 if (mdio_wait(regs)) 195 return 1; 196 197 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & 198 XAE_MDIO_MCR_PHYAD_MASK) | 199 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) 200 & XAE_MDIO_MCR_REGAD_MASK) | 201 XAE_MDIO_MCR_INITIATE_MASK | 202 XAE_MDIO_MCR_OP_READ_MASK; 203 204 writel(mdioctrlreg, ®s->mdio_mcr); 205 206 if (mdio_wait(regs)) 207 return 1; 208 209 /* Read data */ 210 *val = readl(®s->mdio_mrd); 211 return 0; 212 } 213 214 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, 215 u32 data) 216 { 217 struct axi_regs *regs = priv->iobase; 218 u32 mdioctrlreg = 0; 219 220 if (mdio_wait(regs)) 221 return 1; 222 223 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & 224 XAE_MDIO_MCR_PHYAD_MASK) | 225 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) 226 & XAE_MDIO_MCR_REGAD_MASK) | 227 XAE_MDIO_MCR_INITIATE_MASK | 228 XAE_MDIO_MCR_OP_WRITE_MASK; 229 230 /* Write data */ 231 writel(data, ®s->mdio_mwd); 232 233 writel(mdioctrlreg, ®s->mdio_mcr); 234 235 if (mdio_wait(regs)) 236 return 1; 237 238 return 0; 239 } 240 241 static int axiemac_phy_init(struct udevice *dev) 242 { 243 u16 phyreg; 244 u32 i, ret; 245 struct axidma_priv *priv = dev_get_priv(dev); 246 struct axi_regs *regs = priv->iobase; 247 struct phy_device *phydev; 248 249 u32 supported = SUPPORTED_10baseT_Half | 250 SUPPORTED_10baseT_Full | 251 SUPPORTED_100baseT_Half | 252 SUPPORTED_100baseT_Full | 253 SUPPORTED_1000baseT_Half | 254 SUPPORTED_1000baseT_Full; 255 256 /* Set default MDIO divisor */ 257 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc); 258 259 if (priv->phyaddr == -1) { 260 /* Detect the PHY address */ 261 for (i = 31; i >= 0; i--) { 262 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg); 263 if (!ret && (phyreg != 0xFFFF) && 264 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 265 /* Found a valid PHY address */ 266 priv->phyaddr = i; 267 debug("axiemac: Found valid phy address, %x\n", 268 i); 269 break; 270 } 271 } 272 } 273 274 /* Interface - look at tsec */ 275 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); 276 277 phydev->supported &= supported; 278 phydev->advertising = phydev->supported; 279 priv->phydev = phydev; 280 phy_config(phydev); 281 282 return 0; 283 } 284 285 /* Setting axi emac and phy to proper setting */ 286 static int setup_phy(struct udevice *dev) 287 { 288 u16 temp; 289 u32 speed, emmc_reg, ret; 290 struct axidma_priv *priv = dev_get_priv(dev); 291 struct axi_regs *regs = priv->iobase; 292 struct phy_device *phydev = priv->phydev; 293 294 if (priv->interface == PHY_INTERFACE_MODE_SGMII) { 295 /* 296 * In SGMII cases the isolate bit might set 297 * after DMA and ethernet resets and hence 298 * check and clear if set. 299 */ 300 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp); 301 if (ret) 302 return 0; 303 if (temp & BMCR_ISOLATE) { 304 temp &= ~BMCR_ISOLATE; 305 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp); 306 if (ret) 307 return 0; 308 } 309 } 310 311 if (phy_startup(phydev)) { 312 printf("axiemac: could not initialize PHY %s\n", 313 phydev->dev->name); 314 return 0; 315 } 316 if (!phydev->link) { 317 printf("%s: No link.\n", phydev->dev->name); 318 return 0; 319 } 320 321 switch (phydev->speed) { 322 case 1000: 323 speed = XAE_EMMC_LINKSPD_1000; 324 break; 325 case 100: 326 speed = XAE_EMMC_LINKSPD_100; 327 break; 328 case 10: 329 speed = XAE_EMMC_LINKSPD_10; 330 break; 331 default: 332 return 0; 333 } 334 335 /* Setup the emac for the phy speed */ 336 emmc_reg = readl(®s->emmc); 337 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK; 338 emmc_reg |= speed; 339 340 /* Write new speed setting out to Axi Ethernet */ 341 writel(emmc_reg, ®s->emmc); 342 343 /* 344 * Setting the operating speed of the MAC needs a delay. There 345 * doesn't seem to be register to poll, so please consider this 346 * during your application design. 347 */ 348 udelay(1); 349 350 return 1; 351 } 352 353 /* STOP DMA transfers */ 354 static void axiemac_stop(struct udevice *dev) 355 { 356 struct axidma_priv *priv = dev_get_priv(dev); 357 u32 temp; 358 359 /* Stop the hardware */ 360 temp = readl(&priv->dmatx->control); 361 temp &= ~XAXIDMA_CR_RUNSTOP_MASK; 362 writel(temp, &priv->dmatx->control); 363 364 temp = readl(&priv->dmarx->control); 365 temp &= ~XAXIDMA_CR_RUNSTOP_MASK; 366 writel(temp, &priv->dmarx->control); 367 368 debug("axiemac: Halted\n"); 369 } 370 371 static int axi_ethernet_init(struct axidma_priv *priv) 372 { 373 struct axi_regs *regs = priv->iobase; 374 int err; 375 376 /* 377 * Check the status of the MgtRdy bit in the interrupt status 378 * registers. This must be done to allow the MGT clock to become stable 379 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads 380 * will be valid until this bit is valid. 381 * The bit is always a 1 for all other PHY interfaces. 382 * Interrupt status and enable registers are not available in non 383 * processor mode and hence bypass in this mode 384 */ 385 if (!priv->eth_hasnobuf) { 386 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK, 387 true, 200, false); 388 if (err) { 389 printf("%s: Timeout\n", __func__); 390 return 1; 391 } 392 393 /* 394 * Stop the device and reset HW 395 * Disable interrupts 396 */ 397 writel(0, ®s->ie); 398 } 399 400 /* Disable the receiver */ 401 writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1); 402 403 /* 404 * Stopping the receiver in mid-packet causes a dropped packet 405 * indication from HW. Clear it. 406 */ 407 if (!priv->eth_hasnobuf) { 408 /* Set the interrupt status register to clear the interrupt */ 409 writel(XAE_INT_RXRJECT_MASK, ®s->is); 410 } 411 412 /* Setup HW */ 413 /* Set default MDIO divisor */ 414 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc); 415 416 debug("axiemac: InitHw done\n"); 417 return 0; 418 } 419 420 static int axiemac_write_hwaddr(struct udevice *dev) 421 { 422 struct eth_pdata *pdata = dev_get_platdata(dev); 423 struct axidma_priv *priv = dev_get_priv(dev); 424 struct axi_regs *regs = priv->iobase; 425 426 /* Set the MAC address */ 427 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) | 428 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0])); 429 writel(val, ®s->uaw0); 430 431 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4]; 432 val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK; 433 writel(val, ®s->uaw1); 434 return 0; 435 } 436 437 /* Reset DMA engine */ 438 static void axi_dma_init(struct axidma_priv *priv) 439 { 440 u32 timeout = 500; 441 442 /* Reset the engine so the hardware starts from a known state */ 443 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control); 444 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control); 445 446 /* At the initialization time, hardware should finish reset quickly */ 447 while (timeout--) { 448 /* Check transmit/receive channel */ 449 /* Reset is done when the reset bit is low */ 450 if (!((readl(&priv->dmatx->control) | 451 readl(&priv->dmarx->control)) 452 & XAXIDMA_CR_RESET_MASK)) { 453 break; 454 } 455 } 456 if (!timeout) 457 printf("%s: Timeout\n", __func__); 458 } 459 460 static int axiemac_start(struct udevice *dev) 461 { 462 struct axidma_priv *priv = dev_get_priv(dev); 463 struct axi_regs *regs = priv->iobase; 464 u32 temp; 465 466 debug("axiemac: Init started\n"); 467 /* 468 * Initialize AXIDMA engine. AXIDMA engine must be initialized before 469 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is 470 * reset, and since AXIDMA reset line is connected to AxiEthernet, this 471 * would ensure a reset of AxiEthernet. 472 */ 473 axi_dma_init(priv); 474 475 /* Initialize AxiEthernet hardware. */ 476 if (axi_ethernet_init(priv)) 477 return -1; 478 479 /* Disable all RX interrupts before RxBD space setup */ 480 temp = readl(&priv->dmarx->control); 481 temp &= ~XAXIDMA_IRQ_ALL_MASK; 482 writel(temp, &priv->dmarx->control); 483 484 /* Start DMA RX channel. Now it's ready to receive data.*/ 485 axienet_dma_write(&rx_bd, &priv->dmarx->current); 486 487 /* Setup the BD. */ 488 memset(&rx_bd, 0, sizeof(rx_bd)); 489 rx_bd.next = (u32)&rx_bd; 490 rx_bd.phys = (u32)&rxframe; 491 rx_bd.cntrl = sizeof(rxframe); 492 /* Flush the last BD so DMA core could see the updates */ 493 flush_cache((u32)&rx_bd, sizeof(rx_bd)); 494 495 /* It is necessary to flush rxframe because if you don't do it 496 * then cache can contain uninitialized data */ 497 flush_cache((u32)&rxframe, sizeof(rxframe)); 498 499 /* Start the hardware */ 500 temp = readl(&priv->dmarx->control); 501 temp |= XAXIDMA_CR_RUNSTOP_MASK; 502 writel(temp, &priv->dmarx->control); 503 504 /* Rx BD is ready - start */ 505 axienet_dma_write(&rx_bd, &priv->dmarx->tail); 506 507 /* Enable TX */ 508 writel(XAE_TC_TX_MASK, ®s->tc); 509 /* Enable RX */ 510 writel(XAE_RCW1_RX_MASK, ®s->rcw1); 511 512 /* PHY setup */ 513 if (!setup_phy(dev)) { 514 axiemac_stop(dev); 515 return -1; 516 } 517 518 debug("axiemac: Init complete\n"); 519 return 0; 520 } 521 522 static int axiemac_send(struct udevice *dev, void *ptr, int len) 523 { 524 struct axidma_priv *priv = dev_get_priv(dev); 525 u32 timeout; 526 527 if (len > PKTSIZE_ALIGN) 528 len = PKTSIZE_ALIGN; 529 530 /* Flush packet to main memory to be trasfered by DMA */ 531 flush_cache((u32)ptr, len); 532 533 /* Setup Tx BD */ 534 memset(&tx_bd, 0, sizeof(tx_bd)); 535 /* At the end of the ring, link the last BD back to the top */ 536 tx_bd.next = (u32)&tx_bd; 537 tx_bd.phys = (u32)ptr; 538 /* Save len */ 539 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK | 540 XAXIDMA_BD_CTRL_TXEOF_MASK; 541 542 /* Flush the last BD so DMA core could see the updates */ 543 flush_cache((u32)&tx_bd, sizeof(tx_bd)); 544 545 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) { 546 u32 temp; 547 axienet_dma_write(&tx_bd, &priv->dmatx->current); 548 /* Start the hardware */ 549 temp = readl(&priv->dmatx->control); 550 temp |= XAXIDMA_CR_RUNSTOP_MASK; 551 writel(temp, &priv->dmatx->control); 552 } 553 554 /* Start transfer */ 555 axienet_dma_write(&tx_bd, &priv->dmatx->tail); 556 557 /* Wait for transmission to complete */ 558 debug("axiemac: Waiting for tx to be done\n"); 559 timeout = 200; 560 while (timeout && (!(readl(&priv->dmatx->status) & 561 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) { 562 timeout--; 563 udelay(1); 564 } 565 if (!timeout) { 566 printf("%s: Timeout\n", __func__); 567 return 1; 568 } 569 570 debug("axiemac: Sending complete\n"); 571 return 0; 572 } 573 574 static int isrxready(struct axidma_priv *priv) 575 { 576 u32 status; 577 578 /* Read pending interrupts */ 579 status = readl(&priv->dmarx->status); 580 581 /* Acknowledge pending interrupts */ 582 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status); 583 584 /* 585 * If Reception done interrupt is asserted, call RX call back function 586 * to handle the processed BDs and then raise the according flag. 587 */ 588 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) 589 return 1; 590 591 return 0; 592 } 593 594 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) 595 { 596 u32 length; 597 struct axidma_priv *priv = dev_get_priv(dev); 598 u32 temp; 599 600 /* Wait for an incoming packet */ 601 if (!isrxready(priv)) 602 return -1; 603 604 debug("axiemac: RX data ready\n"); 605 606 /* Disable IRQ for a moment till packet is handled */ 607 temp = readl(&priv->dmarx->control); 608 temp &= ~XAXIDMA_IRQ_ALL_MASK; 609 writel(temp, &priv->dmarx->control); 610 if (!priv->eth_hasnobuf) 611 length = rx_bd.app4 & 0xFFFF; /* max length mask */ 612 else 613 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK; 614 615 #ifdef DEBUG 616 print_buffer(&rxframe, &rxframe[0], 1, length, 16); 617 #endif 618 619 *packetp = rxframe; 620 return length; 621 } 622 623 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length) 624 { 625 struct axidma_priv *priv = dev_get_priv(dev); 626 627 #ifdef DEBUG 628 /* It is useful to clear buffer to be sure that it is consistent */ 629 memset(rxframe, 0, sizeof(rxframe)); 630 #endif 631 /* Setup RxBD */ 632 /* Clear the whole buffer and setup it again - all flags are cleared */ 633 memset(&rx_bd, 0, sizeof(rx_bd)); 634 rx_bd.next = (u32)&rx_bd; 635 rx_bd.phys = (u32)&rxframe; 636 rx_bd.cntrl = sizeof(rxframe); 637 638 /* Write bd to HW */ 639 flush_cache((u32)&rx_bd, sizeof(rx_bd)); 640 641 /* It is necessary to flush rxframe because if you don't do it 642 * then cache will contain previous packet */ 643 flush_cache((u32)&rxframe, sizeof(rxframe)); 644 645 /* Rx BD is ready - start again */ 646 axienet_dma_write(&rx_bd, &priv->dmarx->tail); 647 648 debug("axiemac: RX completed, framelength = %d\n", length); 649 650 return 0; 651 } 652 653 static int axiemac_miiphy_read(struct mii_dev *bus, int addr, 654 int devad, int reg) 655 { 656 int ret; 657 u16 value; 658 659 ret = phyread(bus->priv, addr, reg, &value); 660 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, 661 value, ret); 662 return value; 663 } 664 665 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad, 666 int reg, u16 value) 667 { 668 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); 669 return phywrite(bus->priv, addr, reg, value); 670 } 671 672 static int axi_emac_probe(struct udevice *dev) 673 { 674 struct axidma_priv *priv = dev_get_priv(dev); 675 int ret; 676 677 priv->bus = mdio_alloc(); 678 priv->bus->read = axiemac_miiphy_read; 679 priv->bus->write = axiemac_miiphy_write; 680 priv->bus->priv = priv; 681 682 ret = mdio_register_seq(priv->bus, dev->seq); 683 if (ret) 684 return ret; 685 686 axiemac_phy_init(dev); 687 688 return 0; 689 } 690 691 static int axi_emac_remove(struct udevice *dev) 692 { 693 struct axidma_priv *priv = dev_get_priv(dev); 694 695 free(priv->phydev); 696 mdio_unregister(priv->bus); 697 mdio_free(priv->bus); 698 699 return 0; 700 } 701 702 static const struct eth_ops axi_emac_ops = { 703 .start = axiemac_start, 704 .send = axiemac_send, 705 .recv = axiemac_recv, 706 .free_pkt = axiemac_free_pkt, 707 .stop = axiemac_stop, 708 .write_hwaddr = axiemac_write_hwaddr, 709 }; 710 711 static int axi_emac_ofdata_to_platdata(struct udevice *dev) 712 { 713 struct eth_pdata *pdata = dev_get_platdata(dev); 714 struct axidma_priv *priv = dev_get_priv(dev); 715 int node = dev_of_offset(dev); 716 int offset = 0; 717 const char *phy_mode; 718 719 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); 720 priv->iobase = (struct axi_regs *)pdata->iobase; 721 722 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, 723 "axistream-connected"); 724 if (offset <= 0) { 725 printf("%s: axistream is not found\n", __func__); 726 return -EINVAL; 727 } 728 priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob, 729 offset, "reg"); 730 if (!priv->dmatx) { 731 printf("%s: axi_dma register space not found\n", __func__); 732 return -EINVAL; 733 } 734 /* RX channel offset is 0x30 */ 735 priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30); 736 737 priv->phyaddr = -1; 738 739 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); 740 if (offset > 0) 741 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); 742 743 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); 744 if (phy_mode) 745 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 746 if (pdata->phy_interface == -1) { 747 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 748 return -EINVAL; 749 } 750 priv->interface = pdata->phy_interface; 751 752 priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, 753 "xlnx,eth-hasnobuf"); 754 755 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, 756 priv->phyaddr, phy_string_for_interface(priv->interface)); 757 758 return 0; 759 } 760 761 static const struct udevice_id axi_emac_ids[] = { 762 { .compatible = "xlnx,axi-ethernet-1.00.a" }, 763 { } 764 }; 765 766 U_BOOT_DRIVER(axi_emac) = { 767 .name = "axi_emac", 768 .id = UCLASS_ETH, 769 .of_match = axi_emac_ids, 770 .ofdata_to_platdata = axi_emac_ofdata_to_platdata, 771 .probe = axi_emac_probe, 772 .remove = axi_emac_remove, 773 .ops = &axi_emac_ops, 774 .priv_auto_alloc_size = sizeof(struct axidma_priv), 775 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 776 }; 777