14f1ec4c1SMichal Simek /* 24f1ec4c1SMichal Simek * Copyright (C) 2011 Michal Simek <monstr@monstr.eu> 34f1ec4c1SMichal Simek * Copyright (C) 2011 PetaLogix 44f1ec4c1SMichal Simek * Copyright (C) 2010 Xilinx, Inc. All rights reserved. 54f1ec4c1SMichal Simek * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 74f1ec4c1SMichal Simek */ 84f1ec4c1SMichal Simek 94f1ec4c1SMichal Simek #include <config.h> 104f1ec4c1SMichal Simek #include <common.h> 1175cc93faSMichal Simek #include <dm.h> 124f1ec4c1SMichal Simek #include <net.h> 134f1ec4c1SMichal Simek #include <malloc.h> 144f1ec4c1SMichal Simek #include <asm/io.h> 154f1ec4c1SMichal Simek #include <phy.h> 164f1ec4c1SMichal Simek #include <miiphy.h> 174f1ec4c1SMichal Simek 1875cc93faSMichal Simek DECLARE_GLOBAL_DATA_PTR; 1975cc93faSMichal Simek 204f1ec4c1SMichal Simek /* Link setup */ 214f1ec4c1SMichal Simek #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ 224f1ec4c1SMichal Simek #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ 234f1ec4c1SMichal Simek #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ 244f1ec4c1SMichal Simek #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ 254f1ec4c1SMichal Simek 264f1ec4c1SMichal Simek /* Interrupt Status/Enable/Mask Registers bit definitions */ 274f1ec4c1SMichal Simek #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ 284f1ec4c1SMichal Simek #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ 294f1ec4c1SMichal Simek 304f1ec4c1SMichal Simek /* Receive Configuration Word 1 (RCW1) Register bit definitions */ 314f1ec4c1SMichal Simek #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ 324f1ec4c1SMichal Simek 334f1ec4c1SMichal Simek /* Transmitter Configuration (TC) Register bit definitions */ 344f1ec4c1SMichal Simek #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ 354f1ec4c1SMichal Simek 364f1ec4c1SMichal Simek #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF 374f1ec4c1SMichal Simek 384f1ec4c1SMichal Simek /* MDIO Management Configuration (MC) Register bit definitions */ 394f1ec4c1SMichal Simek #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/ 404f1ec4c1SMichal Simek 414f1ec4c1SMichal Simek /* MDIO Management Control Register (MCR) Register bit definitions */ 424f1ec4c1SMichal Simek #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ 434f1ec4c1SMichal Simek #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ 444f1ec4c1SMichal Simek #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ 454f1ec4c1SMichal Simek #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ 464f1ec4c1SMichal Simek #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ 474f1ec4c1SMichal Simek #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ 484f1ec4c1SMichal Simek #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ 494f1ec4c1SMichal Simek #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ 504f1ec4c1SMichal Simek 514f1ec4c1SMichal Simek #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */ 524f1ec4c1SMichal Simek 534f1ec4c1SMichal Simek /* DMA macros */ 544f1ec4c1SMichal Simek /* Bitmasks of XAXIDMA_CR_OFFSET register */ 554f1ec4c1SMichal Simek #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ 564f1ec4c1SMichal Simek #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ 574f1ec4c1SMichal Simek 584f1ec4c1SMichal Simek /* Bitmasks of XAXIDMA_SR_OFFSET register */ 594f1ec4c1SMichal Simek #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */ 604f1ec4c1SMichal Simek 614f1ec4c1SMichal Simek /* Bitmask for interrupts */ 624f1ec4c1SMichal Simek #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ 634f1ec4c1SMichal Simek #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ 644f1ec4c1SMichal Simek #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ 654f1ec4c1SMichal Simek 664f1ec4c1SMichal Simek /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */ 674f1ec4c1SMichal Simek #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ 684f1ec4c1SMichal Simek #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ 694f1ec4c1SMichal Simek 704f1ec4c1SMichal Simek #define DMAALIGN 128 714f1ec4c1SMichal Simek 724f1ec4c1SMichal Simek static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); 734f1ec4c1SMichal Simek 744f1ec4c1SMichal Simek /* Reflect dma offsets */ 754f1ec4c1SMichal Simek struct axidma_reg { 764f1ec4c1SMichal Simek u32 control; /* DMACR */ 774f1ec4c1SMichal Simek u32 status; /* DMASR */ 784f1ec4c1SMichal Simek u32 current; /* CURDESC */ 794f1ec4c1SMichal Simek u32 reserved; 804f1ec4c1SMichal Simek u32 tail; /* TAILDESC */ 814f1ec4c1SMichal Simek }; 824f1ec4c1SMichal Simek 834f1ec4c1SMichal Simek /* Private driver structures */ 844f1ec4c1SMichal Simek struct axidma_priv { 854f1ec4c1SMichal Simek struct axidma_reg *dmatx; 864f1ec4c1SMichal Simek struct axidma_reg *dmarx; 874f1ec4c1SMichal Simek int phyaddr; 886609f35bSMichal Simek struct axi_regs *iobase; 8975cc93faSMichal Simek phy_interface_t interface; 904f1ec4c1SMichal Simek struct phy_device *phydev; 914f1ec4c1SMichal Simek struct mii_dev *bus; 924f1ec4c1SMichal Simek }; 934f1ec4c1SMichal Simek 944f1ec4c1SMichal Simek /* BD descriptors */ 954f1ec4c1SMichal Simek struct axidma_bd { 964f1ec4c1SMichal Simek u32 next; /* Next descriptor pointer */ 974f1ec4c1SMichal Simek u32 reserved1; 984f1ec4c1SMichal Simek u32 phys; /* Buffer address */ 994f1ec4c1SMichal Simek u32 reserved2; 1004f1ec4c1SMichal Simek u32 reserved3; 1014f1ec4c1SMichal Simek u32 reserved4; 1024f1ec4c1SMichal Simek u32 cntrl; /* Control */ 1034f1ec4c1SMichal Simek u32 status; /* Status */ 1044f1ec4c1SMichal Simek u32 app0; 1054f1ec4c1SMichal Simek u32 app1; /* TX start << 16 | insert */ 1064f1ec4c1SMichal Simek u32 app2; /* TX csum seed */ 1074f1ec4c1SMichal Simek u32 app3; 1084f1ec4c1SMichal Simek u32 app4; 1094f1ec4c1SMichal Simek u32 sw_id_offset; 1104f1ec4c1SMichal Simek u32 reserved5; 1114f1ec4c1SMichal Simek u32 reserved6; 1124f1ec4c1SMichal Simek }; 1134f1ec4c1SMichal Simek 1144f1ec4c1SMichal Simek /* Static BDs - driver uses only one BD */ 1154f1ec4c1SMichal Simek static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN))); 1164f1ec4c1SMichal Simek static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN))); 1174f1ec4c1SMichal Simek 1184f1ec4c1SMichal Simek struct axi_regs { 1194f1ec4c1SMichal Simek u32 reserved[3]; 1204f1ec4c1SMichal Simek u32 is; /* 0xC: Interrupt status */ 1214f1ec4c1SMichal Simek u32 reserved2; 1224f1ec4c1SMichal Simek u32 ie; /* 0x14: Interrupt enable */ 1234f1ec4c1SMichal Simek u32 reserved3[251]; 1244f1ec4c1SMichal Simek u32 rcw1; /* 0x404: Rx Configuration Word 1 */ 1254f1ec4c1SMichal Simek u32 tc; /* 0x408: Tx Configuration */ 1264f1ec4c1SMichal Simek u32 reserved4; 1274f1ec4c1SMichal Simek u32 emmc; /* 0x410: EMAC mode configuration */ 1284f1ec4c1SMichal Simek u32 reserved5[59]; 1294f1ec4c1SMichal Simek u32 mdio_mc; /* 0x500: MII Management Config */ 1304f1ec4c1SMichal Simek u32 mdio_mcr; /* 0x504: MII Management Control */ 1314f1ec4c1SMichal Simek u32 mdio_mwd; /* 0x508: MII Management Write Data */ 1324f1ec4c1SMichal Simek u32 mdio_mrd; /* 0x50C: MII Management Read Data */ 1334f1ec4c1SMichal Simek u32 reserved6[124]; 1344f1ec4c1SMichal Simek u32 uaw0; /* 0x700: Unicast address word 0 */ 1354f1ec4c1SMichal Simek u32 uaw1; /* 0x704: Unicast address word 1 */ 1364f1ec4c1SMichal Simek }; 1374f1ec4c1SMichal Simek 1384f1ec4c1SMichal Simek /* Use MII register 1 (MII status register) to detect PHY */ 1394f1ec4c1SMichal Simek #define PHY_DETECT_REG 1 1404f1ec4c1SMichal Simek 1414f1ec4c1SMichal Simek /* 1424f1ec4c1SMichal Simek * Mask used to verify certain PHY features (or register contents) 1434f1ec4c1SMichal Simek * in the register above: 1444f1ec4c1SMichal Simek * 0x1000: 10Mbps full duplex support 1454f1ec4c1SMichal Simek * 0x0800: 10Mbps half duplex support 1464f1ec4c1SMichal Simek * 0x0008: Auto-negotiation support 1474f1ec4c1SMichal Simek */ 1484f1ec4c1SMichal Simek #define PHY_DETECT_MASK 0x1808 1494f1ec4c1SMichal Simek 150f36bbcceSMichal Simek static inline int mdio_wait(struct axi_regs *regs) 1514f1ec4c1SMichal Simek { 1524f1ec4c1SMichal Simek u32 timeout = 200; 1534f1ec4c1SMichal Simek 1544f1ec4c1SMichal Simek /* Wait till MDIO interface is ready to accept a new transaction. */ 1554f1ec4c1SMichal Simek while (timeout && (!(in_be32(®s->mdio_mcr) 1564f1ec4c1SMichal Simek & XAE_MDIO_MCR_READY_MASK))) { 1574f1ec4c1SMichal Simek timeout--; 1584f1ec4c1SMichal Simek udelay(1); 1594f1ec4c1SMichal Simek } 1604f1ec4c1SMichal Simek if (!timeout) { 1614f1ec4c1SMichal Simek printf("%s: Timeout\n", __func__); 1624f1ec4c1SMichal Simek return 1; 1634f1ec4c1SMichal Simek } 1644f1ec4c1SMichal Simek return 0; 1654f1ec4c1SMichal Simek } 1664f1ec4c1SMichal Simek 1670d78abf5SMichal Simek static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum, 1684f1ec4c1SMichal Simek u16 *val) 1694f1ec4c1SMichal Simek { 1700d78abf5SMichal Simek struct axi_regs *regs = priv->iobase; 1714f1ec4c1SMichal Simek u32 mdioctrlreg = 0; 1724f1ec4c1SMichal Simek 173f36bbcceSMichal Simek if (mdio_wait(regs)) 1744f1ec4c1SMichal Simek return 1; 1754f1ec4c1SMichal Simek 1764f1ec4c1SMichal Simek mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & 1774f1ec4c1SMichal Simek XAE_MDIO_MCR_PHYAD_MASK) | 1784f1ec4c1SMichal Simek ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) 1794f1ec4c1SMichal Simek & XAE_MDIO_MCR_REGAD_MASK) | 1804f1ec4c1SMichal Simek XAE_MDIO_MCR_INITIATE_MASK | 1814f1ec4c1SMichal Simek XAE_MDIO_MCR_OP_READ_MASK; 1824f1ec4c1SMichal Simek 1834f1ec4c1SMichal Simek out_be32(®s->mdio_mcr, mdioctrlreg); 1844f1ec4c1SMichal Simek 185f36bbcceSMichal Simek if (mdio_wait(regs)) 1864f1ec4c1SMichal Simek return 1; 1874f1ec4c1SMichal Simek 1884f1ec4c1SMichal Simek /* Read data */ 1894f1ec4c1SMichal Simek *val = in_be32(®s->mdio_mrd); 1904f1ec4c1SMichal Simek return 0; 1914f1ec4c1SMichal Simek } 1924f1ec4c1SMichal Simek 1930d78abf5SMichal Simek static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, 1944f1ec4c1SMichal Simek u32 data) 1954f1ec4c1SMichal Simek { 1960d78abf5SMichal Simek struct axi_regs *regs = priv->iobase; 1974f1ec4c1SMichal Simek u32 mdioctrlreg = 0; 1984f1ec4c1SMichal Simek 199f36bbcceSMichal Simek if (mdio_wait(regs)) 2004f1ec4c1SMichal Simek return 1; 2014f1ec4c1SMichal Simek 2024f1ec4c1SMichal Simek mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & 2034f1ec4c1SMichal Simek XAE_MDIO_MCR_PHYAD_MASK) | 2044f1ec4c1SMichal Simek ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) 2054f1ec4c1SMichal Simek & XAE_MDIO_MCR_REGAD_MASK) | 2064f1ec4c1SMichal Simek XAE_MDIO_MCR_INITIATE_MASK | 2074f1ec4c1SMichal Simek XAE_MDIO_MCR_OP_WRITE_MASK; 2084f1ec4c1SMichal Simek 2094f1ec4c1SMichal Simek /* Write data */ 2104f1ec4c1SMichal Simek out_be32(®s->mdio_mwd, data); 2114f1ec4c1SMichal Simek 2124f1ec4c1SMichal Simek out_be32(®s->mdio_mcr, mdioctrlreg); 2134f1ec4c1SMichal Simek 214f36bbcceSMichal Simek if (mdio_wait(regs)) 2154f1ec4c1SMichal Simek return 1; 2164f1ec4c1SMichal Simek 2174f1ec4c1SMichal Simek return 0; 2184f1ec4c1SMichal Simek } 2194f1ec4c1SMichal Simek 2205d0449d4SMichal Simek static int axiemac_phy_init(struct udevice *dev) 2214f1ec4c1SMichal Simek { 2224f1ec4c1SMichal Simek u16 phyreg; 2235d0449d4SMichal Simek u32 i, ret; 22475cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev); 2256609f35bSMichal Simek struct axi_regs *regs = priv->iobase; 2264f1ec4c1SMichal Simek struct phy_device *phydev; 2274f1ec4c1SMichal Simek 2284f1ec4c1SMichal Simek u32 supported = SUPPORTED_10baseT_Half | 2294f1ec4c1SMichal Simek SUPPORTED_10baseT_Full | 2304f1ec4c1SMichal Simek SUPPORTED_100baseT_Half | 2314f1ec4c1SMichal Simek SUPPORTED_100baseT_Full | 2324f1ec4c1SMichal Simek SUPPORTED_1000baseT_Half | 2334f1ec4c1SMichal Simek SUPPORTED_1000baseT_Full; 2344f1ec4c1SMichal Simek 2355d0449d4SMichal Simek /* Set default MDIO divisor */ 2365d0449d4SMichal Simek out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK); 2375d0449d4SMichal Simek 2384f1ec4c1SMichal Simek if (priv->phyaddr == -1) { 2394f1ec4c1SMichal Simek /* Detect the PHY address */ 2404f1ec4c1SMichal Simek for (i = 31; i >= 0; i--) { 2410d78abf5SMichal Simek ret = phyread(priv, i, PHY_DETECT_REG, &phyreg); 2424f1ec4c1SMichal Simek if (!ret && (phyreg != 0xFFFF) && 2434f1ec4c1SMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 2444f1ec4c1SMichal Simek /* Found a valid PHY address */ 2454f1ec4c1SMichal Simek priv->phyaddr = i; 2464f1ec4c1SMichal Simek debug("axiemac: Found valid phy address, %x\n", 2472652a621SMichal Simek i); 2484f1ec4c1SMichal Simek break; 2494f1ec4c1SMichal Simek } 2504f1ec4c1SMichal Simek } 2514f1ec4c1SMichal Simek } 2524f1ec4c1SMichal Simek 2534f1ec4c1SMichal Simek /* Interface - look at tsec */ 2549c0da762SSiva Durga Prasad Paladugu phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); 2554f1ec4c1SMichal Simek 2564f1ec4c1SMichal Simek phydev->supported &= supported; 2574f1ec4c1SMichal Simek phydev->advertising = phydev->supported; 2584f1ec4c1SMichal Simek priv->phydev = phydev; 2594f1ec4c1SMichal Simek phy_config(phydev); 2605d0449d4SMichal Simek 2615d0449d4SMichal Simek return 0; 2625d0449d4SMichal Simek } 2635d0449d4SMichal Simek 2645d0449d4SMichal Simek /* Setting axi emac and phy to proper setting */ 2655d0449d4SMichal Simek static int setup_phy(struct udevice *dev) 2665d0449d4SMichal Simek { 2678964f241SSiva Durga Prasad Paladugu u16 temp; 2688964f241SSiva Durga Prasad Paladugu u32 speed, emmc_reg, ret; 2695d0449d4SMichal Simek struct axidma_priv *priv = dev_get_priv(dev); 2705d0449d4SMichal Simek struct axi_regs *regs = priv->iobase; 2715d0449d4SMichal Simek struct phy_device *phydev = priv->phydev; 2725d0449d4SMichal Simek 2738964f241SSiva Durga Prasad Paladugu if (priv->interface == PHY_INTERFACE_MODE_SGMII) { 2748964f241SSiva Durga Prasad Paladugu /* 2758964f241SSiva Durga Prasad Paladugu * In SGMII cases the isolate bit might set 2768964f241SSiva Durga Prasad Paladugu * after DMA and ethernet resets and hence 2778964f241SSiva Durga Prasad Paladugu * check and clear if set. 2788964f241SSiva Durga Prasad Paladugu */ 2798964f241SSiva Durga Prasad Paladugu ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp); 2808964f241SSiva Durga Prasad Paladugu if (ret) 2818964f241SSiva Durga Prasad Paladugu return 0; 2828964f241SSiva Durga Prasad Paladugu if (temp & BMCR_ISOLATE) { 2838964f241SSiva Durga Prasad Paladugu temp &= ~BMCR_ISOLATE; 2848964f241SSiva Durga Prasad Paladugu ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp); 2858964f241SSiva Durga Prasad Paladugu if (ret) 2868964f241SSiva Durga Prasad Paladugu return 0; 2878964f241SSiva Durga Prasad Paladugu } 2888964f241SSiva Durga Prasad Paladugu } 2898964f241SSiva Durga Prasad Paladugu 29011af8d65STimur Tabi if (phy_startup(phydev)) { 29111af8d65STimur Tabi printf("axiemac: could not initialize PHY %s\n", 29211af8d65STimur Tabi phydev->dev->name); 29311af8d65STimur Tabi return 0; 29411af8d65STimur Tabi } 2956f9b9372SMichal Simek if (!phydev->link) { 2966f9b9372SMichal Simek printf("%s: No link.\n", phydev->dev->name); 2976f9b9372SMichal Simek return 0; 2986f9b9372SMichal Simek } 2994f1ec4c1SMichal Simek 3004f1ec4c1SMichal Simek switch (phydev->speed) { 3014f1ec4c1SMichal Simek case 1000: 3024f1ec4c1SMichal Simek speed = XAE_EMMC_LINKSPD_1000; 3034f1ec4c1SMichal Simek break; 3044f1ec4c1SMichal Simek case 100: 3054f1ec4c1SMichal Simek speed = XAE_EMMC_LINKSPD_100; 3064f1ec4c1SMichal Simek break; 3074f1ec4c1SMichal Simek case 10: 3084f1ec4c1SMichal Simek speed = XAE_EMMC_LINKSPD_10; 3094f1ec4c1SMichal Simek break; 3104f1ec4c1SMichal Simek default: 3114f1ec4c1SMichal Simek return 0; 3124f1ec4c1SMichal Simek } 3134f1ec4c1SMichal Simek 3144f1ec4c1SMichal Simek /* Setup the emac for the phy speed */ 3154f1ec4c1SMichal Simek emmc_reg = in_be32(®s->emmc); 3164f1ec4c1SMichal Simek emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK; 3174f1ec4c1SMichal Simek emmc_reg |= speed; 3184f1ec4c1SMichal Simek 3194f1ec4c1SMichal Simek /* Write new speed setting out to Axi Ethernet */ 3204f1ec4c1SMichal Simek out_be32(®s->emmc, emmc_reg); 3214f1ec4c1SMichal Simek 3224f1ec4c1SMichal Simek /* 3234f1ec4c1SMichal Simek * Setting the operating speed of the MAC needs a delay. There 3244f1ec4c1SMichal Simek * doesn't seem to be register to poll, so please consider this 3254f1ec4c1SMichal Simek * during your application design. 3264f1ec4c1SMichal Simek */ 3274f1ec4c1SMichal Simek udelay(1); 3284f1ec4c1SMichal Simek 3294f1ec4c1SMichal Simek return 1; 3304f1ec4c1SMichal Simek } 3314f1ec4c1SMichal Simek 3324f1ec4c1SMichal Simek /* STOP DMA transfers */ 333ad499e42SMichal Simek static void axiemac_stop(struct udevice *dev) 3344f1ec4c1SMichal Simek { 33575cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev); 3364f1ec4c1SMichal Simek u32 temp; 3374f1ec4c1SMichal Simek 3384f1ec4c1SMichal Simek /* Stop the hardware */ 3394f1ec4c1SMichal Simek temp = in_be32(&priv->dmatx->control); 3404f1ec4c1SMichal Simek temp &= ~XAXIDMA_CR_RUNSTOP_MASK; 3414f1ec4c1SMichal Simek out_be32(&priv->dmatx->control, temp); 3424f1ec4c1SMichal Simek 3434f1ec4c1SMichal Simek temp = in_be32(&priv->dmarx->control); 3444f1ec4c1SMichal Simek temp &= ~XAXIDMA_CR_RUNSTOP_MASK; 3454f1ec4c1SMichal Simek out_be32(&priv->dmarx->control, temp); 3464f1ec4c1SMichal Simek 3474f1ec4c1SMichal Simek debug("axiemac: Halted\n"); 3484f1ec4c1SMichal Simek } 3494f1ec4c1SMichal Simek 350f0985481SMichal Simek static int axi_ethernet_init(struct axidma_priv *priv) 3514f1ec4c1SMichal Simek { 352f0985481SMichal Simek struct axi_regs *regs = priv->iobase; 3534f1ec4c1SMichal Simek u32 timeout = 200; 3544f1ec4c1SMichal Simek 3554f1ec4c1SMichal Simek /* 3564f1ec4c1SMichal Simek * Check the status of the MgtRdy bit in the interrupt status 3574f1ec4c1SMichal Simek * registers. This must be done to allow the MGT clock to become stable 3584f1ec4c1SMichal Simek * for the Sgmii and 1000BaseX PHY interfaces. No other register reads 3594f1ec4c1SMichal Simek * will be valid until this bit is valid. 3604f1ec4c1SMichal Simek * The bit is always a 1 for all other PHY interfaces. 3614f1ec4c1SMichal Simek */ 3624f1ec4c1SMichal Simek while (timeout && (!(in_be32(®s->is) & XAE_INT_MGTRDY_MASK))) { 3634f1ec4c1SMichal Simek timeout--; 3644f1ec4c1SMichal Simek udelay(1); 3654f1ec4c1SMichal Simek } 3664f1ec4c1SMichal Simek if (!timeout) { 3674f1ec4c1SMichal Simek printf("%s: Timeout\n", __func__); 3684f1ec4c1SMichal Simek return 1; 3694f1ec4c1SMichal Simek } 3704f1ec4c1SMichal Simek 3714f1ec4c1SMichal Simek /* Stop the device and reset HW */ 3724f1ec4c1SMichal Simek /* Disable interrupts */ 3734f1ec4c1SMichal Simek out_be32(®s->ie, 0); 3744f1ec4c1SMichal Simek 3754f1ec4c1SMichal Simek /* Disable the receiver */ 3764f1ec4c1SMichal Simek out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK); 3774f1ec4c1SMichal Simek 3784f1ec4c1SMichal Simek /* 3794f1ec4c1SMichal Simek * Stopping the receiver in mid-packet causes a dropped packet 3804f1ec4c1SMichal Simek * indication from HW. Clear it. 3814f1ec4c1SMichal Simek */ 3824f1ec4c1SMichal Simek /* Set the interrupt status register to clear the interrupt */ 3834f1ec4c1SMichal Simek out_be32(®s->is, XAE_INT_RXRJECT_MASK); 3844f1ec4c1SMichal Simek 3854f1ec4c1SMichal Simek /* Setup HW */ 3864f1ec4c1SMichal Simek /* Set default MDIO divisor */ 3874f1ec4c1SMichal Simek out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK); 3884f1ec4c1SMichal Simek 3894f1ec4c1SMichal Simek debug("axiemac: InitHw done\n"); 3904f1ec4c1SMichal Simek return 0; 3914f1ec4c1SMichal Simek } 3924f1ec4c1SMichal Simek 393ad499e42SMichal Simek static int axiemac_write_hwaddr(struct udevice *dev) 3944f1ec4c1SMichal Simek { 39575cc93faSMichal Simek struct eth_pdata *pdata = dev_get_platdata(dev); 39675cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev); 39775cc93faSMichal Simek struct axi_regs *regs = priv->iobase; 3984f1ec4c1SMichal Simek 3994f1ec4c1SMichal Simek /* Set the MAC address */ 40075cc93faSMichal Simek int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) | 40175cc93faSMichal Simek (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0])); 4024f1ec4c1SMichal Simek out_be32(®s->uaw0, val); 4034f1ec4c1SMichal Simek 40475cc93faSMichal Simek val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4]; 4054f1ec4c1SMichal Simek val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK; 4064f1ec4c1SMichal Simek out_be32(®s->uaw1, val); 4074f1ec4c1SMichal Simek return 0; 4084f1ec4c1SMichal Simek } 4094f1ec4c1SMichal Simek 4104f1ec4c1SMichal Simek /* Reset DMA engine */ 411f0985481SMichal Simek static void axi_dma_init(struct axidma_priv *priv) 4124f1ec4c1SMichal Simek { 4134f1ec4c1SMichal Simek u32 timeout = 500; 4144f1ec4c1SMichal Simek 4154f1ec4c1SMichal Simek /* Reset the engine so the hardware starts from a known state */ 4164f1ec4c1SMichal Simek out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK); 4174f1ec4c1SMichal Simek out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK); 4184f1ec4c1SMichal Simek 4194f1ec4c1SMichal Simek /* At the initialization time, hardware should finish reset quickly */ 4204f1ec4c1SMichal Simek while (timeout--) { 4214f1ec4c1SMichal Simek /* Check transmit/receive channel */ 4224f1ec4c1SMichal Simek /* Reset is done when the reset bit is low */ 4233e3f8ba2SMichal Simek if (!((in_be32(&priv->dmatx->control) | 4244f1ec4c1SMichal Simek in_be32(&priv->dmarx->control)) 4253e3f8ba2SMichal Simek & XAXIDMA_CR_RESET_MASK)) { 4264f1ec4c1SMichal Simek break; 4274f1ec4c1SMichal Simek } 4284f1ec4c1SMichal Simek } 4294f1ec4c1SMichal Simek if (!timeout) 4304f1ec4c1SMichal Simek printf("%s: Timeout\n", __func__); 4314f1ec4c1SMichal Simek } 4324f1ec4c1SMichal Simek 433ad499e42SMichal Simek static int axiemac_start(struct udevice *dev) 4344f1ec4c1SMichal Simek { 43575cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev); 43675cc93faSMichal Simek struct axi_regs *regs = priv->iobase; 4374f1ec4c1SMichal Simek u32 temp; 4384f1ec4c1SMichal Simek 4394f1ec4c1SMichal Simek debug("axiemac: Init started\n"); 4404f1ec4c1SMichal Simek /* 4414f1ec4c1SMichal Simek * Initialize AXIDMA engine. AXIDMA engine must be initialized before 4424f1ec4c1SMichal Simek * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is 4434f1ec4c1SMichal Simek * reset, and since AXIDMA reset line is connected to AxiEthernet, this 4444f1ec4c1SMichal Simek * would ensure a reset of AxiEthernet. 4454f1ec4c1SMichal Simek */ 446f0985481SMichal Simek axi_dma_init(priv); 4474f1ec4c1SMichal Simek 4484f1ec4c1SMichal Simek /* Initialize AxiEthernet hardware. */ 449f0985481SMichal Simek if (axi_ethernet_init(priv)) 4504f1ec4c1SMichal Simek return -1; 4514f1ec4c1SMichal Simek 4524f1ec4c1SMichal Simek /* Disable all RX interrupts before RxBD space setup */ 4534f1ec4c1SMichal Simek temp = in_be32(&priv->dmarx->control); 4544f1ec4c1SMichal Simek temp &= ~XAXIDMA_IRQ_ALL_MASK; 4554f1ec4c1SMichal Simek out_be32(&priv->dmarx->control, temp); 4564f1ec4c1SMichal Simek 4574f1ec4c1SMichal Simek /* Start DMA RX channel. Now it's ready to receive data.*/ 4584f1ec4c1SMichal Simek out_be32(&priv->dmarx->current, (u32)&rx_bd); 4594f1ec4c1SMichal Simek 4604f1ec4c1SMichal Simek /* Setup the BD. */ 4614f1ec4c1SMichal Simek memset(&rx_bd, 0, sizeof(rx_bd)); 4624f1ec4c1SMichal Simek rx_bd.next = (u32)&rx_bd; 4634f1ec4c1SMichal Simek rx_bd.phys = (u32)&rxframe; 4644f1ec4c1SMichal Simek rx_bd.cntrl = sizeof(rxframe); 4654f1ec4c1SMichal Simek /* Flush the last BD so DMA core could see the updates */ 4664f1ec4c1SMichal Simek flush_cache((u32)&rx_bd, sizeof(rx_bd)); 4674f1ec4c1SMichal Simek 4684f1ec4c1SMichal Simek /* It is necessary to flush rxframe because if you don't do it 4694f1ec4c1SMichal Simek * then cache can contain uninitialized data */ 4704f1ec4c1SMichal Simek flush_cache((u32)&rxframe, sizeof(rxframe)); 4714f1ec4c1SMichal Simek 4724f1ec4c1SMichal Simek /* Start the hardware */ 4734f1ec4c1SMichal Simek temp = in_be32(&priv->dmarx->control); 4744f1ec4c1SMichal Simek temp |= XAXIDMA_CR_RUNSTOP_MASK; 4754f1ec4c1SMichal Simek out_be32(&priv->dmarx->control, temp); 4764f1ec4c1SMichal Simek 4774f1ec4c1SMichal Simek /* Rx BD is ready - start */ 4784f1ec4c1SMichal Simek out_be32(&priv->dmarx->tail, (u32)&rx_bd); 4794f1ec4c1SMichal Simek 4804f1ec4c1SMichal Simek /* Enable TX */ 4814f1ec4c1SMichal Simek out_be32(®s->tc, XAE_TC_TX_MASK); 4824f1ec4c1SMichal Simek /* Enable RX */ 4834f1ec4c1SMichal Simek out_be32(®s->rcw1, XAE_RCW1_RX_MASK); 4844f1ec4c1SMichal Simek 4854f1ec4c1SMichal Simek /* PHY setup */ 4864f1ec4c1SMichal Simek if (!setup_phy(dev)) { 487ad499e42SMichal Simek axiemac_stop(dev); 4884f1ec4c1SMichal Simek return -1; 4894f1ec4c1SMichal Simek } 4904f1ec4c1SMichal Simek 4914f1ec4c1SMichal Simek debug("axiemac: Init complete\n"); 4924f1ec4c1SMichal Simek return 0; 4934f1ec4c1SMichal Simek } 4944f1ec4c1SMichal Simek 49575cc93faSMichal Simek static int axiemac_send(struct udevice *dev, void *ptr, int len) 4964f1ec4c1SMichal Simek { 49775cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev); 4984f1ec4c1SMichal Simek u32 timeout; 4994f1ec4c1SMichal Simek 5004f1ec4c1SMichal Simek if (len > PKTSIZE_ALIGN) 5014f1ec4c1SMichal Simek len = PKTSIZE_ALIGN; 5024f1ec4c1SMichal Simek 5034f1ec4c1SMichal Simek /* Flush packet to main memory to be trasfered by DMA */ 5044f1ec4c1SMichal Simek flush_cache((u32)ptr, len); 5054f1ec4c1SMichal Simek 5064f1ec4c1SMichal Simek /* Setup Tx BD */ 5074f1ec4c1SMichal Simek memset(&tx_bd, 0, sizeof(tx_bd)); 5084f1ec4c1SMichal Simek /* At the end of the ring, link the last BD back to the top */ 5094f1ec4c1SMichal Simek tx_bd.next = (u32)&tx_bd; 5104f1ec4c1SMichal Simek tx_bd.phys = (u32)ptr; 5114f1ec4c1SMichal Simek /* Save len */ 5124f1ec4c1SMichal Simek tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK | 5134f1ec4c1SMichal Simek XAXIDMA_BD_CTRL_TXEOF_MASK; 5144f1ec4c1SMichal Simek 5154f1ec4c1SMichal Simek /* Flush the last BD so DMA core could see the updates */ 5164f1ec4c1SMichal Simek flush_cache((u32)&tx_bd, sizeof(tx_bd)); 5174f1ec4c1SMichal Simek 5184f1ec4c1SMichal Simek if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) { 5194f1ec4c1SMichal Simek u32 temp; 5204f1ec4c1SMichal Simek out_be32(&priv->dmatx->current, (u32)&tx_bd); 5214f1ec4c1SMichal Simek /* Start the hardware */ 5224f1ec4c1SMichal Simek temp = in_be32(&priv->dmatx->control); 5234f1ec4c1SMichal Simek temp |= XAXIDMA_CR_RUNSTOP_MASK; 5244f1ec4c1SMichal Simek out_be32(&priv->dmatx->control, temp); 5254f1ec4c1SMichal Simek } 5264f1ec4c1SMichal Simek 5274f1ec4c1SMichal Simek /* Start transfer */ 5284f1ec4c1SMichal Simek out_be32(&priv->dmatx->tail, (u32)&tx_bd); 5294f1ec4c1SMichal Simek 5304f1ec4c1SMichal Simek /* Wait for transmission to complete */ 5314f1ec4c1SMichal Simek debug("axiemac: Waiting for tx to be done\n"); 5324f1ec4c1SMichal Simek timeout = 200; 5333e3f8ba2SMichal Simek while (timeout && (!(in_be32(&priv->dmatx->status) & 5343e3f8ba2SMichal Simek (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) { 5354f1ec4c1SMichal Simek timeout--; 5364f1ec4c1SMichal Simek udelay(1); 5374f1ec4c1SMichal Simek } 5384f1ec4c1SMichal Simek if (!timeout) { 5394f1ec4c1SMichal Simek printf("%s: Timeout\n", __func__); 5404f1ec4c1SMichal Simek return 1; 5414f1ec4c1SMichal Simek } 5424f1ec4c1SMichal Simek 5434f1ec4c1SMichal Simek debug("axiemac: Sending complete\n"); 5444f1ec4c1SMichal Simek return 0; 5454f1ec4c1SMichal Simek } 5464f1ec4c1SMichal Simek 547f0985481SMichal Simek static int isrxready(struct axidma_priv *priv) 5484f1ec4c1SMichal Simek { 5494f1ec4c1SMichal Simek u32 status; 5504f1ec4c1SMichal Simek 5514f1ec4c1SMichal Simek /* Read pending interrupts */ 5524f1ec4c1SMichal Simek status = in_be32(&priv->dmarx->status); 5534f1ec4c1SMichal Simek 5544f1ec4c1SMichal Simek /* Acknowledge pending interrupts */ 5554f1ec4c1SMichal Simek out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK); 5564f1ec4c1SMichal Simek 5574f1ec4c1SMichal Simek /* 5584f1ec4c1SMichal Simek * If Reception done interrupt is asserted, call RX call back function 5594f1ec4c1SMichal Simek * to handle the processed BDs and then raise the according flag. 5604f1ec4c1SMichal Simek */ 5614f1ec4c1SMichal Simek if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) 5624f1ec4c1SMichal Simek return 1; 5634f1ec4c1SMichal Simek 5644f1ec4c1SMichal Simek return 0; 5654f1ec4c1SMichal Simek } 5664f1ec4c1SMichal Simek 56775cc93faSMichal Simek static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) 5684f1ec4c1SMichal Simek { 5694f1ec4c1SMichal Simek u32 length; 57075cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev); 5714f1ec4c1SMichal Simek u32 temp; 5724f1ec4c1SMichal Simek 5734f1ec4c1SMichal Simek /* Wait for an incoming packet */ 574f0985481SMichal Simek if (!isrxready(priv)) 57575cc93faSMichal Simek return -1; 5764f1ec4c1SMichal Simek 5774f1ec4c1SMichal Simek debug("axiemac: RX data ready\n"); 5784f1ec4c1SMichal Simek 5794f1ec4c1SMichal Simek /* Disable IRQ for a moment till packet is handled */ 5804f1ec4c1SMichal Simek temp = in_be32(&priv->dmarx->control); 5814f1ec4c1SMichal Simek temp &= ~XAXIDMA_IRQ_ALL_MASK; 5824f1ec4c1SMichal Simek out_be32(&priv->dmarx->control, temp); 5834f1ec4c1SMichal Simek 5844f1ec4c1SMichal Simek length = rx_bd.app4 & 0xFFFF; /* max length mask */ 5854f1ec4c1SMichal Simek #ifdef DEBUG 5864f1ec4c1SMichal Simek print_buffer(&rxframe, &rxframe[0], 1, length, 16); 5874f1ec4c1SMichal Simek #endif 58897d2363dSMichal Simek 58997d2363dSMichal Simek *packetp = rxframe; 59097d2363dSMichal Simek return length; 59197d2363dSMichal Simek } 59297d2363dSMichal Simek 59397d2363dSMichal Simek static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length) 59497d2363dSMichal Simek { 59597d2363dSMichal Simek struct axidma_priv *priv = dev_get_priv(dev); 5964f1ec4c1SMichal Simek 5974f1ec4c1SMichal Simek #ifdef DEBUG 5984f1ec4c1SMichal Simek /* It is useful to clear buffer to be sure that it is consistent */ 5994f1ec4c1SMichal Simek memset(rxframe, 0, sizeof(rxframe)); 6004f1ec4c1SMichal Simek #endif 6014f1ec4c1SMichal Simek /* Setup RxBD */ 6024f1ec4c1SMichal Simek /* Clear the whole buffer and setup it again - all flags are cleared */ 6034f1ec4c1SMichal Simek memset(&rx_bd, 0, sizeof(rx_bd)); 6044f1ec4c1SMichal Simek rx_bd.next = (u32)&rx_bd; 6054f1ec4c1SMichal Simek rx_bd.phys = (u32)&rxframe; 6064f1ec4c1SMichal Simek rx_bd.cntrl = sizeof(rxframe); 6074f1ec4c1SMichal Simek 6084f1ec4c1SMichal Simek /* Write bd to HW */ 6094f1ec4c1SMichal Simek flush_cache((u32)&rx_bd, sizeof(rx_bd)); 6104f1ec4c1SMichal Simek 6114f1ec4c1SMichal Simek /* It is necessary to flush rxframe because if you don't do it 6124f1ec4c1SMichal Simek * then cache will contain previous packet */ 6134f1ec4c1SMichal Simek flush_cache((u32)&rxframe, sizeof(rxframe)); 6144f1ec4c1SMichal Simek 6154f1ec4c1SMichal Simek /* Rx BD is ready - start again */ 6164f1ec4c1SMichal Simek out_be32(&priv->dmarx->tail, (u32)&rx_bd); 6174f1ec4c1SMichal Simek 6184f1ec4c1SMichal Simek debug("axiemac: RX completed, framelength = %d\n", length); 6194f1ec4c1SMichal Simek 6204f1ec4c1SMichal Simek return 0; 6214f1ec4c1SMichal Simek } 6224f1ec4c1SMichal Simek 62375cc93faSMichal Simek static int axiemac_miiphy_read(struct mii_dev *bus, int addr, 62475cc93faSMichal Simek int devad, int reg) 6254f1ec4c1SMichal Simek { 62675cc93faSMichal Simek int ret; 62775cc93faSMichal Simek u16 value; 6284f1ec4c1SMichal Simek 62975cc93faSMichal Simek ret = phyread(bus->priv, addr, reg, &value); 63075cc93faSMichal Simek debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, 63175cc93faSMichal Simek value, ret); 63275cc93faSMichal Simek return value; 6334f1ec4c1SMichal Simek } 6344f1ec4c1SMichal Simek 63575cc93faSMichal Simek static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad, 63675cc93faSMichal Simek int reg, u16 value) 63775cc93faSMichal Simek { 63875cc93faSMichal Simek debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); 63975cc93faSMichal Simek return phywrite(bus->priv, addr, reg, value); 64075cc93faSMichal Simek } 6414f1ec4c1SMichal Simek 64275cc93faSMichal Simek static int axi_emac_probe(struct udevice *dev) 64375cc93faSMichal Simek { 64475cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev); 64575cc93faSMichal Simek int ret; 64675cc93faSMichal Simek 64775cc93faSMichal Simek priv->bus = mdio_alloc(); 64875cc93faSMichal Simek priv->bus->read = axiemac_miiphy_read; 64975cc93faSMichal Simek priv->bus->write = axiemac_miiphy_write; 65075cc93faSMichal Simek priv->bus->priv = priv; 65175cc93faSMichal Simek 6526516e3f2SMichal Simek ret = mdio_register_seq(priv->bus, dev->seq); 65375cc93faSMichal Simek if (ret) 65475cc93faSMichal Simek return ret; 65575cc93faSMichal Simek 6565d0449d4SMichal Simek axiemac_phy_init(dev); 6575d0449d4SMichal Simek 65875cc93faSMichal Simek return 0; 65975cc93faSMichal Simek } 66075cc93faSMichal Simek 66175cc93faSMichal Simek static int axi_emac_remove(struct udevice *dev) 66275cc93faSMichal Simek { 66375cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev); 66475cc93faSMichal Simek 66575cc93faSMichal Simek free(priv->phydev); 66675cc93faSMichal Simek mdio_unregister(priv->bus); 66775cc93faSMichal Simek mdio_free(priv->bus); 66875cc93faSMichal Simek 66975cc93faSMichal Simek return 0; 67075cc93faSMichal Simek } 67175cc93faSMichal Simek 67275cc93faSMichal Simek static const struct eth_ops axi_emac_ops = { 673ad499e42SMichal Simek .start = axiemac_start, 67475cc93faSMichal Simek .send = axiemac_send, 67575cc93faSMichal Simek .recv = axiemac_recv, 67697d2363dSMichal Simek .free_pkt = axiemac_free_pkt, 677ad499e42SMichal Simek .stop = axiemac_stop, 678ad499e42SMichal Simek .write_hwaddr = axiemac_write_hwaddr, 67975cc93faSMichal Simek }; 68075cc93faSMichal Simek 68175cc93faSMichal Simek static int axi_emac_ofdata_to_platdata(struct udevice *dev) 68275cc93faSMichal Simek { 68375cc93faSMichal Simek struct eth_pdata *pdata = dev_get_platdata(dev); 68475cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev); 685e160f7d4SSimon Glass int node = dev_of_offset(dev); 68675cc93faSMichal Simek int offset = 0; 68775cc93faSMichal Simek const char *phy_mode; 68875cc93faSMichal Simek 689*a821c4afSSimon Glass pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); 69075cc93faSMichal Simek priv->iobase = (struct axi_regs *)pdata->iobase; 69175cc93faSMichal Simek 692e160f7d4SSimon Glass offset = fdtdec_lookup_phandle(gd->fdt_blob, node, 69375cc93faSMichal Simek "axistream-connected"); 69475cc93faSMichal Simek if (offset <= 0) { 69575cc93faSMichal Simek printf("%s: axistream is not found\n", __func__); 69675cc93faSMichal Simek return -EINVAL; 69775cc93faSMichal Simek } 69875cc93faSMichal Simek priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob, 69975cc93faSMichal Simek offset, "reg", 0); 70075cc93faSMichal Simek if (!priv->dmatx) { 70175cc93faSMichal Simek printf("%s: axi_dma register space not found\n", __func__); 70275cc93faSMichal Simek return -EINVAL; 70375cc93faSMichal Simek } 7044f1ec4c1SMichal Simek /* RX channel offset is 0x30 */ 70575cc93faSMichal Simek priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30); 7064f1ec4c1SMichal Simek 7074f1ec4c1SMichal Simek priv->phyaddr = -1; 7084f1ec4c1SMichal Simek 709e160f7d4SSimon Glass offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); 71075cc93faSMichal Simek if (offset > 0) 71175cc93faSMichal Simek priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); 7124f1ec4c1SMichal Simek 713e160f7d4SSimon Glass phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); 71475cc93faSMichal Simek if (phy_mode) 71575cc93faSMichal Simek pdata->phy_interface = phy_get_interface_by_name(phy_mode); 71675cc93faSMichal Simek if (pdata->phy_interface == -1) { 717ceb04e1aSMichal Simek printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 71875cc93faSMichal Simek return -EINVAL; 7194f1ec4c1SMichal Simek } 72075cc93faSMichal Simek priv->interface = pdata->phy_interface; 72175cc93faSMichal Simek 72275cc93faSMichal Simek printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, 72375cc93faSMichal Simek priv->phyaddr, phy_string_for_interface(priv->interface)); 72475cc93faSMichal Simek 72575cc93faSMichal Simek return 0; 72675cc93faSMichal Simek } 72775cc93faSMichal Simek 72875cc93faSMichal Simek static const struct udevice_id axi_emac_ids[] = { 72975cc93faSMichal Simek { .compatible = "xlnx,axi-ethernet-1.00.a" }, 73075cc93faSMichal Simek { } 73175cc93faSMichal Simek }; 73275cc93faSMichal Simek 73375cc93faSMichal Simek U_BOOT_DRIVER(axi_emac) = { 73475cc93faSMichal Simek .name = "axi_emac", 73575cc93faSMichal Simek .id = UCLASS_ETH, 73675cc93faSMichal Simek .of_match = axi_emac_ids, 73775cc93faSMichal Simek .ofdata_to_platdata = axi_emac_ofdata_to_platdata, 73875cc93faSMichal Simek .probe = axi_emac_probe, 73975cc93faSMichal Simek .remove = axi_emac_remove, 74075cc93faSMichal Simek .ops = &axi_emac_ops, 74175cc93faSMichal Simek .priv_auto_alloc_size = sizeof(struct axidma_priv), 74275cc93faSMichal Simek .platdata_auto_alloc_size = sizeof(struct eth_pdata), 74375cc93faSMichal Simek }; 744