14f1ec4c1SMichal Simek /* 24f1ec4c1SMichal Simek * Copyright (C) 2011 Michal Simek <monstr@monstr.eu> 34f1ec4c1SMichal Simek * Copyright (C) 2011 PetaLogix 44f1ec4c1SMichal Simek * Copyright (C) 2010 Xilinx, Inc. All rights reserved. 54f1ec4c1SMichal Simek * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 74f1ec4c1SMichal Simek */ 84f1ec4c1SMichal Simek 94f1ec4c1SMichal Simek #include <config.h> 104f1ec4c1SMichal Simek #include <common.h> 114f1ec4c1SMichal Simek #include <net.h> 124f1ec4c1SMichal Simek #include <malloc.h> 134f1ec4c1SMichal Simek #include <asm/io.h> 144f1ec4c1SMichal Simek #include <phy.h> 154f1ec4c1SMichal Simek #include <miiphy.h> 164f1ec4c1SMichal Simek 174f1ec4c1SMichal Simek #if !defined(CONFIG_PHYLIB) 184f1ec4c1SMichal Simek # error AXI_ETHERNET requires PHYLIB 194f1ec4c1SMichal Simek #endif 204f1ec4c1SMichal Simek 214f1ec4c1SMichal Simek /* Link setup */ 224f1ec4c1SMichal Simek #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ 234f1ec4c1SMichal Simek #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ 244f1ec4c1SMichal Simek #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ 254f1ec4c1SMichal Simek #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ 264f1ec4c1SMichal Simek 274f1ec4c1SMichal Simek /* Interrupt Status/Enable/Mask Registers bit definitions */ 284f1ec4c1SMichal Simek #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ 294f1ec4c1SMichal Simek #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ 304f1ec4c1SMichal Simek 314f1ec4c1SMichal Simek /* Receive Configuration Word 1 (RCW1) Register bit definitions */ 324f1ec4c1SMichal Simek #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ 334f1ec4c1SMichal Simek 344f1ec4c1SMichal Simek /* Transmitter Configuration (TC) Register bit definitions */ 354f1ec4c1SMichal Simek #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ 364f1ec4c1SMichal Simek 374f1ec4c1SMichal Simek #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF 384f1ec4c1SMichal Simek 394f1ec4c1SMichal Simek /* MDIO Management Configuration (MC) Register bit definitions */ 404f1ec4c1SMichal Simek #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/ 414f1ec4c1SMichal Simek 424f1ec4c1SMichal Simek /* MDIO Management Control Register (MCR) Register bit definitions */ 434f1ec4c1SMichal Simek #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ 444f1ec4c1SMichal Simek #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ 454f1ec4c1SMichal Simek #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ 464f1ec4c1SMichal Simek #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ 474f1ec4c1SMichal Simek #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ 484f1ec4c1SMichal Simek #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ 494f1ec4c1SMichal Simek #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ 504f1ec4c1SMichal Simek #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ 514f1ec4c1SMichal Simek 524f1ec4c1SMichal Simek #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */ 534f1ec4c1SMichal Simek 544f1ec4c1SMichal Simek /* DMA macros */ 554f1ec4c1SMichal Simek /* Bitmasks of XAXIDMA_CR_OFFSET register */ 564f1ec4c1SMichal Simek #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ 574f1ec4c1SMichal Simek #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ 584f1ec4c1SMichal Simek 594f1ec4c1SMichal Simek /* Bitmasks of XAXIDMA_SR_OFFSET register */ 604f1ec4c1SMichal Simek #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */ 614f1ec4c1SMichal Simek 624f1ec4c1SMichal Simek /* Bitmask for interrupts */ 634f1ec4c1SMichal Simek #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ 644f1ec4c1SMichal Simek #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ 654f1ec4c1SMichal Simek #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ 664f1ec4c1SMichal Simek 674f1ec4c1SMichal Simek /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */ 684f1ec4c1SMichal Simek #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ 694f1ec4c1SMichal Simek #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ 704f1ec4c1SMichal Simek 714f1ec4c1SMichal Simek #define DMAALIGN 128 724f1ec4c1SMichal Simek 734f1ec4c1SMichal Simek static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); 744f1ec4c1SMichal Simek 754f1ec4c1SMichal Simek /* Reflect dma offsets */ 764f1ec4c1SMichal Simek struct axidma_reg { 774f1ec4c1SMichal Simek u32 control; /* DMACR */ 784f1ec4c1SMichal Simek u32 status; /* DMASR */ 794f1ec4c1SMichal Simek u32 current; /* CURDESC */ 804f1ec4c1SMichal Simek u32 reserved; 814f1ec4c1SMichal Simek u32 tail; /* TAILDESC */ 824f1ec4c1SMichal Simek }; 834f1ec4c1SMichal Simek 844f1ec4c1SMichal Simek /* Private driver structures */ 854f1ec4c1SMichal Simek struct axidma_priv { 864f1ec4c1SMichal Simek struct axidma_reg *dmatx; 874f1ec4c1SMichal Simek struct axidma_reg *dmarx; 884f1ec4c1SMichal Simek int phyaddr; 894f1ec4c1SMichal Simek 904f1ec4c1SMichal Simek struct phy_device *phydev; 914f1ec4c1SMichal Simek struct mii_dev *bus; 924f1ec4c1SMichal Simek }; 934f1ec4c1SMichal Simek 944f1ec4c1SMichal Simek /* BD descriptors */ 954f1ec4c1SMichal Simek struct axidma_bd { 964f1ec4c1SMichal Simek u32 next; /* Next descriptor pointer */ 974f1ec4c1SMichal Simek u32 reserved1; 984f1ec4c1SMichal Simek u32 phys; /* Buffer address */ 994f1ec4c1SMichal Simek u32 reserved2; 1004f1ec4c1SMichal Simek u32 reserved3; 1014f1ec4c1SMichal Simek u32 reserved4; 1024f1ec4c1SMichal Simek u32 cntrl; /* Control */ 1034f1ec4c1SMichal Simek u32 status; /* Status */ 1044f1ec4c1SMichal Simek u32 app0; 1054f1ec4c1SMichal Simek u32 app1; /* TX start << 16 | insert */ 1064f1ec4c1SMichal Simek u32 app2; /* TX csum seed */ 1074f1ec4c1SMichal Simek u32 app3; 1084f1ec4c1SMichal Simek u32 app4; 1094f1ec4c1SMichal Simek u32 sw_id_offset; 1104f1ec4c1SMichal Simek u32 reserved5; 1114f1ec4c1SMichal Simek u32 reserved6; 1124f1ec4c1SMichal Simek }; 1134f1ec4c1SMichal Simek 1144f1ec4c1SMichal Simek /* Static BDs - driver uses only one BD */ 1154f1ec4c1SMichal Simek static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN))); 1164f1ec4c1SMichal Simek static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN))); 1174f1ec4c1SMichal Simek 1184f1ec4c1SMichal Simek struct axi_regs { 1194f1ec4c1SMichal Simek u32 reserved[3]; 1204f1ec4c1SMichal Simek u32 is; /* 0xC: Interrupt status */ 1214f1ec4c1SMichal Simek u32 reserved2; 1224f1ec4c1SMichal Simek u32 ie; /* 0x14: Interrupt enable */ 1234f1ec4c1SMichal Simek u32 reserved3[251]; 1244f1ec4c1SMichal Simek u32 rcw1; /* 0x404: Rx Configuration Word 1 */ 1254f1ec4c1SMichal Simek u32 tc; /* 0x408: Tx Configuration */ 1264f1ec4c1SMichal Simek u32 reserved4; 1274f1ec4c1SMichal Simek u32 emmc; /* 0x410: EMAC mode configuration */ 1284f1ec4c1SMichal Simek u32 reserved5[59]; 1294f1ec4c1SMichal Simek u32 mdio_mc; /* 0x500: MII Management Config */ 1304f1ec4c1SMichal Simek u32 mdio_mcr; /* 0x504: MII Management Control */ 1314f1ec4c1SMichal Simek u32 mdio_mwd; /* 0x508: MII Management Write Data */ 1324f1ec4c1SMichal Simek u32 mdio_mrd; /* 0x50C: MII Management Read Data */ 1334f1ec4c1SMichal Simek u32 reserved6[124]; 1344f1ec4c1SMichal Simek u32 uaw0; /* 0x700: Unicast address word 0 */ 1354f1ec4c1SMichal Simek u32 uaw1; /* 0x704: Unicast address word 1 */ 1364f1ec4c1SMichal Simek }; 1374f1ec4c1SMichal Simek 1384f1ec4c1SMichal Simek /* Use MII register 1 (MII status register) to detect PHY */ 1394f1ec4c1SMichal Simek #define PHY_DETECT_REG 1 1404f1ec4c1SMichal Simek 1414f1ec4c1SMichal Simek /* 1424f1ec4c1SMichal Simek * Mask used to verify certain PHY features (or register contents) 1434f1ec4c1SMichal Simek * in the register above: 1444f1ec4c1SMichal Simek * 0x1000: 10Mbps full duplex support 1454f1ec4c1SMichal Simek * 0x0800: 10Mbps half duplex support 1464f1ec4c1SMichal Simek * 0x0008: Auto-negotiation support 1474f1ec4c1SMichal Simek */ 1484f1ec4c1SMichal Simek #define PHY_DETECT_MASK 0x1808 1494f1ec4c1SMichal Simek 1504f1ec4c1SMichal Simek static inline int mdio_wait(struct eth_device *dev) 1514f1ec4c1SMichal Simek { 1524f1ec4c1SMichal Simek struct axi_regs *regs = (struct axi_regs *)dev->iobase; 1534f1ec4c1SMichal Simek u32 timeout = 200; 1544f1ec4c1SMichal Simek 1554f1ec4c1SMichal Simek /* Wait till MDIO interface is ready to accept a new transaction. */ 1564f1ec4c1SMichal Simek while (timeout && (!(in_be32(®s->mdio_mcr) 1574f1ec4c1SMichal Simek & XAE_MDIO_MCR_READY_MASK))) { 1584f1ec4c1SMichal Simek timeout--; 1594f1ec4c1SMichal Simek udelay(1); 1604f1ec4c1SMichal Simek } 1614f1ec4c1SMichal Simek if (!timeout) { 1624f1ec4c1SMichal Simek printf("%s: Timeout\n", __func__); 1634f1ec4c1SMichal Simek return 1; 1644f1ec4c1SMichal Simek } 1654f1ec4c1SMichal Simek return 0; 1664f1ec4c1SMichal Simek } 1674f1ec4c1SMichal Simek 1684f1ec4c1SMichal Simek static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, 1694f1ec4c1SMichal Simek u16 *val) 1704f1ec4c1SMichal Simek { 1714f1ec4c1SMichal Simek struct axi_regs *regs = (struct axi_regs *)dev->iobase; 1724f1ec4c1SMichal Simek u32 mdioctrlreg = 0; 1734f1ec4c1SMichal Simek 1744f1ec4c1SMichal Simek if (mdio_wait(dev)) 1754f1ec4c1SMichal Simek return 1; 1764f1ec4c1SMichal Simek 1774f1ec4c1SMichal Simek mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & 1784f1ec4c1SMichal Simek XAE_MDIO_MCR_PHYAD_MASK) | 1794f1ec4c1SMichal Simek ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) 1804f1ec4c1SMichal Simek & XAE_MDIO_MCR_REGAD_MASK) | 1814f1ec4c1SMichal Simek XAE_MDIO_MCR_INITIATE_MASK | 1824f1ec4c1SMichal Simek XAE_MDIO_MCR_OP_READ_MASK; 1834f1ec4c1SMichal Simek 1844f1ec4c1SMichal Simek out_be32(®s->mdio_mcr, mdioctrlreg); 1854f1ec4c1SMichal Simek 1864f1ec4c1SMichal Simek if (mdio_wait(dev)) 1874f1ec4c1SMichal Simek return 1; 1884f1ec4c1SMichal Simek 1894f1ec4c1SMichal Simek /* Read data */ 1904f1ec4c1SMichal Simek *val = in_be32(®s->mdio_mrd); 1914f1ec4c1SMichal Simek return 0; 1924f1ec4c1SMichal Simek } 1934f1ec4c1SMichal Simek 1944f1ec4c1SMichal Simek static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, 1954f1ec4c1SMichal Simek u32 data) 1964f1ec4c1SMichal Simek { 1974f1ec4c1SMichal Simek struct axi_regs *regs = (struct axi_regs *)dev->iobase; 1984f1ec4c1SMichal Simek u32 mdioctrlreg = 0; 1994f1ec4c1SMichal Simek 2004f1ec4c1SMichal Simek if (mdio_wait(dev)) 2014f1ec4c1SMichal Simek return 1; 2024f1ec4c1SMichal Simek 2034f1ec4c1SMichal Simek mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & 2044f1ec4c1SMichal Simek XAE_MDIO_MCR_PHYAD_MASK) | 2054f1ec4c1SMichal Simek ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) 2064f1ec4c1SMichal Simek & XAE_MDIO_MCR_REGAD_MASK) | 2074f1ec4c1SMichal Simek XAE_MDIO_MCR_INITIATE_MASK | 2084f1ec4c1SMichal Simek XAE_MDIO_MCR_OP_WRITE_MASK; 2094f1ec4c1SMichal Simek 2104f1ec4c1SMichal Simek /* Write data */ 2114f1ec4c1SMichal Simek out_be32(®s->mdio_mwd, data); 2124f1ec4c1SMichal Simek 2134f1ec4c1SMichal Simek out_be32(®s->mdio_mcr, mdioctrlreg); 2144f1ec4c1SMichal Simek 2154f1ec4c1SMichal Simek if (mdio_wait(dev)) 2164f1ec4c1SMichal Simek return 1; 2174f1ec4c1SMichal Simek 2184f1ec4c1SMichal Simek return 0; 2194f1ec4c1SMichal Simek } 2204f1ec4c1SMichal Simek 2214f1ec4c1SMichal Simek /* Setting axi emac and phy to proper setting */ 2224f1ec4c1SMichal Simek static int setup_phy(struct eth_device *dev) 2234f1ec4c1SMichal Simek { 2244f1ec4c1SMichal Simek u16 phyreg; 2254f1ec4c1SMichal Simek u32 i, speed, emmc_reg, ret; 2264f1ec4c1SMichal Simek struct axidma_priv *priv = dev->priv; 2274f1ec4c1SMichal Simek struct axi_regs *regs = (struct axi_regs *)dev->iobase; 2284f1ec4c1SMichal Simek struct phy_device *phydev; 2294f1ec4c1SMichal Simek 2304f1ec4c1SMichal Simek u32 supported = SUPPORTED_10baseT_Half | 2314f1ec4c1SMichal Simek SUPPORTED_10baseT_Full | 2324f1ec4c1SMichal Simek SUPPORTED_100baseT_Half | 2334f1ec4c1SMichal Simek SUPPORTED_100baseT_Full | 2344f1ec4c1SMichal Simek SUPPORTED_1000baseT_Half | 2354f1ec4c1SMichal Simek SUPPORTED_1000baseT_Full; 2364f1ec4c1SMichal Simek 2374f1ec4c1SMichal Simek if (priv->phyaddr == -1) { 2384f1ec4c1SMichal Simek /* Detect the PHY address */ 2394f1ec4c1SMichal Simek for (i = 31; i >= 0; i--) { 2404f1ec4c1SMichal Simek ret = phyread(dev, i, PHY_DETECT_REG, &phyreg); 2414f1ec4c1SMichal Simek if (!ret && (phyreg != 0xFFFF) && 2424f1ec4c1SMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 2434f1ec4c1SMichal Simek /* Found a valid PHY address */ 2444f1ec4c1SMichal Simek priv->phyaddr = i; 2454f1ec4c1SMichal Simek debug("axiemac: Found valid phy address, %x\n", 2464f1ec4c1SMichal Simek phyreg); 2474f1ec4c1SMichal Simek break; 2484f1ec4c1SMichal Simek } 2494f1ec4c1SMichal Simek } 2504f1ec4c1SMichal Simek } 2514f1ec4c1SMichal Simek 2524f1ec4c1SMichal Simek /* Interface - look at tsec */ 2534f1ec4c1SMichal Simek phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); 2544f1ec4c1SMichal Simek 2554f1ec4c1SMichal Simek phydev->supported &= supported; 2564f1ec4c1SMichal Simek phydev->advertising = phydev->supported; 2574f1ec4c1SMichal Simek priv->phydev = phydev; 2584f1ec4c1SMichal Simek phy_config(phydev); 25911af8d65STimur Tabi if (phy_startup(phydev)) { 26011af8d65STimur Tabi printf("axiemac: could not initialize PHY %s\n", 26111af8d65STimur Tabi phydev->dev->name); 26211af8d65STimur Tabi return 0; 26311af8d65STimur Tabi } 2644f1ec4c1SMichal Simek 2654f1ec4c1SMichal Simek switch (phydev->speed) { 2664f1ec4c1SMichal Simek case 1000: 2674f1ec4c1SMichal Simek speed = XAE_EMMC_LINKSPD_1000; 2684f1ec4c1SMichal Simek break; 2694f1ec4c1SMichal Simek case 100: 2704f1ec4c1SMichal Simek speed = XAE_EMMC_LINKSPD_100; 2714f1ec4c1SMichal Simek break; 2724f1ec4c1SMichal Simek case 10: 2734f1ec4c1SMichal Simek speed = XAE_EMMC_LINKSPD_10; 2744f1ec4c1SMichal Simek break; 2754f1ec4c1SMichal Simek default: 2764f1ec4c1SMichal Simek return 0; 2774f1ec4c1SMichal Simek } 2784f1ec4c1SMichal Simek 2794f1ec4c1SMichal Simek /* Setup the emac for the phy speed */ 2804f1ec4c1SMichal Simek emmc_reg = in_be32(®s->emmc); 2814f1ec4c1SMichal Simek emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK; 2824f1ec4c1SMichal Simek emmc_reg |= speed; 2834f1ec4c1SMichal Simek 2844f1ec4c1SMichal Simek /* Write new speed setting out to Axi Ethernet */ 2854f1ec4c1SMichal Simek out_be32(®s->emmc, emmc_reg); 2864f1ec4c1SMichal Simek 2874f1ec4c1SMichal Simek /* 2884f1ec4c1SMichal Simek * Setting the operating speed of the MAC needs a delay. There 2894f1ec4c1SMichal Simek * doesn't seem to be register to poll, so please consider this 2904f1ec4c1SMichal Simek * during your application design. 2914f1ec4c1SMichal Simek */ 2924f1ec4c1SMichal Simek udelay(1); 2934f1ec4c1SMichal Simek 2944f1ec4c1SMichal Simek return 1; 2954f1ec4c1SMichal Simek } 2964f1ec4c1SMichal Simek 2974f1ec4c1SMichal Simek /* STOP DMA transfers */ 2984f1ec4c1SMichal Simek static void axiemac_halt(struct eth_device *dev) 2994f1ec4c1SMichal Simek { 3004f1ec4c1SMichal Simek struct axidma_priv *priv = dev->priv; 3014f1ec4c1SMichal Simek u32 temp; 3024f1ec4c1SMichal Simek 3034f1ec4c1SMichal Simek /* Stop the hardware */ 3044f1ec4c1SMichal Simek temp = in_be32(&priv->dmatx->control); 3054f1ec4c1SMichal Simek temp &= ~XAXIDMA_CR_RUNSTOP_MASK; 3064f1ec4c1SMichal Simek out_be32(&priv->dmatx->control, temp); 3074f1ec4c1SMichal Simek 3084f1ec4c1SMichal Simek temp = in_be32(&priv->dmarx->control); 3094f1ec4c1SMichal Simek temp &= ~XAXIDMA_CR_RUNSTOP_MASK; 3104f1ec4c1SMichal Simek out_be32(&priv->dmarx->control, temp); 3114f1ec4c1SMichal Simek 3124f1ec4c1SMichal Simek debug("axiemac: Halted\n"); 3134f1ec4c1SMichal Simek } 3144f1ec4c1SMichal Simek 3154f1ec4c1SMichal Simek static int axi_ethernet_init(struct eth_device *dev) 3164f1ec4c1SMichal Simek { 3174f1ec4c1SMichal Simek struct axi_regs *regs = (struct axi_regs *)dev->iobase; 3184f1ec4c1SMichal Simek u32 timeout = 200; 3194f1ec4c1SMichal Simek 3204f1ec4c1SMichal Simek /* 3214f1ec4c1SMichal Simek * Check the status of the MgtRdy bit in the interrupt status 3224f1ec4c1SMichal Simek * registers. This must be done to allow the MGT clock to become stable 3234f1ec4c1SMichal Simek * for the Sgmii and 1000BaseX PHY interfaces. No other register reads 3244f1ec4c1SMichal Simek * will be valid until this bit is valid. 3254f1ec4c1SMichal Simek * The bit is always a 1 for all other PHY interfaces. 3264f1ec4c1SMichal Simek */ 3274f1ec4c1SMichal Simek while (timeout && (!(in_be32(®s->is) & XAE_INT_MGTRDY_MASK))) { 3284f1ec4c1SMichal Simek timeout--; 3294f1ec4c1SMichal Simek udelay(1); 3304f1ec4c1SMichal Simek } 3314f1ec4c1SMichal Simek if (!timeout) { 3324f1ec4c1SMichal Simek printf("%s: Timeout\n", __func__); 3334f1ec4c1SMichal Simek return 1; 3344f1ec4c1SMichal Simek } 3354f1ec4c1SMichal Simek 3364f1ec4c1SMichal Simek /* Stop the device and reset HW */ 3374f1ec4c1SMichal Simek /* Disable interrupts */ 3384f1ec4c1SMichal Simek out_be32(®s->ie, 0); 3394f1ec4c1SMichal Simek 3404f1ec4c1SMichal Simek /* Disable the receiver */ 3414f1ec4c1SMichal Simek out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK); 3424f1ec4c1SMichal Simek 3434f1ec4c1SMichal Simek /* 3444f1ec4c1SMichal Simek * Stopping the receiver in mid-packet causes a dropped packet 3454f1ec4c1SMichal Simek * indication from HW. Clear it. 3464f1ec4c1SMichal Simek */ 3474f1ec4c1SMichal Simek /* Set the interrupt status register to clear the interrupt */ 3484f1ec4c1SMichal Simek out_be32(®s->is, XAE_INT_RXRJECT_MASK); 3494f1ec4c1SMichal Simek 3504f1ec4c1SMichal Simek /* Setup HW */ 3514f1ec4c1SMichal Simek /* Set default MDIO divisor */ 3524f1ec4c1SMichal Simek out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK); 3534f1ec4c1SMichal Simek 3544f1ec4c1SMichal Simek debug("axiemac: InitHw done\n"); 3554f1ec4c1SMichal Simek return 0; 3564f1ec4c1SMichal Simek } 3574f1ec4c1SMichal Simek 3584f1ec4c1SMichal Simek static int axiemac_setup_mac(struct eth_device *dev) 3594f1ec4c1SMichal Simek { 3604f1ec4c1SMichal Simek struct axi_regs *regs = (struct axi_regs *)dev->iobase; 3614f1ec4c1SMichal Simek 3624f1ec4c1SMichal Simek /* Set the MAC address */ 3634f1ec4c1SMichal Simek int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) | 3644f1ec4c1SMichal Simek (dev->enetaddr[1] << 8) | (dev->enetaddr[0])); 3654f1ec4c1SMichal Simek out_be32(®s->uaw0, val); 3664f1ec4c1SMichal Simek 3674f1ec4c1SMichal Simek val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ; 3684f1ec4c1SMichal Simek val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK; 3694f1ec4c1SMichal Simek out_be32(®s->uaw1, val); 3704f1ec4c1SMichal Simek return 0; 3714f1ec4c1SMichal Simek } 3724f1ec4c1SMichal Simek 3734f1ec4c1SMichal Simek /* Reset DMA engine */ 3744f1ec4c1SMichal Simek static void axi_dma_init(struct eth_device *dev) 3754f1ec4c1SMichal Simek { 3764f1ec4c1SMichal Simek struct axidma_priv *priv = dev->priv; 3774f1ec4c1SMichal Simek u32 timeout = 500; 3784f1ec4c1SMichal Simek 3794f1ec4c1SMichal Simek /* Reset the engine so the hardware starts from a known state */ 3804f1ec4c1SMichal Simek out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK); 3814f1ec4c1SMichal Simek out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK); 3824f1ec4c1SMichal Simek 3834f1ec4c1SMichal Simek /* At the initialization time, hardware should finish reset quickly */ 3844f1ec4c1SMichal Simek while (timeout--) { 3854f1ec4c1SMichal Simek /* Check transmit/receive channel */ 3864f1ec4c1SMichal Simek /* Reset is done when the reset bit is low */ 3874f1ec4c1SMichal Simek if (!(in_be32(&priv->dmatx->control) | 3884f1ec4c1SMichal Simek in_be32(&priv->dmarx->control)) 3894f1ec4c1SMichal Simek & XAXIDMA_CR_RESET_MASK) { 3904f1ec4c1SMichal Simek break; 3914f1ec4c1SMichal Simek } 3924f1ec4c1SMichal Simek } 3934f1ec4c1SMichal Simek if (!timeout) 3944f1ec4c1SMichal Simek printf("%s: Timeout\n", __func__); 3954f1ec4c1SMichal Simek } 3964f1ec4c1SMichal Simek 3974f1ec4c1SMichal Simek static int axiemac_init(struct eth_device *dev, bd_t * bis) 3984f1ec4c1SMichal Simek { 3994f1ec4c1SMichal Simek struct axidma_priv *priv = dev->priv; 4004f1ec4c1SMichal Simek struct axi_regs *regs = (struct axi_regs *)dev->iobase; 4014f1ec4c1SMichal Simek u32 temp; 4024f1ec4c1SMichal Simek 4034f1ec4c1SMichal Simek debug("axiemac: Init started\n"); 4044f1ec4c1SMichal Simek /* 4054f1ec4c1SMichal Simek * Initialize AXIDMA engine. AXIDMA engine must be initialized before 4064f1ec4c1SMichal Simek * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is 4074f1ec4c1SMichal Simek * reset, and since AXIDMA reset line is connected to AxiEthernet, this 4084f1ec4c1SMichal Simek * would ensure a reset of AxiEthernet. 4094f1ec4c1SMichal Simek */ 4104f1ec4c1SMichal Simek axi_dma_init(dev); 4114f1ec4c1SMichal Simek 4124f1ec4c1SMichal Simek /* Initialize AxiEthernet hardware. */ 4134f1ec4c1SMichal Simek if (axi_ethernet_init(dev)) 4144f1ec4c1SMichal Simek return -1; 4154f1ec4c1SMichal Simek 4164f1ec4c1SMichal Simek /* Disable all RX interrupts before RxBD space setup */ 4174f1ec4c1SMichal Simek temp = in_be32(&priv->dmarx->control); 4184f1ec4c1SMichal Simek temp &= ~XAXIDMA_IRQ_ALL_MASK; 4194f1ec4c1SMichal Simek out_be32(&priv->dmarx->control, temp); 4204f1ec4c1SMichal Simek 4214f1ec4c1SMichal Simek /* Start DMA RX channel. Now it's ready to receive data.*/ 4224f1ec4c1SMichal Simek out_be32(&priv->dmarx->current, (u32)&rx_bd); 4234f1ec4c1SMichal Simek 4244f1ec4c1SMichal Simek /* Setup the BD. */ 4254f1ec4c1SMichal Simek memset(&rx_bd, 0, sizeof(rx_bd)); 4264f1ec4c1SMichal Simek rx_bd.next = (u32)&rx_bd; 4274f1ec4c1SMichal Simek rx_bd.phys = (u32)&rxframe; 4284f1ec4c1SMichal Simek rx_bd.cntrl = sizeof(rxframe); 4294f1ec4c1SMichal Simek /* Flush the last BD so DMA core could see the updates */ 4304f1ec4c1SMichal Simek flush_cache((u32)&rx_bd, sizeof(rx_bd)); 4314f1ec4c1SMichal Simek 4324f1ec4c1SMichal Simek /* It is necessary to flush rxframe because if you don't do it 4334f1ec4c1SMichal Simek * then cache can contain uninitialized data */ 4344f1ec4c1SMichal Simek flush_cache((u32)&rxframe, sizeof(rxframe)); 4354f1ec4c1SMichal Simek 4364f1ec4c1SMichal Simek /* Start the hardware */ 4374f1ec4c1SMichal Simek temp = in_be32(&priv->dmarx->control); 4384f1ec4c1SMichal Simek temp |= XAXIDMA_CR_RUNSTOP_MASK; 4394f1ec4c1SMichal Simek out_be32(&priv->dmarx->control, temp); 4404f1ec4c1SMichal Simek 4414f1ec4c1SMichal Simek /* Rx BD is ready - start */ 4424f1ec4c1SMichal Simek out_be32(&priv->dmarx->tail, (u32)&rx_bd); 4434f1ec4c1SMichal Simek 4444f1ec4c1SMichal Simek /* Enable TX */ 4454f1ec4c1SMichal Simek out_be32(®s->tc, XAE_TC_TX_MASK); 4464f1ec4c1SMichal Simek /* Enable RX */ 4474f1ec4c1SMichal Simek out_be32(®s->rcw1, XAE_RCW1_RX_MASK); 4484f1ec4c1SMichal Simek 4494f1ec4c1SMichal Simek /* PHY setup */ 4504f1ec4c1SMichal Simek if (!setup_phy(dev)) { 4514f1ec4c1SMichal Simek axiemac_halt(dev); 4524f1ec4c1SMichal Simek return -1; 4534f1ec4c1SMichal Simek } 4544f1ec4c1SMichal Simek 4554f1ec4c1SMichal Simek debug("axiemac: Init complete\n"); 4564f1ec4c1SMichal Simek return 0; 4574f1ec4c1SMichal Simek } 4584f1ec4c1SMichal Simek 4598d094e5fSStephan Linz static int axiemac_send(struct eth_device *dev, void *ptr, int len) 4604f1ec4c1SMichal Simek { 4614f1ec4c1SMichal Simek struct axidma_priv *priv = dev->priv; 4624f1ec4c1SMichal Simek u32 timeout; 4634f1ec4c1SMichal Simek 4644f1ec4c1SMichal Simek if (len > PKTSIZE_ALIGN) 4654f1ec4c1SMichal Simek len = PKTSIZE_ALIGN; 4664f1ec4c1SMichal Simek 4674f1ec4c1SMichal Simek /* Flush packet to main memory to be trasfered by DMA */ 4684f1ec4c1SMichal Simek flush_cache((u32)ptr, len); 4694f1ec4c1SMichal Simek 4704f1ec4c1SMichal Simek /* Setup Tx BD */ 4714f1ec4c1SMichal Simek memset(&tx_bd, 0, sizeof(tx_bd)); 4724f1ec4c1SMichal Simek /* At the end of the ring, link the last BD back to the top */ 4734f1ec4c1SMichal Simek tx_bd.next = (u32)&tx_bd; 4744f1ec4c1SMichal Simek tx_bd.phys = (u32)ptr; 4754f1ec4c1SMichal Simek /* Save len */ 4764f1ec4c1SMichal Simek tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK | 4774f1ec4c1SMichal Simek XAXIDMA_BD_CTRL_TXEOF_MASK; 4784f1ec4c1SMichal Simek 4794f1ec4c1SMichal Simek /* Flush the last BD so DMA core could see the updates */ 4804f1ec4c1SMichal Simek flush_cache((u32)&tx_bd, sizeof(tx_bd)); 4814f1ec4c1SMichal Simek 4824f1ec4c1SMichal Simek if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) { 4834f1ec4c1SMichal Simek u32 temp; 4844f1ec4c1SMichal Simek out_be32(&priv->dmatx->current, (u32)&tx_bd); 4854f1ec4c1SMichal Simek /* Start the hardware */ 4864f1ec4c1SMichal Simek temp = in_be32(&priv->dmatx->control); 4874f1ec4c1SMichal Simek temp |= XAXIDMA_CR_RUNSTOP_MASK; 4884f1ec4c1SMichal Simek out_be32(&priv->dmatx->control, temp); 4894f1ec4c1SMichal Simek } 4904f1ec4c1SMichal Simek 4914f1ec4c1SMichal Simek /* Start transfer */ 4924f1ec4c1SMichal Simek out_be32(&priv->dmatx->tail, (u32)&tx_bd); 4934f1ec4c1SMichal Simek 4944f1ec4c1SMichal Simek /* Wait for transmission to complete */ 4954f1ec4c1SMichal Simek debug("axiemac: Waiting for tx to be done\n"); 4964f1ec4c1SMichal Simek timeout = 200; 4974f1ec4c1SMichal Simek while (timeout && (!in_be32(&priv->dmatx->status) & 4984f1ec4c1SMichal Simek (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) { 4994f1ec4c1SMichal Simek timeout--; 5004f1ec4c1SMichal Simek udelay(1); 5014f1ec4c1SMichal Simek } 5024f1ec4c1SMichal Simek if (!timeout) { 5034f1ec4c1SMichal Simek printf("%s: Timeout\n", __func__); 5044f1ec4c1SMichal Simek return 1; 5054f1ec4c1SMichal Simek } 5064f1ec4c1SMichal Simek 5074f1ec4c1SMichal Simek debug("axiemac: Sending complete\n"); 5084f1ec4c1SMichal Simek return 0; 5094f1ec4c1SMichal Simek } 5104f1ec4c1SMichal Simek 5114f1ec4c1SMichal Simek static int isrxready(struct eth_device *dev) 5124f1ec4c1SMichal Simek { 5134f1ec4c1SMichal Simek u32 status; 5144f1ec4c1SMichal Simek struct axidma_priv *priv = dev->priv; 5154f1ec4c1SMichal Simek 5164f1ec4c1SMichal Simek /* Read pending interrupts */ 5174f1ec4c1SMichal Simek status = in_be32(&priv->dmarx->status); 5184f1ec4c1SMichal Simek 5194f1ec4c1SMichal Simek /* Acknowledge pending interrupts */ 5204f1ec4c1SMichal Simek out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK); 5214f1ec4c1SMichal Simek 5224f1ec4c1SMichal Simek /* 5234f1ec4c1SMichal Simek * If Reception done interrupt is asserted, call RX call back function 5244f1ec4c1SMichal Simek * to handle the processed BDs and then raise the according flag. 5254f1ec4c1SMichal Simek */ 5264f1ec4c1SMichal Simek if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) 5274f1ec4c1SMichal Simek return 1; 5284f1ec4c1SMichal Simek 5294f1ec4c1SMichal Simek return 0; 5304f1ec4c1SMichal Simek } 5314f1ec4c1SMichal Simek 5324f1ec4c1SMichal Simek static int axiemac_recv(struct eth_device *dev) 5334f1ec4c1SMichal Simek { 5344f1ec4c1SMichal Simek u32 length; 5354f1ec4c1SMichal Simek struct axidma_priv *priv = dev->priv; 5364f1ec4c1SMichal Simek u32 temp; 5374f1ec4c1SMichal Simek 5384f1ec4c1SMichal Simek /* Wait for an incoming packet */ 5394f1ec4c1SMichal Simek if (!isrxready(dev)) 5404f1ec4c1SMichal Simek return 0; 5414f1ec4c1SMichal Simek 5424f1ec4c1SMichal Simek debug("axiemac: RX data ready\n"); 5434f1ec4c1SMichal Simek 5444f1ec4c1SMichal Simek /* Disable IRQ for a moment till packet is handled */ 5454f1ec4c1SMichal Simek temp = in_be32(&priv->dmarx->control); 5464f1ec4c1SMichal Simek temp &= ~XAXIDMA_IRQ_ALL_MASK; 5474f1ec4c1SMichal Simek out_be32(&priv->dmarx->control, temp); 5484f1ec4c1SMichal Simek 5494f1ec4c1SMichal Simek length = rx_bd.app4 & 0xFFFF; /* max length mask */ 5504f1ec4c1SMichal Simek #ifdef DEBUG 5514f1ec4c1SMichal Simek print_buffer(&rxframe, &rxframe[0], 1, length, 16); 5524f1ec4c1SMichal Simek #endif 5534f1ec4c1SMichal Simek /* Pass the received frame up for processing */ 5544f1ec4c1SMichal Simek if (length) 5554f1ec4c1SMichal Simek NetReceive(rxframe, length); 5564f1ec4c1SMichal Simek 5574f1ec4c1SMichal Simek #ifdef DEBUG 5584f1ec4c1SMichal Simek /* It is useful to clear buffer to be sure that it is consistent */ 5594f1ec4c1SMichal Simek memset(rxframe, 0, sizeof(rxframe)); 5604f1ec4c1SMichal Simek #endif 5614f1ec4c1SMichal Simek /* Setup RxBD */ 5624f1ec4c1SMichal Simek /* Clear the whole buffer and setup it again - all flags are cleared */ 5634f1ec4c1SMichal Simek memset(&rx_bd, 0, sizeof(rx_bd)); 5644f1ec4c1SMichal Simek rx_bd.next = (u32)&rx_bd; 5654f1ec4c1SMichal Simek rx_bd.phys = (u32)&rxframe; 5664f1ec4c1SMichal Simek rx_bd.cntrl = sizeof(rxframe); 5674f1ec4c1SMichal Simek 5684f1ec4c1SMichal Simek /* Write bd to HW */ 5694f1ec4c1SMichal Simek flush_cache((u32)&rx_bd, sizeof(rx_bd)); 5704f1ec4c1SMichal Simek 5714f1ec4c1SMichal Simek /* It is necessary to flush rxframe because if you don't do it 5724f1ec4c1SMichal Simek * then cache will contain previous packet */ 5734f1ec4c1SMichal Simek flush_cache((u32)&rxframe, sizeof(rxframe)); 5744f1ec4c1SMichal Simek 5754f1ec4c1SMichal Simek /* Rx BD is ready - start again */ 5764f1ec4c1SMichal Simek out_be32(&priv->dmarx->tail, (u32)&rx_bd); 5774f1ec4c1SMichal Simek 5784f1ec4c1SMichal Simek debug("axiemac: RX completed, framelength = %d\n", length); 5794f1ec4c1SMichal Simek 5804f1ec4c1SMichal Simek return length; 5814f1ec4c1SMichal Simek } 5824f1ec4c1SMichal Simek 5834f1ec4c1SMichal Simek static int axiemac_miiphy_read(const char *devname, uchar addr, 5844f1ec4c1SMichal Simek uchar reg, ushort *val) 5854f1ec4c1SMichal Simek { 5864f1ec4c1SMichal Simek struct eth_device *dev = eth_get_dev(); 5874f1ec4c1SMichal Simek u32 ret; 5884f1ec4c1SMichal Simek 5894f1ec4c1SMichal Simek ret = phyread(dev, addr, reg, val); 5904f1ec4c1SMichal Simek debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); 5914f1ec4c1SMichal Simek return ret; 5924f1ec4c1SMichal Simek } 5934f1ec4c1SMichal Simek 5944f1ec4c1SMichal Simek static int axiemac_miiphy_write(const char *devname, uchar addr, 5954f1ec4c1SMichal Simek uchar reg, ushort val) 5964f1ec4c1SMichal Simek { 5974f1ec4c1SMichal Simek struct eth_device *dev = eth_get_dev(); 5984f1ec4c1SMichal Simek 5994f1ec4c1SMichal Simek debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); 6004f1ec4c1SMichal Simek return phywrite(dev, addr, reg, val); 6014f1ec4c1SMichal Simek } 6024f1ec4c1SMichal Simek 6034f1ec4c1SMichal Simek static int axiemac_bus_reset(struct mii_dev *bus) 6044f1ec4c1SMichal Simek { 6054f1ec4c1SMichal Simek debug("axiemac: Bus reset\n"); 6064f1ec4c1SMichal Simek return 0; 6074f1ec4c1SMichal Simek } 6084f1ec4c1SMichal Simek 6094f1ec4c1SMichal Simek int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, 6104f1ec4c1SMichal Simek unsigned long dma_addr) 6114f1ec4c1SMichal Simek { 6124f1ec4c1SMichal Simek struct eth_device *dev; 6134f1ec4c1SMichal Simek struct axidma_priv *priv; 6144f1ec4c1SMichal Simek 6154f1ec4c1SMichal Simek dev = calloc(1, sizeof(struct eth_device)); 6164f1ec4c1SMichal Simek if (dev == NULL) 6174f1ec4c1SMichal Simek return -1; 6184f1ec4c1SMichal Simek 6194f1ec4c1SMichal Simek dev->priv = calloc(1, sizeof(struct axidma_priv)); 6204f1ec4c1SMichal Simek if (dev->priv == NULL) { 6214f1ec4c1SMichal Simek free(dev); 6224f1ec4c1SMichal Simek return -1; 6234f1ec4c1SMichal Simek } 6244f1ec4c1SMichal Simek priv = dev->priv; 6254f1ec4c1SMichal Simek 6264f1ec4c1SMichal Simek sprintf(dev->name, "aximac.%lx", base_addr); 6274f1ec4c1SMichal Simek 6284f1ec4c1SMichal Simek dev->iobase = base_addr; 6294f1ec4c1SMichal Simek priv->dmatx = (struct axidma_reg *)dma_addr; 6304f1ec4c1SMichal Simek /* RX channel offset is 0x30 */ 6314f1ec4c1SMichal Simek priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30); 6324f1ec4c1SMichal Simek dev->init = axiemac_init; 6334f1ec4c1SMichal Simek dev->halt = axiemac_halt; 6344f1ec4c1SMichal Simek dev->send = axiemac_send; 6354f1ec4c1SMichal Simek dev->recv = axiemac_recv; 6364f1ec4c1SMichal Simek dev->write_hwaddr = axiemac_setup_mac; 6374f1ec4c1SMichal Simek 6384f1ec4c1SMichal Simek #ifdef CONFIG_PHY_ADDR 6394f1ec4c1SMichal Simek priv->phyaddr = CONFIG_PHY_ADDR; 6404f1ec4c1SMichal Simek #else 6414f1ec4c1SMichal Simek priv->phyaddr = -1; 6424f1ec4c1SMichal Simek #endif 6434f1ec4c1SMichal Simek 6444f1ec4c1SMichal Simek eth_register(dev); 6454f1ec4c1SMichal Simek 6464f1ec4c1SMichal Simek #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 6474f1ec4c1SMichal Simek miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write); 6484f1ec4c1SMichal Simek priv->bus = miiphy_get_dev_by_name(dev->name); 6494f1ec4c1SMichal Simek priv->bus->reset = axiemac_bus_reset; 6504f1ec4c1SMichal Simek #endif 6514f1ec4c1SMichal Simek return 1; 6524f1ec4c1SMichal Simek } 653