xref: /openbmc/u-boot/drivers/net/uli526x.c (revision b9b1bc8542db5f26453c45db843903dee7056244)
1 /*
2  * Copyright 2007, 2010 Freescale Semiconductor, Inc.
3  *
4  * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
5  *
6  * Description:
7  * ULI 526x Ethernet port driver.
8  * Based on the Linux driver: drivers/net/tulip/uli526x.c
9  *
10  * This is free software; you can redistribute it and/or modify
11  * it under the terms of  the GNU General  Public License as published by
12  * the Free Software Foundation;  either version 2 of the  License, or
13  * (at your option) any later version.
14  */
15 
16 #include <common.h>
17 #include <malloc.h>
18 #include <net.h>
19 #include <netdev.h>
20 #include <asm/io.h>
21 #include <pci.h>
22 #include <miiphy.h>
23 
24 /* some kernel function compatible define */
25 
26 #undef DEBUG
27 
28 /* Board/System/Debug information/definition */
29 #define ULI_VENDOR_ID		0x10B9
30 #define ULI5261_DEVICE_ID	0x5261
31 #define ULI5263_DEVICE_ID	0x5263
32 /* ULi M5261 ID*/
33 #define PCI_ULI5261_ID		(ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID)
34 /* ULi M5263 ID*/
35 #define PCI_ULI5263_ID		(ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID)
36 
37 #define ULI526X_IO_SIZE	0x100
38 #define TX_DESC_CNT	0x10		/* Allocated Tx descriptors */
39 #define RX_DESC_CNT	PKTBUFSRX	/* Allocated Rx descriptors */
40 #define TX_FREE_DESC_CNT	(TX_DESC_CNT - 2) /* Max TX packet count */
41 #define TX_WAKE_DESC_CNT	(TX_DESC_CNT - 3) /* TX wakeup count */
42 #define DESC_ALL_CNT		(TX_DESC_CNT + RX_DESC_CNT)
43 #define TX_BUF_ALLOC		0x300
44 #define RX_ALLOC_SIZE		PKTSIZE
45 #define ULI526X_RESET		1
46 #define CR0_DEFAULT		0
47 #define CR6_DEFAULT		0x22200000
48 #define CR7_DEFAULT		0x180c1
49 #define CR15_DEFAULT		0x06		/* TxJabber RxWatchdog */
50 #define TDES0_ERR_MASK		0x4302		/* TXJT, LC, EC, FUE */
51 #define MAX_PACKET_SIZE		1514
52 #define ULI5261_MAX_MULTICAST	14
53 #define RX_COPY_SIZE		100
54 #define MAX_CHECK_PACKET	0x8000
55 
56 #define ULI526X_10MHF		0
57 #define ULI526X_100MHF		1
58 #define ULI526X_10MFD		4
59 #define ULI526X_100MFD		5
60 #define ULI526X_AUTO		8
61 
62 #define ULI526X_TXTH_72		0x400000	/* TX TH 72 byte */
63 #define ULI526X_TXTH_96		0x404000	/* TX TH 96 byte */
64 #define ULI526X_TXTH_128	0x0000		/* TX TH 128 byte */
65 #define ULI526X_TXTH_256	0x4000		/* TX TH 256 byte */
66 #define ULI526X_TXTH_512	0x8000		/* TX TH 512 byte */
67 #define ULI526X_TXTH_1K		0xC000		/* TX TH 1K  byte */
68 
69 /* CR9 definition: SROM/MII */
70 #define CR9_SROM_READ		0x4800
71 #define CR9_SRCS		0x1
72 #define CR9_SRCLK		0x2
73 #define CR9_CRDOUT		0x8
74 #define SROM_DATA_0		0x0
75 #define SROM_DATA_1		0x4
76 #define PHY_DATA_1		0x20000
77 #define PHY_DATA_0		0x00000
78 #define MDCLKH			0x10000
79 
80 #define PHY_POWER_DOWN	0x800
81 
82 #define SROM_V41_CODE		0x14
83 
84 #define SROM_CLK_WRITE(data, ioaddr) do {			\
85 	outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr);		\
86 	udelay(5);						\
87 	outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr);	\
88 	udelay(5);						\
89 	outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr);		\
90 	udelay(5);						\
91 	} while (0)
92 
93 /* Structure/enum declaration */
94 
95 struct tx_desc {
96 	u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
97 	char *tx_buf_ptr;		/* Data for us */
98 	struct tx_desc *next_tx_desc;
99 };
100 
101 struct rx_desc {
102 	u32 rdes0, rdes1, rdes2, rdes3;	/* Data for the card */
103 	char *rx_buf_ptr;		/* Data for us */
104 	struct rx_desc *next_rx_desc;
105 };
106 
107 struct uli526x_board_info {
108 	u32 chip_id;	/* Chip vendor/Device ID */
109 	pci_dev_t pdev;
110 
111 	long ioaddr;			/* I/O base address */
112 	u32 cr0_data;
113 	u32 cr5_data;
114 	u32 cr6_data;
115 	u32 cr7_data;
116 	u32 cr15_data;
117 
118 	/* pointer for memory physical address */
119 	dma_addr_t buf_pool_dma_ptr;	/* Tx buffer pool memory */
120 	dma_addr_t buf_pool_dma_start;	/* Tx buffer pool align dword */
121 	dma_addr_t desc_pool_dma_ptr;	/* descriptor pool memory */
122 	dma_addr_t first_tx_desc_dma;
123 	dma_addr_t first_rx_desc_dma;
124 
125 	/* descriptor pointer */
126 	unsigned char *buf_pool_ptr;	/* Tx buffer pool memory */
127 	unsigned char *buf_pool_start;	/* Tx buffer pool align dword */
128 	unsigned char *desc_pool_ptr;	/* descriptor pool memory */
129 	struct tx_desc *first_tx_desc;
130 	struct tx_desc *tx_insert_ptr;
131 	struct tx_desc *tx_remove_ptr;
132 	struct rx_desc *first_rx_desc;
133 	struct rx_desc *rx_ready_ptr;	/* packet come pointer */
134 	unsigned long tx_packet_cnt;	/* transmitted packet count */
135 
136 	u16 PHY_reg4;			/* Saved Phyxcer register 4 value */
137 
138 	u8 media_mode;			/* user specify media mode */
139 	u8 op_mode;			/* real work dedia mode */
140 	u8 phy_addr;
141 
142 	/* NIC SROM data */
143 	unsigned char srom[128];
144 };
145 
146 enum uli526x_offsets {
147 	DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
148 	DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
149 	DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
150 	DCR15 = 0x78
151 };
152 
153 enum uli526x_CR6_bits {
154 	CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
155 	CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
156 	CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
157 };
158 
159 /* Global variable declaration -- */
160 
161 static unsigned char uli526x_media_mode = ULI526X_AUTO;
162 
163 static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
164 	__attribute__ ((aligned(32)));
165 static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
166 
167 /* For module input parameter */
168 static int mode = 8;
169 
170 /* function declaration -- */
171 static int uli526x_start_xmit(struct eth_device *dev,
172 				volatile void *packet, int length);
173 static const struct ethtool_ops netdev_ethtool_ops;
174 static u16 read_srom_word(long, int);
175 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
176 static void allocate_rx_buffer(struct uli526x_board_info *);
177 static void update_cr6(u32, unsigned long);
178 static u16 phy_read(unsigned long, u8, u8, u32);
179 static u16 phy_readby_cr10(unsigned long, u8, u8);
180 static void phy_write(unsigned long, u8, u8, u16, u32);
181 static void phy_writeby_cr10(unsigned long, u8, u8, u16);
182 static void phy_write_1bit(unsigned long, u32, u32);
183 static u16 phy_read_1bit(unsigned long, u32);
184 static int uli526x_rx_packet(struct eth_device *);
185 static void uli526x_free_tx_pkt(struct eth_device *,
186 		struct uli526x_board_info *);
187 static void uli526x_reuse_buf(struct rx_desc *);
188 static void uli526x_init(struct eth_device *);
189 static void uli526x_set_phyxcer(struct uli526x_board_info *);
190 
191 
192 static int uli526x_init_one(struct eth_device *, bd_t *);
193 static void uli526x_disable(struct eth_device *);
194 static void set_mac_addr(struct eth_device *);
195 
196 static struct pci_device_id uli526x_pci_tbl[] = {
197 	{ ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
198 	{ ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
199 	{}
200 };
201 
202 /* ULI526X network board routine */
203 
204 /*
205  *	Search ULI526X board, register it
206  */
207 
208 int uli526x_initialize(bd_t *bis)
209 {
210 	pci_dev_t devno;
211 	int card_number = 0;
212 	struct eth_device *dev;
213 	struct uli526x_board_info *db;	/* board information structure */
214 
215 	u32 iobase;
216 	int idx = 0;
217 
218 	while (1) {
219 		/* Find PCI device */
220 		devno = pci_find_devices(uli526x_pci_tbl, idx++);
221 		if (devno < 0)
222 			break;
223 
224 		pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
225 		iobase &= ~0xf;
226 
227 		dev = (struct eth_device *)malloc(sizeof *dev);
228 		sprintf(dev->name, "uli526x#%d", card_number);
229 		db = (struct uli526x_board_info *)
230 			malloc(sizeof(struct uli526x_board_info));
231 
232 		dev->priv = db;
233 		db->pdev = devno;
234 		dev->iobase = iobase;
235 
236 		dev->init = uli526x_init_one;
237 		dev->halt = uli526x_disable;
238 		dev->send = uli526x_start_xmit;
239 		dev->recv = uli526x_rx_packet;
240 
241 		/* init db */
242 		db->ioaddr = dev->iobase;
243 		/* get chip id */
244 
245 		pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
246 #ifdef DEBUG
247 		printf("uli526x: uli526x @0x%x\n", iobase);
248 		printf("uli526x: chip_id%x\n", db->chip_id);
249 #endif
250 		eth_register(dev);
251 		card_number++;
252 		pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
253 		udelay(10 * 1000);
254 	}
255 	return card_number;
256 }
257 
258 static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
259 {
260 
261 	struct uli526x_board_info *db = dev->priv;
262 	int i;
263 
264 	switch (mode) {
265 	case ULI526X_10MHF:
266 	case ULI526X_100MHF:
267 	case ULI526X_10MFD:
268 	case ULI526X_100MFD:
269 		uli526x_media_mode = mode;
270 		break;
271 	default:
272 		uli526x_media_mode = ULI526X_AUTO;
273 		break;
274 	}
275 
276 	/* Allocate Tx/Rx descriptor memory */
277 	db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
278 	db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
279 	if (db->desc_pool_ptr == NULL)
280 		return -1;
281 
282 	db->buf_pool_ptr = (uchar *)&buf_pool[0];
283 	db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
284 	if (db->buf_pool_ptr == NULL)
285 		return -1;
286 
287 	db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
288 	db->first_tx_desc_dma = db->desc_pool_dma_ptr;
289 
290 	db->buf_pool_start = db->buf_pool_ptr;
291 	db->buf_pool_dma_start = db->buf_pool_dma_ptr;
292 
293 #ifdef DEBUG
294 	printf("%s(): db->ioaddr= 0x%x\n",
295 		__FUNCTION__, db->ioaddr);
296 	printf("%s(): media_mode= 0x%x\n",
297 		__FUNCTION__, uli526x_media_mode);
298 	printf("%s(): db->desc_pool_ptr= 0x%x\n",
299 		__FUNCTION__, db->desc_pool_ptr);
300 	printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
301 		__FUNCTION__, db->desc_pool_dma_ptr);
302 	printf("%s(): db->buf_pool_ptr= 0x%x\n",
303 		__FUNCTION__, db->buf_pool_ptr);
304 	printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
305 		__FUNCTION__, db->buf_pool_dma_ptr);
306 #endif
307 
308 	/* read 64 word srom data */
309 	for (i = 0; i < 64; i++)
310 		((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
311 			i));
312 
313 	/* Set Node address */
314 	if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) ||
315 	    ((db->srom[0] == 0x00) && (db->srom[1] == 0x00)))
316 	/* SROM absent, so write MAC address to ID Table */
317 		set_mac_addr(dev);
318 	else {		/*Exist SROM*/
319 		for (i = 0; i < 6; i++)
320 			dev->enetaddr[i] = db->srom[20 + i];
321 	}
322 #ifdef DEBUG
323 	for (i = 0; i < 6; i++)
324 		printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
325 #endif
326 	db->PHY_reg4 = 0x1e0;
327 
328 	/* system variable init */
329 	db->cr6_data = CR6_DEFAULT ;
330 	db->cr6_data |= ULI526X_TXTH_256;
331 	db->cr0_data = CR0_DEFAULT;
332 	uli526x_init(dev);
333 	return 0;
334 }
335 
336 static void uli526x_disable(struct eth_device *dev)
337 {
338 #ifdef DEBUG
339 	printf("uli526x_disable\n");
340 #endif
341 	struct uli526x_board_info *db = dev->priv;
342 
343 	if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
344 		/* Reset & stop ULI526X board */
345 		outl(ULI526X_RESET, db->ioaddr + DCR0);
346 		udelay(5);
347 		phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
348 
349 		/* reset the board */
350 		db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);	/* Disable Tx/Rx */
351 		update_cr6(db->cr6_data, dev->iobase);
352 		outl(0, dev->iobase + DCR7);		/* Disable Interrupt */
353 		outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
354 	}
355 }
356 
357 /*	Initialize ULI526X board
358  *	Reset ULI526X board
359  *	Initialize TX/Rx descriptor chain structure
360  *	Send the set-up frame
361  *	Enable Tx/Rx machine
362  */
363 
364 static void uli526x_init(struct eth_device *dev)
365 {
366 
367 	struct uli526x_board_info *db = dev->priv;
368 	u8	phy_tmp;
369 	u16	phy_value;
370 	u16 phy_reg_reset;
371 
372 	/* Reset M526x MAC controller */
373 	outl(ULI526X_RESET, db->ioaddr + DCR0);	/* RESET MAC */
374 	udelay(100);
375 	outl(db->cr0_data, db->ioaddr + DCR0);
376 	udelay(5);
377 
378 	/* Phy addr : In some boards,M5261/M5263 phy address != 1 */
379 	db->phy_addr = 1;
380 	db->tx_packet_cnt = 0;
381 	for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
382 		/* peer add */
383 		phy_value = phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
384 		if (phy_value != 0xffff && phy_value != 0) {
385 			db->phy_addr = phy_tmp;
386 			break;
387 		}
388 	}
389 
390 #ifdef DEBUG
391 	printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
392 	printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
393 #endif
394 	if (phy_tmp == 32)
395 		printf("Can not find the phy address!!!");
396 
397 	/* Parser SROM and media mode */
398 	db->media_mode = uli526x_media_mode;
399 
400 	if (!(inl(db->ioaddr + DCR12) & 0x8)) {
401 		/* Phyxcer capability setting */
402 		phy_reg_reset = phy_read(db->ioaddr,
403 			db->phy_addr, 0, db->chip_id);
404 		phy_reg_reset = (phy_reg_reset | 0x8000);
405 		phy_write(db->ioaddr, db->phy_addr, 0,
406 			phy_reg_reset, db->chip_id);
407 		udelay(500);
408 
409 		/* Process Phyxcer Media Mode */
410 		uli526x_set_phyxcer(db);
411 	}
412 	/* Media Mode Process */
413 	if (!(db->media_mode & ULI526X_AUTO))
414 		db->op_mode = db->media_mode;	/* Force Mode */
415 
416 	/* Initialize Transmit/Receive decriptor and CR3/4 */
417 	uli526x_descriptor_init(db, db->ioaddr);
418 
419 	/* Init CR6 to program M526X operation */
420 	update_cr6(db->cr6_data, db->ioaddr);
421 
422 	/* Init CR7, interrupt active bit */
423 	db->cr7_data = CR7_DEFAULT;
424 	outl(db->cr7_data, db->ioaddr + DCR7);
425 
426 	/* Init CR15, Tx jabber and Rx watchdog timer */
427 	outl(db->cr15_data, db->ioaddr + DCR15);
428 
429 	/* Enable ULI526X Tx/Rx function */
430 	db->cr6_data |= CR6_RXSC | CR6_TXSC;
431 	update_cr6(db->cr6_data, db->ioaddr);
432 	while (!(inl(db->ioaddr + DCR12) & 0x8))
433 		udelay(10);
434 }
435 
436 /*
437  *	Hardware start transmission.
438  *	Send a packet to media from the upper layer.
439  */
440 
441 static int uli526x_start_xmit(struct eth_device *dev,
442 				volatile void *packet, int length)
443 {
444 	struct uli526x_board_info *db = dev->priv;
445 	struct tx_desc *txptr;
446 	unsigned int len = length;
447 	/* Too large packet check */
448 	if (len > MAX_PACKET_SIZE) {
449 		printf(": big packet = %d\n", len);
450 		return 0;
451 	}
452 
453 	/* No Tx resource check, it never happen nromally */
454 	if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
455 		printf("No Tx resource %ld\n", db->tx_packet_cnt);
456 		return 0;
457 	}
458 
459 	/* Disable NIC interrupt */
460 	outl(0, dev->iobase + DCR7);
461 
462 	/* transmit this packet */
463 	txptr = db->tx_insert_ptr;
464 	memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
465 	txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
466 
467 	/* Point to next transmit free descriptor */
468 	db->tx_insert_ptr = txptr->next_tx_desc;
469 
470 	/* Transmit Packet Process */
471 	if ((db->tx_packet_cnt < TX_DESC_CNT)) {
472 		txptr->tdes0 = cpu_to_le32(0x80000000);	/* Set owner bit */
473 		db->tx_packet_cnt++;			/* Ready to send */
474 		outl(0x1, dev->iobase + DCR1);	/* Issue Tx polling */
475 	}
476 
477 	/* Got ULI526X status */
478 	db->cr5_data = inl(db->ioaddr + DCR5);
479 	outl(db->cr5_data, db->ioaddr + DCR5);
480 
481 #ifdef TX_DEBUG
482 	printf("%s(): length = 0x%x\n", __FUNCTION__, length);
483 	printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
484 #endif
485 
486 	outl(db->cr7_data, dev->iobase + DCR7);
487 	uli526x_free_tx_pkt(dev, db);
488 
489 	return length;
490 }
491 
492 /*
493  *	Free TX resource after TX complete
494  */
495 
496 static void uli526x_free_tx_pkt(struct eth_device *dev,
497 	struct uli526x_board_info *db)
498 {
499 	struct tx_desc *txptr;
500 	u32 tdes0;
501 
502 	txptr = db->tx_remove_ptr;
503 	while (db->tx_packet_cnt) {
504 		tdes0 = le32_to_cpu(txptr->tdes0);
505 		/* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
506 		if (tdes0 & 0x80000000)
507 			break;
508 
509 		/* A packet sent completed */
510 		db->tx_packet_cnt--;
511 
512 		if (tdes0 != 0x7fffffff) {
513 #ifdef TX_DEBUG
514 			printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
515 #endif
516 			if (tdes0 & TDES0_ERR_MASK) {
517 				if (tdes0 & 0x0002) {	/* UnderRun */
518 					if (!(db->cr6_data & CR6_SFT)) {
519 						db->cr6_data = db->cr6_data |
520 							CR6_SFT;
521 						update_cr6(db->cr6_data,
522 							db->ioaddr);
523 					}
524 				}
525 			}
526 		}
527 
528 		txptr = txptr->next_tx_desc;
529 	}/* End of while */
530 
531 	/* Update TX remove pointer to next */
532 	db->tx_remove_ptr = txptr;
533 }
534 
535 
536 /*
537  *	Receive the come packet and pass to upper layer
538  */
539 
540 static int uli526x_rx_packet(struct eth_device *dev)
541 {
542 	struct uli526x_board_info *db = dev->priv;
543 	struct rx_desc *rxptr;
544 	int rxlen = 0;
545 	u32 rdes0;
546 
547 	rxptr = db->rx_ready_ptr;
548 
549 	rdes0 = le32_to_cpu(rxptr->rdes0);
550 #ifdef RX_DEBUG
551 	printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0);
552 #endif
553 	if (!(rdes0 & 0x80000000)) {	/* packet owner check */
554 		if ((rdes0 & 0x300) != 0x300) {
555 			/* A packet without First/Last flag */
556 			/* reuse this buf */
557 			printf("A packet without First/Last flag");
558 			uli526x_reuse_buf(rxptr);
559 		} else {
560 			/* A packet with First/Last flag */
561 			rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
562 #ifdef RX_DEBUG
563 			printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
564 #endif
565 			/* error summary bit check */
566 			if (rdes0 & 0x8000) {
567 				/* This is a error packet */
568 				printf("Error: rdes0: %x\n", rdes0);
569 			}
570 
571 			if (!(rdes0 & 0x8000) ||
572 				((db->cr6_data & CR6_PM) && (rxlen > 6))) {
573 
574 #ifdef RX_DEBUG
575 				printf("%s(): rx_skb_ptr =%x\n",
576 					__FUNCTION__, rxptr->rx_buf_ptr);
577 				printf("%s(): rxlen =%x\n",
578 					__FUNCTION__, rxlen);
579 
580 				printf("%s(): buf addr =%x\n",
581 					__FUNCTION__, rxptr->rx_buf_ptr);
582 				printf("%s(): rxlen =%x\n",
583 					__FUNCTION__, rxlen);
584 				int i;
585 				for (i = 0; i < 0x20; i++)
586 					printf("%s(): data[%x] =%x\n",
587 					__FUNCTION__, i, rxptr->rx_buf_ptr[i]);
588 #endif
589 
590 				NetReceive((uchar *)rxptr->rx_buf_ptr, rxlen);
591 				uli526x_reuse_buf(rxptr);
592 
593 			} else {
594 				/* Reuse SKB buffer when the packet is error */
595 				printf("Reuse buffer, rdes0");
596 				uli526x_reuse_buf(rxptr);
597 			}
598 		}
599 
600 		rxptr = rxptr->next_rx_desc;
601 	}
602 
603 	db->rx_ready_ptr = rxptr;
604 	return rxlen;
605 }
606 
607 /*
608  *	Reuse the RX buffer
609  */
610 
611 static void uli526x_reuse_buf(struct rx_desc *rxptr)
612 {
613 
614 	if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
615 		rxptr->rdes0 = cpu_to_le32(0x80000000);
616 	else
617 		printf("Buffer reuse method error");
618 }
619 /*
620  *	Initialize transmit/Receive descriptor
621  *	Using Chain structure, and allocate Tx/Rx buffer
622  */
623 
624 static void uli526x_descriptor_init(struct uli526x_board_info *db,
625 	unsigned long ioaddr)
626 {
627 	struct tx_desc *tmp_tx;
628 	struct rx_desc *tmp_rx;
629 	unsigned char *tmp_buf;
630 	dma_addr_t tmp_tx_dma, tmp_rx_dma;
631 	dma_addr_t tmp_buf_dma;
632 	int i;
633 	/* tx descriptor start pointer */
634 	db->tx_insert_ptr = db->first_tx_desc;
635 	db->tx_remove_ptr = db->first_tx_desc;
636 
637 	outl(db->first_tx_desc_dma, ioaddr + DCR4);     /* TX DESC address */
638 
639 	/* rx descriptor start pointer */
640 	db->first_rx_desc = (void *)db->first_tx_desc +
641 		sizeof(struct tx_desc) * TX_DESC_CNT;
642 	db->first_rx_desc_dma =  db->first_tx_desc_dma +
643 		sizeof(struct tx_desc) * TX_DESC_CNT;
644 	db->rx_ready_ptr = db->first_rx_desc;
645 	outl(db->first_rx_desc_dma, ioaddr + DCR3);	/* RX DESC address */
646 #ifdef DEBUG
647 	printf("%s(): db->first_tx_desc= 0x%x\n",
648 		__FUNCTION__, db->first_tx_desc);
649 	printf("%s(): db->first_rx_desc_dma= 0x%x\n",
650 		__FUNCTION__, db->first_rx_desc_dma);
651 #endif
652 	/* Init Transmit chain */
653 	tmp_buf = db->buf_pool_start;
654 	tmp_buf_dma = db->buf_pool_dma_start;
655 	tmp_tx_dma = db->first_tx_desc_dma;
656 	for (tmp_tx = db->first_tx_desc, i = 0;
657 			i < TX_DESC_CNT; i++, tmp_tx++) {
658 		tmp_tx->tx_buf_ptr = (char *)tmp_buf;
659 		tmp_tx->tdes0 = cpu_to_le32(0);
660 		tmp_tx->tdes1 = cpu_to_le32(0x81000000);	/* IC, chain */
661 		tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
662 		tmp_tx_dma += sizeof(struct tx_desc);
663 		tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
664 		tmp_tx->next_tx_desc = tmp_tx + 1;
665 		tmp_buf = tmp_buf + TX_BUF_ALLOC;
666 		tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
667 	}
668 	(--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
669 	tmp_tx->next_tx_desc = db->first_tx_desc;
670 
671 	 /* Init Receive descriptor chain */
672 	tmp_rx_dma = db->first_rx_desc_dma;
673 	for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
674 			i++, tmp_rx++) {
675 		tmp_rx->rdes0 = cpu_to_le32(0);
676 		tmp_rx->rdes1 = cpu_to_le32(0x01000600);
677 		tmp_rx_dma += sizeof(struct rx_desc);
678 		tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
679 		tmp_rx->next_rx_desc = tmp_rx + 1;
680 	}
681 	(--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
682 	tmp_rx->next_rx_desc = db->first_rx_desc;
683 
684 	/* pre-allocate Rx buffer */
685 	allocate_rx_buffer(db);
686 }
687 
688 /*
689  *	Update CR6 value
690  *	Firstly stop ULI526X, then written value and start
691  */
692 
693 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
694 {
695 
696 	outl(cr6_data, ioaddr + DCR6);
697 	udelay(5);
698 }
699 
700 /*
701  *	Allocate rx buffer,
702  */
703 
704 static void allocate_rx_buffer(struct uli526x_board_info *db)
705 {
706 	int index;
707 	struct rx_desc *rxptr;
708 	rxptr = db->first_rx_desc;
709 	u32 addr;
710 
711 	for (index = 0; index < RX_DESC_CNT; index++) {
712 		addr = (u32)NetRxPackets[index];
713 		addr += (16 - (addr & 15));
714 		rxptr->rx_buf_ptr = (char *) addr;
715 		rxptr->rdes2 = cpu_to_le32(addr);
716 		rxptr->rdes0 = cpu_to_le32(0x80000000);
717 #ifdef DEBUG
718 		printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
719 		printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
720 		printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
721 		printf("%s(): rxptr buf address = 0x%x\n", \
722 			__FUNCTION__, rxptr->rx_buf_ptr);
723 		printf("%s(): rdes2  = 0x%x\n", __FUNCTION__, rxptr->rdes2);
724 #endif
725 		rxptr = rxptr->next_rx_desc;
726 	}
727 }
728 
729 /*
730  *	Read one word data from the serial ROM
731  */
732 
733 static u16 read_srom_word(long ioaddr, int offset)
734 {
735 	int i;
736 	u16 srom_data = 0;
737 	long cr9_ioaddr = ioaddr + DCR9;
738 
739 	outl(CR9_SROM_READ, cr9_ioaddr);
740 	outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
741 
742 	/* Send the Read Command 110b */
743 	SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
744 	SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
745 	SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
746 
747 	/* Send the offset */
748 	for (i = 5; i >= 0; i--) {
749 		srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
750 		SROM_CLK_WRITE(srom_data, cr9_ioaddr);
751 	}
752 
753 	outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
754 
755 	for (i = 16; i > 0; i--) {
756 		outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
757 		udelay(5);
758 		srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
759 			? 1 : 0);
760 		outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
761 		udelay(5);
762 	}
763 
764 	outl(CR9_SROM_READ, cr9_ioaddr);
765 	return srom_data;
766 }
767 
768 /*
769  *	Set 10/100 phyxcer capability
770  *	AUTO mode : phyxcer register4 is NIC capability
771  *	Force mode: phyxcer register4 is the force media
772  */
773 
774 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
775 {
776 	u16 phy_reg;
777 
778 	/* Phyxcer capability setting */
779 	phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
780 
781 	if (db->media_mode & ULI526X_AUTO) {
782 		/* AUTO Mode */
783 		phy_reg |= db->PHY_reg4;
784 	} else {
785 		/* Force Mode */
786 		switch (db->media_mode) {
787 		case ULI526X_10MHF: phy_reg |= 0x20; break;
788 		case ULI526X_10MFD: phy_reg |= 0x40; break;
789 		case ULI526X_100MHF: phy_reg |= 0x80; break;
790 		case ULI526X_100MFD: phy_reg |= 0x100; break;
791 		}
792 
793 	}
794 
795 	/* Write new capability to Phyxcer Reg4 */
796 	if (!(phy_reg & 0x01e0)) {
797 		phy_reg |= db->PHY_reg4;
798 		db->media_mode |= ULI526X_AUTO;
799 	}
800 	phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
801 
802 	/* Restart Auto-Negotiation */
803 	phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
804 	udelay(50);
805 }
806 
807 /*
808  *	Write a word to Phy register
809  */
810 
811 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
812 	u16 phy_data, u32 chip_id)
813 {
814 	u16 i;
815 	unsigned long ioaddr;
816 
817 	if (chip_id == PCI_ULI5263_ID) {
818 		phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
819 		return;
820 	}
821 	/* M5261/M5263 Chip */
822 	ioaddr = iobase + DCR9;
823 
824 	/* Send 33 synchronization clock to Phy controller */
825 	for (i = 0; i < 35; i++)
826 		phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
827 
828 	/* Send start command(01) to Phy */
829 	phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
830 	phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
831 
832 	/* Send write command(01) to Phy */
833 	phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
834 	phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
835 
836 	/* Send Phy address */
837 	for (i = 0x10; i > 0; i = i >> 1)
838 		phy_write_1bit(ioaddr, phy_addr & i ?
839 			PHY_DATA_1 : PHY_DATA_0, chip_id);
840 
841 	/* Send register address */
842 	for (i = 0x10; i > 0; i = i >> 1)
843 		phy_write_1bit(ioaddr, offset & i ?
844 			PHY_DATA_1 : PHY_DATA_0, chip_id);
845 
846 	/* written trasnition */
847 	phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
848 	phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
849 
850 	/* Write a word data to PHY controller */
851 	for (i = 0x8000; i > 0; i >>= 1)
852 		phy_write_1bit(ioaddr, phy_data & i ?
853 			PHY_DATA_1 : PHY_DATA_0, chip_id);
854 }
855 
856 /*
857  *	Read a word data from phy register
858  */
859 
860 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
861 {
862 	int i;
863 	u16 phy_data;
864 	unsigned long ioaddr;
865 
866 	if (chip_id == PCI_ULI5263_ID)
867 		return phy_readby_cr10(iobase, phy_addr, offset);
868 	/* M5261/M5263 Chip */
869 	ioaddr = iobase + DCR9;
870 
871 	/* Send 33 synchronization clock to Phy controller */
872 	for (i = 0; i < 35; i++)
873 		phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
874 
875 	/* Send start command(01) to Phy */
876 	phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
877 	phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
878 
879 	/* Send read command(10) to Phy */
880 	phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
881 	phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
882 
883 	/* Send Phy address */
884 	for (i = 0x10; i > 0; i = i >> 1)
885 		phy_write_1bit(ioaddr, phy_addr & i ?
886 			PHY_DATA_1 : PHY_DATA_0, chip_id);
887 
888 	/* Send register address */
889 	for (i = 0x10; i > 0; i = i >> 1)
890 		phy_write_1bit(ioaddr, offset & i ?
891 			PHY_DATA_1 : PHY_DATA_0, chip_id);
892 
893 	/* Skip transition state */
894 	phy_read_1bit(ioaddr, chip_id);
895 
896 	/* read 16bit data */
897 	for (phy_data = 0, i = 0; i < 16; i++) {
898 		phy_data <<= 1;
899 		phy_data |= phy_read_1bit(ioaddr, chip_id);
900 	}
901 
902 	return phy_data;
903 }
904 
905 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
906 {
907 	unsigned long ioaddr, cr10_value;
908 
909 	ioaddr = iobase + DCR10;
910 	cr10_value = phy_addr;
911 	cr10_value = (cr10_value<<5) + offset;
912 	cr10_value = (cr10_value<<16) + 0x08000000;
913 	outl(cr10_value, ioaddr);
914 	udelay(1);
915 	while (1) {
916 		cr10_value = inl(ioaddr);
917 		if (cr10_value & 0x10000000)
918 			break;
919 	}
920 	return (cr10_value&0x0ffff);
921 }
922 
923 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
924 	u8 offset, u16 phy_data)
925 {
926 	unsigned long ioaddr, cr10_value;
927 
928 	ioaddr = iobase + DCR10;
929 	cr10_value = phy_addr;
930 	cr10_value = (cr10_value<<5) + offset;
931 	cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
932 	outl(cr10_value, ioaddr);
933 	udelay(1);
934 }
935 /*
936  *	Write one bit data to Phy Controller
937  */
938 
939 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
940 {
941 	outl(phy_data , ioaddr);			/* MII Clock Low */
942 	udelay(1);
943 	outl(phy_data  | MDCLKH, ioaddr);	/* MII Clock High */
944 	udelay(1);
945 	outl(phy_data , ioaddr);			/* MII Clock Low */
946 	udelay(1);
947 }
948 
949 /*
950  *	Read one bit phy data from PHY controller
951  */
952 
953 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
954 {
955 	u16 phy_data;
956 
957 	outl(0x50000 , ioaddr);
958 	udelay(1);
959 	phy_data = (inl(ioaddr) >> 19) & 0x1;
960 	outl(0x40000 , ioaddr);
961 	udelay(1);
962 
963 	return phy_data;
964 }
965 
966 /*
967  * Set MAC address to ID Table
968  */
969 
970 static void set_mac_addr(struct eth_device *dev)
971 {
972 	int i;
973 	u16 addr;
974 	struct uli526x_board_info *db = dev->priv;
975 	outl(0x10000, db->ioaddr + DCR0);	/* Diagnosis mode */
976 	/* Reset dianostic pointer port */
977 	outl(0x1c0, db->ioaddr + DCR13);
978 	outl(0, db->ioaddr + DCR14);	/* Clear reset port */
979 	outl(0x10, db->ioaddr + DCR14);	/* Reset ID Table pointer */
980 	outl(0, db->ioaddr + DCR14);	/* Clear reset port */
981 	outl(0, db->ioaddr + DCR13);	/* Clear CR13 */
982 	/* Select ID Table access port */
983 	outl(0x1b0, db->ioaddr + DCR13);
984 	/* Read MAC address from CR14 */
985 	for (i = 0; i < 3; i++) {
986 		addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
987 		outl(addr, db->ioaddr + DCR14);
988 	}
989 	/* write end */
990 	outl(0, db->ioaddr + DCR13);	/* Clear CR13 */
991 	outl(0, db->ioaddr + DCR0);	/* Clear CR0 */
992 	udelay(10);
993 	return;
994 }
995