1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. 3 * 4 * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007 5 * 6 * Description: 7 * ULI 526x Ethernet port driver. 8 * Based on the Linux driver: drivers/net/tulip/uli526x.c 9 * 10 * This is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 */ 15 16 #include <common.h> 17 #include <malloc.h> 18 #include <net.h> 19 #include <asm/io.h> 20 #include <pci.h> 21 #include <miiphy.h> 22 23 /* some kernel function compatible define */ 24 25 #undef DEBUG 26 27 /* Board/System/Debug information/definition */ 28 #define ULI_VENDOR_ID 0x10B9 29 #define ULI5261_DEVICE_ID 0x5261 30 #define ULI5263_DEVICE_ID 0x5263 31 /* ULi M5261 ID*/ 32 #define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID) 33 /* ULi M5263 ID*/ 34 #define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID) 35 36 #define ULI526X_IO_SIZE 0x100 37 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */ 38 #define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */ 39 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */ 40 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */ 41 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT) 42 #define TX_BUF_ALLOC 0x300 43 #define RX_ALLOC_SIZE PKTSIZE 44 #define ULI526X_RESET 1 45 #define CR0_DEFAULT 0 46 #define CR6_DEFAULT 0x22200000 47 #define CR7_DEFAULT 0x180c1 48 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */ 49 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */ 50 #define MAX_PACKET_SIZE 1514 51 #define ULI5261_MAX_MULTICAST 14 52 #define RX_COPY_SIZE 100 53 #define MAX_CHECK_PACKET 0x8000 54 55 #define ULI526X_10MHF 0 56 #define ULI526X_100MHF 1 57 #define ULI526X_10MFD 4 58 #define ULI526X_100MFD 5 59 #define ULI526X_AUTO 8 60 61 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */ 62 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */ 63 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */ 64 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */ 65 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */ 66 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */ 67 68 /* CR9 definition: SROM/MII */ 69 #define CR9_SROM_READ 0x4800 70 #define CR9_SRCS 0x1 71 #define CR9_SRCLK 0x2 72 #define CR9_CRDOUT 0x8 73 #define SROM_DATA_0 0x0 74 #define SROM_DATA_1 0x4 75 #define PHY_DATA_1 0x20000 76 #define PHY_DATA_0 0x00000 77 #define MDCLKH 0x10000 78 79 #define PHY_POWER_DOWN 0x800 80 81 #define SROM_V41_CODE 0x14 82 83 #define SROM_CLK_WRITE(data, ioaddr) do { \ 84 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \ 85 udelay(5); \ 86 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \ 87 udelay(5); \ 88 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \ 89 udelay(5); \ 90 } while (0) 91 92 /* Structure/enum declaration */ 93 94 struct tx_desc { 95 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */ 96 char *tx_buf_ptr; /* Data for us */ 97 struct tx_desc *next_tx_desc; 98 }; 99 100 struct rx_desc { 101 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */ 102 char *rx_buf_ptr; /* Data for us */ 103 struct rx_desc *next_rx_desc; 104 }; 105 106 struct uli526x_board_info { 107 u32 chip_id; /* Chip vendor/Device ID */ 108 pci_dev_t pdev; 109 110 long ioaddr; /* I/O base address */ 111 u32 cr0_data; 112 u32 cr5_data; 113 u32 cr6_data; 114 u32 cr7_data; 115 u32 cr15_data; 116 117 /* pointer for memory physical address */ 118 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */ 119 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */ 120 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */ 121 dma_addr_t first_tx_desc_dma; 122 dma_addr_t first_rx_desc_dma; 123 124 /* descriptor pointer */ 125 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */ 126 unsigned char *buf_pool_start; /* Tx buffer pool align dword */ 127 unsigned char *desc_pool_ptr; /* descriptor pool memory */ 128 struct tx_desc *first_tx_desc; 129 struct tx_desc *tx_insert_ptr; 130 struct tx_desc *tx_remove_ptr; 131 struct rx_desc *first_rx_desc; 132 struct rx_desc *rx_ready_ptr; /* packet come pointer */ 133 unsigned long tx_packet_cnt; /* transmitted packet count */ 134 135 u16 PHY_reg4; /* Saved Phyxcer register 4 value */ 136 137 u8 media_mode; /* user specify media mode */ 138 u8 op_mode; /* real work dedia mode */ 139 u8 phy_addr; 140 141 /* NIC SROM data */ 142 unsigned char srom[128]; 143 }; 144 145 enum uli526x_offsets { 146 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, 147 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, 148 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70, 149 DCR15 = 0x78 150 }; 151 152 enum uli526x_CR6_bits { 153 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, 154 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, 155 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000 156 }; 157 158 /* Global variable declaration -- */ 159 160 static unsigned char uli526x_media_mode = ULI526X_AUTO; 161 162 static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20] 163 __attribute__ ((aligned(32))); 164 static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4]; 165 166 /* For module input parameter */ 167 static int mode = 8; 168 169 /* function declaration -- */ 170 static int uli526x_start_xmit(struct eth_device *dev, 171 volatile void *packet, int length); 172 static const struct ethtool_ops netdev_ethtool_ops; 173 static u16 read_srom_word(long, int); 174 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long); 175 static void allocate_rx_buffer(struct uli526x_board_info *); 176 static void update_cr6(u32, unsigned long); 177 static u16 phy_read(unsigned long, u8, u8, u32); 178 static u16 phy_readby_cr10(unsigned long, u8, u8); 179 static void phy_write(unsigned long, u8, u8, u16, u32); 180 static void phy_writeby_cr10(unsigned long, u8, u8, u16); 181 static void phy_write_1bit(unsigned long, u32, u32); 182 static u16 phy_read_1bit(unsigned long, u32); 183 static int uli526x_rx_packet(struct eth_device *); 184 static void uli526x_free_tx_pkt(struct eth_device *, 185 struct uli526x_board_info *); 186 static void uli526x_reuse_buf(struct rx_desc *); 187 static void uli526x_init(struct eth_device *); 188 static void uli526x_set_phyxcer(struct uli526x_board_info *); 189 190 191 static int uli526x_init_one(struct eth_device *, bd_t *); 192 static void uli526x_disable(struct eth_device *); 193 static void set_mac_addr(struct eth_device *); 194 195 static struct pci_device_id uli526x_pci_tbl[] = { 196 { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */ 197 { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */ 198 {} 199 }; 200 201 /* ULI526X network board routine */ 202 203 /* 204 * Search ULI526X board, register it 205 */ 206 207 int uli526x_initialize(bd_t *bis) 208 { 209 pci_dev_t devno; 210 int card_number = 0; 211 struct eth_device *dev; 212 struct uli526x_board_info *db; /* board information structure */ 213 214 u32 iobase; 215 int idx = 0; 216 217 while (1) { 218 /* Find PCI device */ 219 devno = pci_find_devices(uli526x_pci_tbl, idx++); 220 if (devno < 0) 221 break; 222 223 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 224 iobase &= ~0xf; 225 226 dev = (struct eth_device *)malloc(sizeof *dev); 227 sprintf(dev->name, "uli526x#%d\n", card_number); 228 db = (struct uli526x_board_info *) 229 malloc(sizeof(struct uli526x_board_info)); 230 231 dev->priv = db; 232 db->pdev = devno; 233 dev->iobase = iobase; 234 235 dev->init = uli526x_init_one; 236 dev->halt = uli526x_disable; 237 dev->send = uli526x_start_xmit; 238 dev->recv = uli526x_rx_packet; 239 240 /* init db */ 241 db->ioaddr = dev->iobase; 242 /* get chip id */ 243 244 pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id); 245 #ifdef DEBUG 246 printf("uli526x: uli526x @0x%x\n", iobase); 247 printf("uli526x: chip_id%x\n", db->chip_id); 248 #endif 249 eth_register(dev); 250 card_number++; 251 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); 252 udelay(10 * 1000); 253 } 254 return card_number; 255 } 256 257 static int uli526x_init_one(struct eth_device *dev, bd_t *bis) 258 { 259 260 struct uli526x_board_info *db = dev->priv; 261 int i; 262 263 switch (mode) { 264 case ULI526X_10MHF: 265 case ULI526X_100MHF: 266 case ULI526X_10MFD: 267 case ULI526X_100MFD: 268 uli526x_media_mode = mode; 269 break; 270 default: 271 uli526x_media_mode = ULI526X_AUTO; 272 break; 273 } 274 275 /* Allocate Tx/Rx descriptor memory */ 276 db->desc_pool_ptr = (uchar *)&desc_pool_array[0]; 277 db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0]; 278 if (db->desc_pool_ptr == NULL) 279 return -1; 280 281 db->buf_pool_ptr = (uchar *)&buf_pool[0]; 282 db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0]; 283 if (db->buf_pool_ptr == NULL) 284 return -1; 285 286 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; 287 db->first_tx_desc_dma = db->desc_pool_dma_ptr; 288 289 db->buf_pool_start = db->buf_pool_ptr; 290 db->buf_pool_dma_start = db->buf_pool_dma_ptr; 291 292 #ifdef DEBUG 293 printf("%s(): db->ioaddr= 0x%x\n", 294 __FUNCTION__, db->ioaddr); 295 printf("%s(): media_mode= 0x%x\n", 296 __FUNCTION__, uli526x_media_mode); 297 printf("%s(): db->desc_pool_ptr= 0x%x\n", 298 __FUNCTION__, db->desc_pool_ptr); 299 printf("%s(): db->desc_pool_dma_ptr= 0x%x\n", 300 __FUNCTION__, db->desc_pool_dma_ptr); 301 printf("%s(): db->buf_pool_ptr= 0x%x\n", 302 __FUNCTION__, db->buf_pool_ptr); 303 printf("%s(): db->buf_pool_dma_ptr= 0x%x\n", 304 __FUNCTION__, db->buf_pool_dma_ptr); 305 #endif 306 307 /* read 64 word srom data */ 308 for (i = 0; i < 64; i++) 309 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, 310 i)); 311 312 /* Set Node address */ 313 if (((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) 314 /* SROM absent, so write MAC address to ID Table */ 315 set_mac_addr(dev); 316 else { /*Exist SROM*/ 317 for (i = 0; i < 6; i++) 318 dev->enetaddr[i] = db->srom[20 + i]; 319 } 320 #ifdef DEBUG 321 for (i = 0; i < 6; i++) 322 printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]); 323 #endif 324 db->PHY_reg4 = 0x1e0; 325 326 /* system variable init */ 327 db->cr6_data = CR6_DEFAULT ; 328 db->cr6_data |= ULI526X_TXTH_256; 329 db->cr0_data = CR0_DEFAULT; 330 uli526x_init(dev); 331 return 0; 332 } 333 334 static void uli526x_disable(struct eth_device *dev) 335 { 336 #ifdef DEBUG 337 printf("uli526x_disable\n"); 338 #endif 339 struct uli526x_board_info *db = dev->priv; 340 341 if (!((inl(db->ioaddr + DCR12)) & 0x8)) { 342 /* Reset & stop ULI526X board */ 343 outl(ULI526X_RESET, db->ioaddr + DCR0); 344 udelay(5); 345 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); 346 347 /* reset the board */ 348 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */ 349 update_cr6(db->cr6_data, dev->iobase); 350 outl(0, dev->iobase + DCR7); /* Disable Interrupt */ 351 outl(inl(dev->iobase + DCR5), dev->iobase + DCR5); 352 } 353 } 354 355 /* Initialize ULI526X board 356 * Reset ULI526X board 357 * Initialize TX/Rx descriptor chain structure 358 * Send the set-up frame 359 * Enable Tx/Rx machine 360 */ 361 362 static void uli526x_init(struct eth_device *dev) 363 { 364 365 struct uli526x_board_info *db = dev->priv; 366 u8 phy_tmp; 367 u16 phy_value; 368 u16 phy_reg_reset; 369 370 /* Reset M526x MAC controller */ 371 outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */ 372 udelay(100); 373 outl(db->cr0_data, db->ioaddr + DCR0); 374 udelay(5); 375 376 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */ 377 db->phy_addr = 1; 378 db->tx_packet_cnt = 0; 379 for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) { 380 /* peer add */ 381 phy_value = phy_read(db->ioaddr, phy_tmp, 3, db->chip_id); 382 if (phy_value != 0xffff && phy_value != 0) { 383 db->phy_addr = phy_tmp; 384 break; 385 } 386 } 387 388 #ifdef DEBUG 389 printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr); 390 printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr); 391 #endif 392 if (phy_tmp == 32) 393 printf("Can not find the phy address!!!"); 394 395 /* Parser SROM and media mode */ 396 db->media_mode = uli526x_media_mode; 397 398 if (!(inl(db->ioaddr + DCR12) & 0x8)) { 399 /* Phyxcer capability setting */ 400 phy_reg_reset = phy_read(db->ioaddr, 401 db->phy_addr, 0, db->chip_id); 402 phy_reg_reset = (phy_reg_reset | 0x8000); 403 phy_write(db->ioaddr, db->phy_addr, 0, 404 phy_reg_reset, db->chip_id); 405 udelay(500); 406 407 /* Process Phyxcer Media Mode */ 408 uli526x_set_phyxcer(db); 409 } 410 /* Media Mode Process */ 411 if (!(db->media_mode & ULI526X_AUTO)) 412 db->op_mode = db->media_mode; /* Force Mode */ 413 414 /* Initialize Transmit/Receive decriptor and CR3/4 */ 415 uli526x_descriptor_init(db, db->ioaddr); 416 417 /* Init CR6 to program M526X operation */ 418 update_cr6(db->cr6_data, db->ioaddr); 419 420 /* Init CR7, interrupt active bit */ 421 db->cr7_data = CR7_DEFAULT; 422 outl(db->cr7_data, db->ioaddr + DCR7); 423 424 /* Init CR15, Tx jabber and Rx watchdog timer */ 425 outl(db->cr15_data, db->ioaddr + DCR15); 426 427 /* Enable ULI526X Tx/Rx function */ 428 db->cr6_data |= CR6_RXSC | CR6_TXSC; 429 update_cr6(db->cr6_data, db->ioaddr); 430 while (!(inl(db->ioaddr + DCR12) & 0x8)) 431 udelay(10); 432 } 433 434 /* 435 * Hardware start transmission. 436 * Send a packet to media from the upper layer. 437 */ 438 439 static int uli526x_start_xmit(struct eth_device *dev, 440 volatile void *packet, int length) 441 { 442 struct uli526x_board_info *db = dev->priv; 443 struct tx_desc *txptr; 444 unsigned int len = length; 445 /* Too large packet check */ 446 if (len > MAX_PACKET_SIZE) { 447 printf(": big packet = %d\n", len); 448 return 0; 449 } 450 451 /* No Tx resource check, it never happen nromally */ 452 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) { 453 printf("No Tx resource %ld\n", db->tx_packet_cnt); 454 return 0; 455 } 456 457 /* Disable NIC interrupt */ 458 outl(0, dev->iobase + DCR7); 459 460 /* transmit this packet */ 461 txptr = db->tx_insert_ptr; 462 memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length); 463 txptr->tdes1 = cpu_to_le32(0xe1000000 | length); 464 465 /* Point to next transmit free descriptor */ 466 db->tx_insert_ptr = txptr->next_tx_desc; 467 468 /* Transmit Packet Process */ 469 if ((db->tx_packet_cnt < TX_DESC_CNT)) { 470 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ 471 db->tx_packet_cnt++; /* Ready to send */ 472 outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */ 473 } 474 475 /* Got ULI526X status */ 476 db->cr5_data = inl(db->ioaddr + DCR5); 477 outl(db->cr5_data, db->ioaddr + DCR5); 478 479 #ifdef TX_DEBUG 480 printf("%s(): length = 0x%x\n", __FUNCTION__, length); 481 printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data); 482 #endif 483 484 outl(db->cr7_data, dev->iobase + DCR7); 485 uli526x_free_tx_pkt(dev, db); 486 487 return length; 488 } 489 490 /* 491 * Free TX resource after TX complete 492 */ 493 494 static void uli526x_free_tx_pkt(struct eth_device *dev, 495 struct uli526x_board_info *db) 496 { 497 struct tx_desc *txptr; 498 u32 tdes0; 499 500 txptr = db->tx_remove_ptr; 501 while (db->tx_packet_cnt) { 502 tdes0 = le32_to_cpu(txptr->tdes0); 503 /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */ 504 if (tdes0 & 0x80000000) 505 break; 506 507 /* A packet sent completed */ 508 db->tx_packet_cnt--; 509 510 if (tdes0 != 0x7fffffff) { 511 #ifdef TX_DEBUG 512 printf("%s()tdes0=%x\n", __FUNCTION__, tdes0); 513 #endif 514 if (tdes0 & TDES0_ERR_MASK) { 515 if (tdes0 & 0x0002) { /* UnderRun */ 516 if (!(db->cr6_data & CR6_SFT)) { 517 db->cr6_data = db->cr6_data | 518 CR6_SFT; 519 update_cr6(db->cr6_data, 520 db->ioaddr); 521 } 522 } 523 } 524 } 525 526 txptr = txptr->next_tx_desc; 527 }/* End of while */ 528 529 /* Update TX remove pointer to next */ 530 db->tx_remove_ptr = txptr; 531 } 532 533 534 /* 535 * Receive the come packet and pass to upper layer 536 */ 537 538 static int uli526x_rx_packet(struct eth_device *dev) 539 { 540 struct uli526x_board_info *db = dev->priv; 541 struct rx_desc *rxptr; 542 int rxlen = 0; 543 u32 rdes0; 544 545 rxptr = db->rx_ready_ptr; 546 547 rdes0 = le32_to_cpu(rxptr->rdes0); 548 #ifdef RX_DEBUG 549 printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0); 550 #endif 551 if (!(rdes0 & 0x80000000)) { /* packet owner check */ 552 if ((rdes0 & 0x300) != 0x300) { 553 /* A packet without First/Last flag */ 554 /* reuse this buf */ 555 printf("A packet without First/Last flag"); 556 uli526x_reuse_buf(rxptr); 557 } else { 558 /* A packet with First/Last flag */ 559 rxlen = ((rdes0 >> 16) & 0x3fff) - 4; 560 #ifdef RX_DEBUG 561 printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen); 562 #endif 563 /* error summary bit check */ 564 if (rdes0 & 0x8000) { 565 /* This is a error packet */ 566 printf("Eroor: rdes0: %lx\n", rdes0); 567 } 568 569 if (!(rdes0 & 0x8000) || 570 ((db->cr6_data & CR6_PM) && (rxlen > 6))) { 571 572 #ifdef RX_DEBUG 573 printf("%s(): rx_skb_ptr =%x\n", 574 __FUNCTION__, rxptr->rx_buf_ptr); 575 printf("%s(): rxlen =%x\n", 576 __FUNCTION__, rxlen); 577 578 printf("%s(): buf addr =%x\n", 579 __FUNCTION__, rxptr->rx_buf_ptr); 580 printf("%s(): rxlen =%x\n", 581 __FUNCTION__, rxlen); 582 int i; 583 for (i = 0; i < 0x20; i++) 584 printf("%s(): data[%x] =%x\n", 585 __FUNCTION__, i, rxptr->rx_buf_ptr[i]); 586 #endif 587 588 NetReceive((uchar *)rxptr->rx_buf_ptr, rxlen); 589 uli526x_reuse_buf(rxptr); 590 591 } else { 592 /* Reuse SKB buffer when the packet is error */ 593 printf("Reuse buffer, rdes0"); 594 uli526x_reuse_buf(rxptr); 595 } 596 } 597 598 rxptr = rxptr->next_rx_desc; 599 } 600 601 db->rx_ready_ptr = rxptr; 602 return rxlen; 603 } 604 605 /* 606 * Reuse the RX buffer 607 */ 608 609 static void uli526x_reuse_buf(struct rx_desc *rxptr) 610 { 611 612 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) 613 rxptr->rdes0 = cpu_to_le32(0x80000000); 614 else 615 printf("Buffer reuse method error"); 616 } 617 /* 618 * Initialize transmit/Receive descriptor 619 * Using Chain structure, and allocate Tx/Rx buffer 620 */ 621 622 static void uli526x_descriptor_init(struct uli526x_board_info *db, 623 unsigned long ioaddr) 624 { 625 struct tx_desc *tmp_tx; 626 struct rx_desc *tmp_rx; 627 unsigned char *tmp_buf; 628 dma_addr_t tmp_tx_dma, tmp_rx_dma; 629 dma_addr_t tmp_buf_dma; 630 int i; 631 /* tx descriptor start pointer */ 632 db->tx_insert_ptr = db->first_tx_desc; 633 db->tx_remove_ptr = db->first_tx_desc; 634 635 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */ 636 637 /* rx descriptor start pointer */ 638 db->first_rx_desc = (void *)db->first_tx_desc + 639 sizeof(struct tx_desc) * TX_DESC_CNT; 640 db->first_rx_desc_dma = db->first_tx_desc_dma + 641 sizeof(struct tx_desc) * TX_DESC_CNT; 642 db->rx_ready_ptr = db->first_rx_desc; 643 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */ 644 #ifdef DEBUG 645 printf("%s(): db->first_tx_desc= 0x%x\n", 646 __FUNCTION__, db->first_tx_desc); 647 printf("%s(): db->first_rx_desc_dma= 0x%x\n", 648 __FUNCTION__, db->first_rx_desc_dma); 649 #endif 650 /* Init Transmit chain */ 651 tmp_buf = db->buf_pool_start; 652 tmp_buf_dma = db->buf_pool_dma_start; 653 tmp_tx_dma = db->first_tx_desc_dma; 654 for (tmp_tx = db->first_tx_desc, i = 0; 655 i < TX_DESC_CNT; i++, tmp_tx++) { 656 tmp_tx->tx_buf_ptr = (char *)tmp_buf; 657 tmp_tx->tdes0 = cpu_to_le32(0); 658 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */ 659 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma); 660 tmp_tx_dma += sizeof(struct tx_desc); 661 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma); 662 tmp_tx->next_tx_desc = tmp_tx + 1; 663 tmp_buf = tmp_buf + TX_BUF_ALLOC; 664 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC; 665 } 666 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma); 667 tmp_tx->next_tx_desc = db->first_tx_desc; 668 669 /* Init Receive descriptor chain */ 670 tmp_rx_dma = db->first_rx_desc_dma; 671 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; 672 i++, tmp_rx++) { 673 tmp_rx->rdes0 = cpu_to_le32(0); 674 tmp_rx->rdes1 = cpu_to_le32(0x01000600); 675 tmp_rx_dma += sizeof(struct rx_desc); 676 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma); 677 tmp_rx->next_rx_desc = tmp_rx + 1; 678 } 679 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma); 680 tmp_rx->next_rx_desc = db->first_rx_desc; 681 682 /* pre-allocate Rx buffer */ 683 allocate_rx_buffer(db); 684 } 685 686 /* 687 * Update CR6 value 688 * Firstly stop ULI526X, then written value and start 689 */ 690 691 static void update_cr6(u32 cr6_data, unsigned long ioaddr) 692 { 693 694 outl(cr6_data, ioaddr + DCR6); 695 udelay(5); 696 } 697 698 /* 699 * Allocate rx buffer, 700 */ 701 702 static void allocate_rx_buffer(struct uli526x_board_info *db) 703 { 704 int index; 705 struct rx_desc *rxptr; 706 rxptr = db->first_rx_desc; 707 u32 addr; 708 709 for (index = 0; index < RX_DESC_CNT; index++) { 710 addr = (u32)NetRxPackets[index]; 711 addr += (16 - (addr & 15)); 712 rxptr->rx_buf_ptr = (char *) addr; 713 rxptr->rdes2 = cpu_to_le32(addr); 714 rxptr->rdes0 = cpu_to_le32(0x80000000); 715 #ifdef DEBUG 716 printf("%s(): Number 0x%x:\n", __FUNCTION__, index); 717 printf("%s(): addr 0x%x:\n", __FUNCTION__, addr); 718 printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr); 719 printf("%s(): rxptr buf address = 0x%x\n", \ 720 __FUNCTION__, rxptr->rx_buf_ptr); 721 printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2); 722 #endif 723 rxptr = rxptr->next_rx_desc; 724 } 725 } 726 727 /* 728 * Read one word data from the serial ROM 729 */ 730 731 static u16 read_srom_word(long ioaddr, int offset) 732 { 733 int i; 734 u16 srom_data = 0; 735 long cr9_ioaddr = ioaddr + DCR9; 736 737 outl(CR9_SROM_READ, cr9_ioaddr); 738 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); 739 740 /* Send the Read Command 110b */ 741 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); 742 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); 743 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr); 744 745 /* Send the offset */ 746 for (i = 5; i >= 0; i--) { 747 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0; 748 SROM_CLK_WRITE(srom_data, cr9_ioaddr); 749 } 750 751 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); 752 753 for (i = 16; i > 0; i--) { 754 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr); 755 udelay(5); 756 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) 757 ? 1 : 0); 758 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); 759 udelay(5); 760 } 761 762 outl(CR9_SROM_READ, cr9_ioaddr); 763 return srom_data; 764 } 765 766 /* 767 * Set 10/100 phyxcer capability 768 * AUTO mode : phyxcer register4 is NIC capability 769 * Force mode: phyxcer register4 is the force media 770 */ 771 772 static void uli526x_set_phyxcer(struct uli526x_board_info *db) 773 { 774 u16 phy_reg; 775 776 /* Phyxcer capability setting */ 777 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0; 778 779 if (db->media_mode & ULI526X_AUTO) { 780 /* AUTO Mode */ 781 phy_reg |= db->PHY_reg4; 782 } else { 783 /* Force Mode */ 784 switch (db->media_mode) { 785 case ULI526X_10MHF: phy_reg |= 0x20; break; 786 case ULI526X_10MFD: phy_reg |= 0x40; break; 787 case ULI526X_100MHF: phy_reg |= 0x80; break; 788 case ULI526X_100MFD: phy_reg |= 0x100; break; 789 } 790 791 } 792 793 /* Write new capability to Phyxcer Reg4 */ 794 if (!(phy_reg & 0x01e0)) { 795 phy_reg |= db->PHY_reg4; 796 db->media_mode |= ULI526X_AUTO; 797 } 798 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); 799 800 /* Restart Auto-Negotiation */ 801 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); 802 udelay(50); 803 } 804 805 /* 806 * Write a word to Phy register 807 */ 808 809 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, 810 u16 phy_data, u32 chip_id) 811 { 812 u16 i; 813 unsigned long ioaddr; 814 815 if (chip_id == PCI_ULI5263_ID) { 816 phy_writeby_cr10(iobase, phy_addr, offset, phy_data); 817 return; 818 } 819 /* M5261/M5263 Chip */ 820 ioaddr = iobase + DCR9; 821 822 /* Send 33 synchronization clock to Phy controller */ 823 for (i = 0; i < 35; i++) 824 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 825 826 /* Send start command(01) to Phy */ 827 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); 828 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 829 830 /* Send write command(01) to Phy */ 831 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); 832 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 833 834 /* Send Phy address */ 835 for (i = 0x10; i > 0; i = i >> 1) 836 phy_write_1bit(ioaddr, phy_addr & i ? 837 PHY_DATA_1 : PHY_DATA_0, chip_id); 838 839 /* Send register address */ 840 for (i = 0x10; i > 0; i = i >> 1) 841 phy_write_1bit(ioaddr, offset & i ? 842 PHY_DATA_1 : PHY_DATA_0, chip_id); 843 844 /* written trasnition */ 845 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 846 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); 847 848 /* Write a word data to PHY controller */ 849 for (i = 0x8000; i > 0; i >>= 1) 850 phy_write_1bit(ioaddr, phy_data & i ? 851 PHY_DATA_1 : PHY_DATA_0, chip_id); 852 } 853 854 /* 855 * Read a word data from phy register 856 */ 857 858 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id) 859 { 860 int i; 861 u16 phy_data; 862 unsigned long ioaddr; 863 864 if (chip_id == PCI_ULI5263_ID) 865 return phy_readby_cr10(iobase, phy_addr, offset); 866 /* M5261/M5263 Chip */ 867 ioaddr = iobase + DCR9; 868 869 /* Send 33 synchronization clock to Phy controller */ 870 for (i = 0; i < 35; i++) 871 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 872 873 /* Send start command(01) to Phy */ 874 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); 875 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 876 877 /* Send read command(10) to Phy */ 878 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); 879 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); 880 881 /* Send Phy address */ 882 for (i = 0x10; i > 0; i = i >> 1) 883 phy_write_1bit(ioaddr, phy_addr & i ? 884 PHY_DATA_1 : PHY_DATA_0, chip_id); 885 886 /* Send register address */ 887 for (i = 0x10; i > 0; i = i >> 1) 888 phy_write_1bit(ioaddr, offset & i ? 889 PHY_DATA_1 : PHY_DATA_0, chip_id); 890 891 /* Skip transition state */ 892 phy_read_1bit(ioaddr, chip_id); 893 894 /* read 16bit data */ 895 for (phy_data = 0, i = 0; i < 16; i++) { 896 phy_data <<= 1; 897 phy_data |= phy_read_1bit(ioaddr, chip_id); 898 } 899 900 return phy_data; 901 } 902 903 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset) 904 { 905 unsigned long ioaddr, cr10_value; 906 907 ioaddr = iobase + DCR10; 908 cr10_value = phy_addr; 909 cr10_value = (cr10_value<<5) + offset; 910 cr10_value = (cr10_value<<16) + 0x08000000; 911 outl(cr10_value, ioaddr); 912 udelay(1); 913 while (1) { 914 cr10_value = inl(ioaddr); 915 if (cr10_value & 0x10000000) 916 break; 917 } 918 return (cr10_value&0x0ffff); 919 } 920 921 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, 922 u8 offset, u16 phy_data) 923 { 924 unsigned long ioaddr, cr10_value; 925 926 ioaddr = iobase + DCR10; 927 cr10_value = phy_addr; 928 cr10_value = (cr10_value<<5) + offset; 929 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data; 930 outl(cr10_value, ioaddr); 931 udelay(1); 932 } 933 /* 934 * Write one bit data to Phy Controller 935 */ 936 937 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id) 938 { 939 outl(phy_data , ioaddr); /* MII Clock Low */ 940 udelay(1); 941 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ 942 udelay(1); 943 outl(phy_data , ioaddr); /* MII Clock Low */ 944 udelay(1); 945 } 946 947 /* 948 * Read one bit phy data from PHY controller 949 */ 950 951 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id) 952 { 953 u16 phy_data; 954 955 outl(0x50000 , ioaddr); 956 udelay(1); 957 phy_data = (inl(ioaddr) >> 19) & 0x1; 958 outl(0x40000 , ioaddr); 959 udelay(1); 960 961 return phy_data; 962 } 963 964 /* 965 * Set MAC address to ID Table 966 */ 967 968 static void set_mac_addr(struct eth_device *dev) 969 { 970 int i; 971 u16 addr; 972 struct uli526x_board_info *db = dev->priv; 973 outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */ 974 /* Reset dianostic pointer port */ 975 outl(0x1c0, db->ioaddr + DCR13); 976 outl(0, db->ioaddr + DCR14); /* Clear reset port */ 977 outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */ 978 outl(0, db->ioaddr + DCR14); /* Clear reset port */ 979 outl(0, db->ioaddr + DCR13); /* Clear CR13 */ 980 /* Select ID Table access port */ 981 outl(0x1b0, db->ioaddr + DCR13); 982 /* Read MAC address from CR14 */ 983 for (i = 0; i < 3; i++) { 984 addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8); 985 outl(addr, db->ioaddr + DCR14); 986 } 987 /* write end */ 988 outl(0, db->ioaddr + DCR13); /* Clear CR13 */ 989 outl(0, db->ioaddr + DCR0); /* Clear CR0 */ 990 udelay(10); 991 return; 992 } 993