1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004, 2007 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 20 #if defined(CONFIG_TSEC_ENET) 21 #include "tsec.h" 22 #include "miiphy.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define TX_BUF_CNT 2 27 28 static uint rxIdx; /* index of the current RX buffer */ 29 static uint txIdx; /* index of the current TX buffer */ 30 31 typedef volatile struct rtxbd { 32 txbd8_t txbd[TX_BUF_CNT]; 33 rxbd8_t rxbd[PKTBUFSRX]; 34 } RTXBD; 35 36 struct tsec_info_struct { 37 unsigned int phyaddr; 38 u32 flags; 39 unsigned int phyregidx; 40 }; 41 42 /* The tsec_info structure contains 3 values which the 43 * driver uses to determine how to operate a given ethernet 44 * device. The information needed is: 45 * phyaddr - The address of the PHY which is attached to 46 * the given device. 47 * 48 * flags - This variable indicates whether the device 49 * supports gigabit speed ethernet, and whether it should be 50 * in reduced mode. 51 * 52 * phyregidx - This variable specifies which ethernet device 53 * controls the MII Management registers which are connected 54 * to the PHY. For now, only TSEC1 (index 0) has 55 * access to the PHYs, so all of the entries have "0". 56 * 57 * The values specified in the table are taken from the board's 58 * config file in include/configs/. When implementing a new 59 * board with ethernet capability, it is necessary to define: 60 * TSECn_PHY_ADDR 61 * TSECn_PHYIDX 62 * 63 * for n = 1,2,3, etc. And for FEC: 64 * FEC_PHY_ADDR 65 * FEC_PHYIDX 66 */ 67 static struct tsec_info_struct tsec_info[] = { 68 #ifdef CONFIG_TSEC1 69 {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX}, 70 #else 71 {0, 0, 0}, 72 #endif 73 #ifdef CONFIG_TSEC2 74 {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX}, 75 #else 76 {0, 0, 0}, 77 #endif 78 #ifdef CONFIG_MPC85XX_FEC 79 {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX}, 80 #else 81 #ifdef CONFIG_TSEC3 82 {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX}, 83 #else 84 {0, 0, 0}, 85 #endif 86 #ifdef CONFIG_TSEC4 87 {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX}, 88 #else 89 {0, 0, 0}, 90 #endif /* CONFIG_TSEC4 */ 91 #endif /* CONFIG_MPC85XX_FEC */ 92 }; 93 94 #define MAXCONTROLLERS (4) 95 96 static int relocated = 0; 97 98 static struct tsec_private *privlist[MAXCONTROLLERS]; 99 100 #ifdef __GNUC__ 101 static RTXBD rtx __attribute__ ((aligned(8))); 102 #else 103 #error "rtx must be 64-bit aligned" 104 #endif 105 106 static int tsec_send(struct eth_device *dev, 107 volatile void *packet, int length); 108 static int tsec_recv(struct eth_device *dev); 109 static int tsec_init(struct eth_device *dev, bd_t * bd); 110 static void tsec_halt(struct eth_device *dev); 111 static void init_registers(volatile tsec_t * regs); 112 static void startup_tsec(struct eth_device *dev); 113 static int init_phy(struct eth_device *dev); 114 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 115 uint read_phy_reg(struct tsec_private *priv, uint regnum); 116 struct phy_info *get_phy_info(struct eth_device *dev); 117 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 118 static void adjust_link(struct eth_device *dev); 119 static void relocate_cmds(void); 120 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 121 && !defined(BITBANGMII) 122 static int tsec_miiphy_write(char *devname, unsigned char addr, 123 unsigned char reg, unsigned short value); 124 static int tsec_miiphy_read(char *devname, unsigned char addr, 125 unsigned char reg, unsigned short *value); 126 #endif 127 #ifdef CONFIG_MCAST_TFTP 128 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 129 #endif 130 131 /* Initialize device structure. Returns success if PHY 132 * initialization succeeded (i.e. if it recognizes the PHY) 133 */ 134 int tsec_initialize(bd_t * bis, int index, char *devname) 135 { 136 struct eth_device *dev; 137 int i; 138 struct tsec_private *priv; 139 140 dev = (struct eth_device *)malloc(sizeof *dev); 141 142 if (NULL == dev) 143 return 0; 144 145 memset(dev, 0, sizeof *dev); 146 147 priv = (struct tsec_private *)malloc(sizeof(*priv)); 148 149 if (NULL == priv) 150 return 0; 151 152 privlist[index] = priv; 153 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE); 154 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR + 155 tsec_info[index].phyregidx * 156 TSEC_SIZE); 157 158 priv->phyaddr = tsec_info[index].phyaddr; 159 priv->flags = tsec_info[index].flags; 160 161 sprintf(dev->name, devname); 162 dev->iobase = 0; 163 dev->priv = priv; 164 dev->init = tsec_init; 165 dev->halt = tsec_halt; 166 dev->send = tsec_send; 167 dev->recv = tsec_recv; 168 #ifdef CONFIG_MCAST_TFTP 169 dev->mcast = tsec_mcast_addr; 170 #endif 171 172 /* Tell u-boot to get the addr from the env */ 173 for (i = 0; i < 6; i++) 174 dev->enetaddr[i] = 0; 175 176 eth_register(dev); 177 178 /* Reset the MAC */ 179 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 180 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 181 182 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 183 && !defined(BITBANGMII) 184 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 185 #endif 186 187 /* Try to initialize PHY here, and return */ 188 return init_phy(dev); 189 } 190 191 /* Initializes data structures and registers for the controller, 192 * and brings the interface up. Returns the link status, meaning 193 * that it returns success if the link is up, failure otherwise. 194 * This allows u-boot to find the first active controller. 195 */ 196 int tsec_init(struct eth_device *dev, bd_t * bd) 197 { 198 uint tempval; 199 char tmpbuf[MAC_ADDR_LEN]; 200 int i; 201 struct tsec_private *priv = (struct tsec_private *)dev->priv; 202 volatile tsec_t *regs = priv->regs; 203 204 /* Make sure the controller is stopped */ 205 tsec_halt(dev); 206 207 /* Init MACCFG2. Defaults to GMII */ 208 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 209 210 /* Init ECNTRL */ 211 regs->ecntrl = ECNTRL_INIT_SETTINGS; 212 213 /* Copy the station address into the address registers. 214 * Backwards, because little endian MACS are dumb */ 215 for (i = 0; i < MAC_ADDR_LEN; i++) { 216 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 217 } 218 regs->macstnaddr1 = *((uint *) (tmpbuf)); 219 220 tempval = *((uint *) (tmpbuf + 4)); 221 222 regs->macstnaddr2 = tempval; 223 224 /* reset the indices to zero */ 225 rxIdx = 0; 226 txIdx = 0; 227 228 /* Clear out (for the most part) the other registers */ 229 init_registers(regs); 230 231 /* Ready the device for tx/rx */ 232 startup_tsec(dev); 233 234 /* If there's no link, fail */ 235 return (priv->link ? 0 : -1); 236 237 } 238 239 /* Write value to the device's PHY through the registers 240 * specified in priv, modifying the register specified in regnum. 241 * It will wait for the write to be done (or for a timeout to 242 * expire) before exiting 243 */ 244 void write_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum, uint value) 245 { 246 volatile tsec_t *regbase = priv->phyregs; 247 int timeout = 1000000; 248 249 regbase->miimadd = (phyid << 8) | regnum; 250 regbase->miimcon = value; 251 asm("sync"); 252 253 timeout = 1000000; 254 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 255 } 256 257 /* #define to provide old write_phy_reg functionality without duplicating code */ 258 #define write_phy_reg(priv, regnum, value) write_any_phy_reg(priv,priv->phyaddr,regnum,value) 259 260 /* Reads register regnum on the device's PHY through the 261 * registers specified in priv. It lowers and raises the read 262 * command, and waits for the data to become valid (miimind 263 * notvalid bit cleared), and the bus to cease activity (miimind 264 * busy bit cleared), and then returns the value 265 */ 266 uint read_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum) 267 { 268 uint value; 269 volatile tsec_t *regbase = priv->phyregs; 270 271 /* Put the address of the phy, and the register 272 * number into MIIMADD */ 273 regbase->miimadd = (phyid << 8) | regnum; 274 275 /* Clear the command register, and wait */ 276 regbase->miimcom = 0; 277 asm("sync"); 278 279 /* Initiate a read command, and wait */ 280 regbase->miimcom = MIIM_READ_COMMAND; 281 asm("sync"); 282 283 /* Wait for the the indication that the read is done */ 284 while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 285 286 /* Grab the value read from the PHY */ 287 value = regbase->miimstat; 288 289 return value; 290 } 291 292 /* #define to provide old read_phy_reg functionality without duplicating code */ 293 #define read_phy_reg(priv,regnum) read_any_phy_reg(priv,priv->phyaddr,regnum) 294 295 /* Discover which PHY is attached to the device, and configure it 296 * properly. If the PHY is not recognized, then return 0 297 * (failure). Otherwise, return 1 298 */ 299 static int init_phy(struct eth_device *dev) 300 { 301 struct tsec_private *priv = (struct tsec_private *)dev->priv; 302 struct phy_info *curphy; 303 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); 304 305 /* Assign a Physical address to the TBI */ 306 regs->tbipa = CFG_TBIPA_VALUE; 307 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); 308 regs->tbipa = CFG_TBIPA_VALUE; 309 asm("sync"); 310 311 /* Reset MII (due to new addresses) */ 312 priv->phyregs->miimcfg = MIIMCFG_RESET; 313 asm("sync"); 314 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 315 asm("sync"); 316 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 317 318 if (0 == relocated) 319 relocate_cmds(); 320 321 /* Get the cmd structure corresponding to the attached 322 * PHY */ 323 curphy = get_phy_info(dev); 324 325 if (curphy == NULL) { 326 priv->phyinfo = NULL; 327 printf("%s: No PHY found\n", dev->name); 328 329 return 0; 330 } 331 332 priv->phyinfo = curphy; 333 334 phy_run_commands(priv, priv->phyinfo->config); 335 336 return 1; 337 } 338 339 /* 340 * Returns which value to write to the control register. 341 * For 10/100, the value is slightly different 342 */ 343 uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 344 { 345 if (priv->flags & TSEC_GIGABIT) 346 return MIIM_CONTROL_INIT; 347 else 348 return MIIM_CR_INIT; 349 } 350 351 /* Parse the status register for link, and then do 352 * auto-negotiation 353 */ 354 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 355 { 356 /* 357 * Wait if the link is up, and autonegotiation is in progress 358 * (ie - we're capable and it's not done) 359 */ 360 mii_reg = read_phy_reg(priv, MIIM_STATUS); 361 if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) 362 && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 363 int i = 0; 364 365 puts("Waiting for PHY auto negotiation to complete"); 366 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 367 /* 368 * Timeout reached ? 369 */ 370 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 371 puts(" TIMEOUT !\n"); 372 priv->link = 0; 373 return 0; 374 } 375 376 if ((i++ % 1000) == 0) { 377 putc('.'); 378 } 379 udelay(1000); /* 1 ms */ 380 mii_reg = read_phy_reg(priv, MIIM_STATUS); 381 } 382 puts(" done\n"); 383 priv->link = 1; 384 udelay(500000); /* another 500 ms (results in faster booting) */ 385 } else { 386 if (mii_reg & MIIM_STATUS_LINK) 387 priv->link = 1; 388 else 389 priv->link = 0; 390 } 391 392 return 0; 393 } 394 395 /* Generic function which updates the speed and duplex. If 396 * autonegotiation is enabled, it uses the AND of the link 397 * partner's advertised capabilities and our advertised 398 * capabilities. If autonegotiation is disabled, we use the 399 * appropriate bits in the control register. 400 * 401 * Stolen from Linux's mii.c and phy_device.c 402 */ 403 uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 404 { 405 /* We're using autonegotiation */ 406 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 407 uint lpa = 0; 408 uint gblpa = 0; 409 410 /* Check for gigabit capability */ 411 if (mii_reg & PHY_BMSR_EXT) { 412 /* We want a list of states supported by 413 * both PHYs in the link 414 */ 415 gblpa = read_phy_reg(priv, PHY_1000BTSR); 416 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 417 } 418 419 /* Set the baseline so we only have to set them 420 * if they're different 421 */ 422 priv->speed = 10; 423 priv->duplexity = 0; 424 425 /* Check the gigabit fields */ 426 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 427 priv->speed = 1000; 428 429 if (gblpa & PHY_1000BTSR_1000FD) 430 priv->duplexity = 1; 431 432 /* We're done! */ 433 return 0; 434 } 435 436 lpa = read_phy_reg(priv, PHY_ANAR); 437 lpa &= read_phy_reg(priv, PHY_ANLPAR); 438 439 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 440 priv->speed = 100; 441 442 if (lpa & PHY_ANLPAR_TXFD) 443 priv->duplexity = 1; 444 445 } else if (lpa & PHY_ANLPAR_10FD) 446 priv->duplexity = 1; 447 } else { 448 uint bmcr = read_phy_reg(priv, PHY_BMCR); 449 450 priv->speed = 10; 451 priv->duplexity = 0; 452 453 if (bmcr & PHY_BMCR_DPLX) 454 priv->duplexity = 1; 455 456 if (bmcr & PHY_BMCR_1000_MBPS) 457 priv->speed = 1000; 458 else if (bmcr & PHY_BMCR_100_MBPS) 459 priv->speed = 100; 460 } 461 462 return 0; 463 } 464 465 /* 466 * Parse the BCM54xx status register for speed and duplex information. 467 * The linux sungem_phy has this information, but in a table format. 468 */ 469 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 470 { 471 472 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ 473 474 case 1: 475 printf("Enet starting in 10BT/HD\n"); 476 priv->duplexity = 0; 477 priv->speed = 10; 478 break; 479 480 case 2: 481 printf("Enet starting in 10BT/FD\n"); 482 priv->duplexity = 1; 483 priv->speed = 10; 484 break; 485 486 case 3: 487 printf("Enet starting in 100BT/HD\n"); 488 priv->duplexity = 0; 489 priv->speed = 100; 490 break; 491 492 case 5: 493 printf("Enet starting in 100BT/FD\n"); 494 priv->duplexity = 1; 495 priv->speed = 100; 496 break; 497 498 case 6: 499 printf("Enet starting in 1000BT/HD\n"); 500 priv->duplexity = 0; 501 priv->speed = 1000; 502 break; 503 504 case 7: 505 printf("Enet starting in 1000BT/FD\n"); 506 priv->duplexity = 1; 507 priv->speed = 1000; 508 break; 509 510 default: 511 printf("Auto-neg error, defaulting to 10BT/HD\n"); 512 priv->duplexity = 0; 513 priv->speed = 10; 514 break; 515 } 516 517 return 0; 518 519 } 520 /* Parse the 88E1011's status register for speed and duplex 521 * information 522 */ 523 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 524 { 525 uint speed; 526 527 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 528 529 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 530 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 531 int i = 0; 532 533 puts("Waiting for PHY realtime link"); 534 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 535 /* Timeout reached ? */ 536 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 537 puts(" TIMEOUT !\n"); 538 priv->link = 0; 539 break; 540 } 541 542 if ((i++ % 1000) == 0) { 543 putc('.'); 544 } 545 udelay(1000); /* 1 ms */ 546 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 547 } 548 puts(" done\n"); 549 udelay(500000); /* another 500 ms (results in faster booting) */ 550 } else { 551 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 552 priv->link = 1; 553 else 554 priv->link = 0; 555 } 556 557 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 558 priv->duplexity = 1; 559 else 560 priv->duplexity = 0; 561 562 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 563 564 switch (speed) { 565 case MIIM_88E1011_PHYSTAT_GBIT: 566 priv->speed = 1000; 567 break; 568 case MIIM_88E1011_PHYSTAT_100: 569 priv->speed = 100; 570 break; 571 default: 572 priv->speed = 10; 573 } 574 575 return 0; 576 } 577 578 /* Parse the RTL8211B's status register for speed and duplex 579 * information 580 */ 581 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 582 { 583 uint speed; 584 585 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 586 if ((mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) && 587 !(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 588 int i = 0; 589 590 puts("Waiting for PHY realtime link"); 591 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 592 /* Timeout reached ? */ 593 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 594 puts(" TIMEOUT !\n"); 595 priv->link = 0; 596 break; 597 } 598 599 if ((i++ % 1000) == 0) { 600 putc('.'); 601 } 602 udelay(1000); /* 1 ms */ 603 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 604 } 605 puts(" done\n"); 606 udelay(500000); /* another 500 ms (results in faster booting) */ 607 } else { 608 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 609 priv->link = 1; 610 else 611 priv->link = 0; 612 } 613 614 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 615 priv->duplexity = 1; 616 else 617 priv->duplexity = 0; 618 619 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 620 621 switch (speed) { 622 case MIIM_RTL8211B_PHYSTAT_GBIT: 623 priv->speed = 1000; 624 break; 625 case MIIM_RTL8211B_PHYSTAT_100: 626 priv->speed = 100; 627 break; 628 default: 629 priv->speed = 10; 630 } 631 632 return 0; 633 } 634 635 /* Parse the cis8201's status register for speed and duplex 636 * information 637 */ 638 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 639 { 640 uint speed; 641 642 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 643 priv->duplexity = 1; 644 else 645 priv->duplexity = 0; 646 647 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 648 switch (speed) { 649 case MIIM_CIS8201_AUXCONSTAT_GBIT: 650 priv->speed = 1000; 651 break; 652 case MIIM_CIS8201_AUXCONSTAT_100: 653 priv->speed = 100; 654 break; 655 default: 656 priv->speed = 10; 657 break; 658 } 659 660 return 0; 661 } 662 663 /* Parse the vsc8244's status register for speed and duplex 664 * information 665 */ 666 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 667 { 668 uint speed; 669 670 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 671 priv->duplexity = 1; 672 else 673 priv->duplexity = 0; 674 675 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 676 switch (speed) { 677 case MIIM_VSC8244_AUXCONSTAT_GBIT: 678 priv->speed = 1000; 679 break; 680 case MIIM_VSC8244_AUXCONSTAT_100: 681 priv->speed = 100; 682 break; 683 default: 684 priv->speed = 10; 685 break; 686 } 687 688 return 0; 689 } 690 691 /* Parse the DM9161's status register for speed and duplex 692 * information 693 */ 694 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 695 { 696 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 697 priv->speed = 100; 698 else 699 priv->speed = 10; 700 701 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 702 priv->duplexity = 1; 703 else 704 priv->duplexity = 0; 705 706 return 0; 707 } 708 709 /* 710 * Hack to write all 4 PHYs with the LED values 711 */ 712 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 713 { 714 uint phyid; 715 volatile tsec_t *regbase = priv->phyregs; 716 int timeout = 1000000; 717 718 for (phyid = 0; phyid < 4; phyid++) { 719 regbase->miimadd = (phyid << 8) | mii_reg; 720 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 721 asm("sync"); 722 723 timeout = 1000000; 724 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 725 } 726 727 return MIIM_CIS8204_SLEDCON_INIT; 728 } 729 730 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 731 { 732 if (priv->flags & TSEC_REDUCED) 733 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 734 else 735 return MIIM_CIS8204_EPHYCON_INIT; 736 } 737 738 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 739 { 740 uint mii_data = read_phy_reg(priv, mii_reg); 741 742 if (priv->flags & TSEC_REDUCED) 743 mii_data = (mii_data & 0xfff0) | 0x000b; 744 return mii_data; 745 } 746 747 /* Initialized required registers to appropriate values, zeroing 748 * those we don't care about (unless zero is bad, in which case, 749 * choose a more appropriate value) 750 */ 751 static void init_registers(volatile tsec_t * regs) 752 { 753 /* Clear IEVENT */ 754 regs->ievent = IEVENT_INIT_CLEAR; 755 756 regs->imask = IMASK_INIT_CLEAR; 757 758 regs->hash.iaddr0 = 0; 759 regs->hash.iaddr1 = 0; 760 regs->hash.iaddr2 = 0; 761 regs->hash.iaddr3 = 0; 762 regs->hash.iaddr4 = 0; 763 regs->hash.iaddr5 = 0; 764 regs->hash.iaddr6 = 0; 765 regs->hash.iaddr7 = 0; 766 767 regs->hash.gaddr0 = 0; 768 regs->hash.gaddr1 = 0; 769 regs->hash.gaddr2 = 0; 770 regs->hash.gaddr3 = 0; 771 regs->hash.gaddr4 = 0; 772 regs->hash.gaddr5 = 0; 773 regs->hash.gaddr6 = 0; 774 regs->hash.gaddr7 = 0; 775 776 regs->rctrl = 0x00000000; 777 778 /* Init RMON mib registers */ 779 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 780 781 regs->rmon.cam1 = 0xffffffff; 782 regs->rmon.cam2 = 0xffffffff; 783 784 regs->mrblr = MRBLR_INIT_SETTINGS; 785 786 regs->minflr = MINFLR_INIT_SETTINGS; 787 788 regs->attr = ATTR_INIT_SETTINGS; 789 regs->attreli = ATTRELI_INIT_SETTINGS; 790 791 } 792 793 /* Configure maccfg2 based on negotiated speed and duplex 794 * reported by PHY handling code 795 */ 796 static void adjust_link(struct eth_device *dev) 797 { 798 struct tsec_private *priv = (struct tsec_private *)dev->priv; 799 volatile tsec_t *regs = priv->regs; 800 801 if (priv->link) { 802 if (priv->duplexity != 0) 803 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 804 else 805 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 806 807 switch (priv->speed) { 808 case 1000: 809 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 810 | MACCFG2_GMII); 811 break; 812 case 100: 813 case 10: 814 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 815 | MACCFG2_MII); 816 817 /* Set R100 bit in all modes although 818 * it is only used in RGMII mode 819 */ 820 if (priv->speed == 100) 821 regs->ecntrl |= ECNTRL_R100; 822 else 823 regs->ecntrl &= ~(ECNTRL_R100); 824 break; 825 default: 826 printf("%s: Speed was bad\n", dev->name); 827 break; 828 } 829 830 printf("Speed: %d, %s duplex\n", priv->speed, 831 (priv->duplexity) ? "full" : "half"); 832 833 } else { 834 printf("%s: No link.\n", dev->name); 835 } 836 } 837 838 /* Set up the buffers and their descriptors, and bring up the 839 * interface 840 */ 841 static void startup_tsec(struct eth_device *dev) 842 { 843 int i; 844 struct tsec_private *priv = (struct tsec_private *)dev->priv; 845 volatile tsec_t *regs = priv->regs; 846 847 /* Point to the buffer descriptors */ 848 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 849 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 850 851 /* Initialize the Rx Buffer descriptors */ 852 for (i = 0; i < PKTBUFSRX; i++) { 853 rtx.rxbd[i].status = RXBD_EMPTY; 854 rtx.rxbd[i].length = 0; 855 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 856 } 857 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 858 859 /* Initialize the TX Buffer Descriptors */ 860 for (i = 0; i < TX_BUF_CNT; i++) { 861 rtx.txbd[i].status = 0; 862 rtx.txbd[i].length = 0; 863 rtx.txbd[i].bufPtr = 0; 864 } 865 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 866 867 /* Start up the PHY */ 868 if(priv->phyinfo) 869 phy_run_commands(priv, priv->phyinfo->startup); 870 871 adjust_link(dev); 872 873 /* Enable Transmit and Receive */ 874 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 875 876 /* Tell the DMA it is clear to go */ 877 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 878 regs->tstat = TSTAT_CLEAR_THALT; 879 regs->rstat = RSTAT_CLEAR_RHALT; 880 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 881 } 882 883 /* This returns the status bits of the device. The return value 884 * is never checked, and this is what the 8260 driver did, so we 885 * do the same. Presumably, this would be zero if there were no 886 * errors 887 */ 888 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 889 { 890 int i; 891 int result = 0; 892 struct tsec_private *priv = (struct tsec_private *)dev->priv; 893 volatile tsec_t *regs = priv->regs; 894 895 /* Find an empty buffer descriptor */ 896 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 897 if (i >= TOUT_LOOP) { 898 debug("%s: tsec: tx buffers full\n", dev->name); 899 return result; 900 } 901 } 902 903 rtx.txbd[txIdx].bufPtr = (uint) packet; 904 rtx.txbd[txIdx].length = length; 905 rtx.txbd[txIdx].status |= 906 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 907 908 /* Tell the DMA to go */ 909 regs->tstat = TSTAT_CLEAR_THALT; 910 911 /* Wait for buffer to be transmitted */ 912 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 913 if (i >= TOUT_LOOP) { 914 debug("%s: tsec: tx error\n", dev->name); 915 return result; 916 } 917 } 918 919 txIdx = (txIdx + 1) % TX_BUF_CNT; 920 result = rtx.txbd[txIdx].status & TXBD_STATS; 921 922 return result; 923 } 924 925 static int tsec_recv(struct eth_device *dev) 926 { 927 int length; 928 struct tsec_private *priv = (struct tsec_private *)dev->priv; 929 volatile tsec_t *regs = priv->regs; 930 931 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 932 933 length = rtx.rxbd[rxIdx].length; 934 935 /* Send the packet up if there were no errors */ 936 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 937 NetReceive(NetRxPackets[rxIdx], length - 4); 938 } else { 939 printf("Got error %x\n", 940 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 941 } 942 943 rtx.rxbd[rxIdx].length = 0; 944 945 /* Set the wrap bit if this is the last element in the list */ 946 rtx.rxbd[rxIdx].status = 947 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 948 949 rxIdx = (rxIdx + 1) % PKTBUFSRX; 950 } 951 952 if (regs->ievent & IEVENT_BSY) { 953 regs->ievent = IEVENT_BSY; 954 regs->rstat = RSTAT_CLEAR_RHALT; 955 } 956 957 return -1; 958 959 } 960 961 /* Stop the interface */ 962 static void tsec_halt(struct eth_device *dev) 963 { 964 struct tsec_private *priv = (struct tsec_private *)dev->priv; 965 volatile tsec_t *regs = priv->regs; 966 967 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 968 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 969 970 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; 971 972 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 973 974 /* Shut down the PHY, as needed */ 975 if(priv->phyinfo) 976 phy_run_commands(priv, priv->phyinfo->shutdown); 977 } 978 979 struct phy_info phy_info_M88E1149S = { 980 0x1410ca, 981 "Marvell 88E1149S", 982 4, 983 (struct phy_cmd[]){ /* config */ 984 /* Reset and configure the PHY */ 985 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 986 {0x1d, 0x1f, NULL}, 987 {0x1e, 0x200c, NULL}, 988 {0x1d, 0x5, NULL}, 989 {0x1e, 0x0, NULL}, 990 {0x1e, 0x100, NULL}, 991 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 992 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 993 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 994 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 995 {miim_end,} 996 }, 997 (struct phy_cmd[]){ /* startup */ 998 /* Status is read once to clear old link state */ 999 {MIIM_STATUS, miim_read, NULL}, 1000 /* Auto-negotiate */ 1001 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1002 /* Read the status */ 1003 {MIIM_88E1011_PHY_STATUS, miim_read, 1004 &mii_parse_88E1011_psr}, 1005 {miim_end,} 1006 }, 1007 (struct phy_cmd[]){ /* shutdown */ 1008 {miim_end,} 1009 }, 1010 }; 1011 1012 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 1013 struct phy_info phy_info_BCM5461S = { 1014 0x02060c1, /* 5461 ID */ 1015 "Broadcom BCM5461S", 1016 0, /* not clear to me what minor revisions we can shift away */ 1017 (struct phy_cmd[]) { /* config */ 1018 /* Reset and configure the PHY */ 1019 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1020 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1021 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1022 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1023 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1024 {miim_end,} 1025 }, 1026 (struct phy_cmd[]) { /* startup */ 1027 /* Status is read once to clear old link state */ 1028 {MIIM_STATUS, miim_read, NULL}, 1029 /* Auto-negotiate */ 1030 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1031 /* Read the status */ 1032 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1033 {miim_end,} 1034 }, 1035 (struct phy_cmd[]) { /* shutdown */ 1036 {miim_end,} 1037 }, 1038 }; 1039 1040 struct phy_info phy_info_BCM5464S = { 1041 0x02060b1, /* 5464 ID */ 1042 "Broadcom BCM5464S", 1043 0, /* not clear to me what minor revisions we can shift away */ 1044 (struct phy_cmd[]) { /* config */ 1045 /* Reset and configure the PHY */ 1046 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1047 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1048 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1049 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1050 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1051 {miim_end,} 1052 }, 1053 (struct phy_cmd[]) { /* startup */ 1054 /* Status is read once to clear old link state */ 1055 {MIIM_STATUS, miim_read, NULL}, 1056 /* Auto-negotiate */ 1057 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1058 /* Read the status */ 1059 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1060 {miim_end,} 1061 }, 1062 (struct phy_cmd[]) { /* shutdown */ 1063 {miim_end,} 1064 }, 1065 }; 1066 1067 struct phy_info phy_info_M88E1011S = { 1068 0x01410c6, 1069 "Marvell 88E1011S", 1070 4, 1071 (struct phy_cmd[]){ /* config */ 1072 /* Reset and configure the PHY */ 1073 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1074 {0x1d, 0x1f, NULL}, 1075 {0x1e, 0x200c, NULL}, 1076 {0x1d, 0x5, NULL}, 1077 {0x1e, 0x0, NULL}, 1078 {0x1e, 0x100, NULL}, 1079 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1080 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1081 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1082 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1083 {miim_end,} 1084 }, 1085 (struct phy_cmd[]){ /* startup */ 1086 /* Status is read once to clear old link state */ 1087 {MIIM_STATUS, miim_read, NULL}, 1088 /* Auto-negotiate */ 1089 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1090 /* Read the status */ 1091 {MIIM_88E1011_PHY_STATUS, miim_read, 1092 &mii_parse_88E1011_psr}, 1093 {miim_end,} 1094 }, 1095 (struct phy_cmd[]){ /* shutdown */ 1096 {miim_end,} 1097 }, 1098 }; 1099 1100 struct phy_info phy_info_M88E1111S = { 1101 0x01410cc, 1102 "Marvell 88E1111S", 1103 4, 1104 (struct phy_cmd[]){ /* config */ 1105 /* Reset and configure the PHY */ 1106 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1107 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1108 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1109 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1110 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1111 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1112 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1113 {miim_end,} 1114 }, 1115 (struct phy_cmd[]){ /* startup */ 1116 /* Status is read once to clear old link state */ 1117 {MIIM_STATUS, miim_read, NULL}, 1118 /* Auto-negotiate */ 1119 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1120 /* Read the status */ 1121 {MIIM_88E1011_PHY_STATUS, miim_read, 1122 &mii_parse_88E1011_psr}, 1123 {miim_end,} 1124 }, 1125 (struct phy_cmd[]){ /* shutdown */ 1126 {miim_end,} 1127 }, 1128 }; 1129 1130 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1131 { 1132 uint mii_data = read_phy_reg(priv, mii_reg); 1133 1134 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1135 if (priv->flags & TSEC_REDUCED) 1136 return mii_data | 1137 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1138 else 1139 return mii_data; 1140 } 1141 1142 static struct phy_info phy_info_M88E1145 = { 1143 0x01410cd, 1144 "Marvell 88E1145", 1145 4, 1146 (struct phy_cmd[]){ /* config */ 1147 /* Reset the PHY */ 1148 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1149 1150 /* Errata E0, E1 */ 1151 {29, 0x001b, NULL}, 1152 {30, 0x418f, NULL}, 1153 {29, 0x0016, NULL}, 1154 {30, 0xa2da, NULL}, 1155 1156 /* Configure the PHY */ 1157 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1158 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1159 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, 1160 NULL}, 1161 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1162 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1163 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1164 {miim_end,} 1165 }, 1166 (struct phy_cmd[]){ /* startup */ 1167 /* Status is read once to clear old link state */ 1168 {MIIM_STATUS, miim_read, NULL}, 1169 /* Auto-negotiate */ 1170 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1171 {MIIM_88E1111_PHY_LED_CONTROL, 1172 MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1173 /* Read the Status */ 1174 {MIIM_88E1011_PHY_STATUS, miim_read, 1175 &mii_parse_88E1011_psr}, 1176 {miim_end,} 1177 }, 1178 (struct phy_cmd[]){ /* shutdown */ 1179 {miim_end,} 1180 }, 1181 }; 1182 1183 struct phy_info phy_info_cis8204 = { 1184 0x3f11, 1185 "Cicada Cis8204", 1186 6, 1187 (struct phy_cmd[]){ /* config */ 1188 /* Override PHY config settings */ 1189 {MIIM_CIS8201_AUX_CONSTAT, 1190 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1191 /* Configure some basic stuff */ 1192 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1193 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1194 &mii_cis8204_fixled}, 1195 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1196 &mii_cis8204_setmode}, 1197 {miim_end,} 1198 }, 1199 (struct phy_cmd[]){ /* startup */ 1200 /* Read the Status (2x to make sure link is right) */ 1201 {MIIM_STATUS, miim_read, NULL}, 1202 /* Auto-negotiate */ 1203 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1204 /* Read the status */ 1205 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1206 &mii_parse_cis8201}, 1207 {miim_end,} 1208 }, 1209 (struct phy_cmd[]){ /* shutdown */ 1210 {miim_end,} 1211 }, 1212 }; 1213 1214 /* Cicada 8201 */ 1215 struct phy_info phy_info_cis8201 = { 1216 0xfc41, 1217 "CIS8201", 1218 4, 1219 (struct phy_cmd[]){ /* config */ 1220 /* Override PHY config settings */ 1221 {MIIM_CIS8201_AUX_CONSTAT, 1222 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1223 /* Set up the interface mode */ 1224 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, 1225 NULL}, 1226 /* Configure some basic stuff */ 1227 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1228 {miim_end,} 1229 }, 1230 (struct phy_cmd[]){ /* startup */ 1231 /* Read the Status (2x to make sure link is right) */ 1232 {MIIM_STATUS, miim_read, NULL}, 1233 /* Auto-negotiate */ 1234 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1235 /* Read the status */ 1236 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1237 &mii_parse_cis8201}, 1238 {miim_end,} 1239 }, 1240 (struct phy_cmd[]){ /* shutdown */ 1241 {miim_end,} 1242 }, 1243 }; 1244 struct phy_info phy_info_VSC8244 = { 1245 0x3f1b, 1246 "Vitesse VSC8244", 1247 6, 1248 (struct phy_cmd[]){ /* config */ 1249 /* Override PHY config settings */ 1250 /* Configure some basic stuff */ 1251 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1252 {miim_end,} 1253 }, 1254 (struct phy_cmd[]){ /* startup */ 1255 /* Read the Status (2x to make sure link is right) */ 1256 {MIIM_STATUS, miim_read, NULL}, 1257 /* Auto-negotiate */ 1258 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1259 /* Read the status */ 1260 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1261 &mii_parse_vsc8244}, 1262 {miim_end,} 1263 }, 1264 (struct phy_cmd[]){ /* shutdown */ 1265 {miim_end,} 1266 }, 1267 }; 1268 1269 struct phy_info phy_info_dm9161 = { 1270 0x0181b88, 1271 "Davicom DM9161E", 1272 4, 1273 (struct phy_cmd[]){ /* config */ 1274 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1275 /* Do not bypass the scrambler/descrambler */ 1276 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1277 /* Clear 10BTCSR to default */ 1278 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, 1279 NULL}, 1280 /* Configure some basic stuff */ 1281 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1282 /* Restart Auto Negotiation */ 1283 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1284 {miim_end,} 1285 }, 1286 (struct phy_cmd[]){ /* startup */ 1287 /* Status is read once to clear old link state */ 1288 {MIIM_STATUS, miim_read, NULL}, 1289 /* Auto-negotiate */ 1290 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1291 /* Read the status */ 1292 {MIIM_DM9161_SCSR, miim_read, 1293 &mii_parse_dm9161_scsr}, 1294 {miim_end,} 1295 }, 1296 (struct phy_cmd[]){ /* shutdown */ 1297 {miim_end,} 1298 }, 1299 }; 1300 /* a generic flavor. */ 1301 struct phy_info phy_info_generic = { 1302 0, 1303 "Unknown/Generic PHY", 1304 32, 1305 (struct phy_cmd[]) { /* config */ 1306 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1307 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1308 {miim_end,} 1309 }, 1310 (struct phy_cmd[]) { /* startup */ 1311 {PHY_BMSR, miim_read, NULL}, 1312 {PHY_BMSR, miim_read, &mii_parse_sr}, 1313 {PHY_BMSR, miim_read, &mii_parse_link}, 1314 {miim_end,} 1315 }, 1316 (struct phy_cmd[]) { /* shutdown */ 1317 {miim_end,} 1318 } 1319 }; 1320 1321 1322 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1323 { 1324 unsigned int speed; 1325 if (priv->link) { 1326 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1327 1328 switch (speed) { 1329 case MIIM_LXT971_SR2_10HDX: 1330 priv->speed = 10; 1331 priv->duplexity = 0; 1332 break; 1333 case MIIM_LXT971_SR2_10FDX: 1334 priv->speed = 10; 1335 priv->duplexity = 1; 1336 break; 1337 case MIIM_LXT971_SR2_100HDX: 1338 priv->speed = 100; 1339 priv->duplexity = 0; 1340 break; 1341 default: 1342 priv->speed = 100; 1343 priv->duplexity = 1; 1344 } 1345 } else { 1346 priv->speed = 0; 1347 priv->duplexity = 0; 1348 } 1349 1350 return 0; 1351 } 1352 1353 static struct phy_info phy_info_lxt971 = { 1354 0x0001378e, 1355 "LXT971", 1356 4, 1357 (struct phy_cmd[]){ /* config */ 1358 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1359 {miim_end,} 1360 }, 1361 (struct phy_cmd[]){ /* startup - enable interrupts */ 1362 /* { 0x12, 0x00f2, NULL }, */ 1363 {MIIM_STATUS, miim_read, NULL}, 1364 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1365 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1366 {miim_end,} 1367 }, 1368 (struct phy_cmd[]){ /* shutdown - disable interrupts */ 1369 {miim_end,} 1370 }, 1371 }; 1372 1373 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1374 * information 1375 */ 1376 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1377 { 1378 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1379 1380 case MIIM_DP83865_SPD_1000: 1381 priv->speed = 1000; 1382 break; 1383 1384 case MIIM_DP83865_SPD_100: 1385 priv->speed = 100; 1386 break; 1387 1388 default: 1389 priv->speed = 10; 1390 break; 1391 1392 } 1393 1394 if (mii_reg & MIIM_DP83865_DPX_FULL) 1395 priv->duplexity = 1; 1396 else 1397 priv->duplexity = 0; 1398 1399 return 0; 1400 } 1401 1402 struct phy_info phy_info_dp83865 = { 1403 0x20005c7, 1404 "NatSemi DP83865", 1405 4, 1406 (struct phy_cmd[]){ /* config */ 1407 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1408 {miim_end,} 1409 }, 1410 (struct phy_cmd[]){ /* startup */ 1411 /* Status is read once to clear old link state */ 1412 {MIIM_STATUS, miim_read, NULL}, 1413 /* Auto-negotiate */ 1414 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1415 /* Read the link and auto-neg status */ 1416 {MIIM_DP83865_LANR, miim_read, 1417 &mii_parse_dp83865_lanr}, 1418 {miim_end,} 1419 }, 1420 (struct phy_cmd[]){ /* shutdown */ 1421 {miim_end,} 1422 }, 1423 }; 1424 1425 struct phy_info phy_info_rtl8211b = { 1426 0x001cc91, 1427 "RealTek RTL8211B", 1428 4, 1429 (struct phy_cmd[]){ /* config */ 1430 /* Reset and configure the PHY */ 1431 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1432 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1433 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1434 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1435 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1436 {miim_end,} 1437 }, 1438 (struct phy_cmd[]){ /* startup */ 1439 /* Status is read once to clear old link state */ 1440 {MIIM_STATUS, miim_read, NULL}, 1441 /* Auto-negotiate */ 1442 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1443 /* Read the status */ 1444 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1445 {miim_end,} 1446 }, 1447 (struct phy_cmd[]){ /* shutdown */ 1448 {miim_end,} 1449 }, 1450 }; 1451 1452 struct phy_info *phy_info[] = { 1453 &phy_info_cis8204, 1454 &phy_info_cis8201, 1455 &phy_info_BCM5461S, 1456 &phy_info_BCM5464S, 1457 &phy_info_M88E1011S, 1458 &phy_info_M88E1111S, 1459 &phy_info_M88E1145, 1460 &phy_info_M88E1149S, 1461 &phy_info_dm9161, 1462 &phy_info_lxt971, 1463 &phy_info_VSC8244, 1464 &phy_info_dp83865, 1465 &phy_info_rtl8211b, 1466 &phy_info_generic, 1467 NULL 1468 }; 1469 1470 /* Grab the identifier of the device's PHY, and search through 1471 * all of the known PHYs to see if one matches. If so, return 1472 * it, if not, return NULL 1473 */ 1474 struct phy_info *get_phy_info(struct eth_device *dev) 1475 { 1476 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1477 uint phy_reg, phy_ID; 1478 int i; 1479 struct phy_info *theInfo = NULL; 1480 1481 /* Grab the bits from PHYIR1, and put them in the upper half */ 1482 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1483 phy_ID = (phy_reg & 0xffff) << 16; 1484 1485 /* Grab the bits from PHYIR2, and put them in the lower half */ 1486 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1487 phy_ID |= (phy_reg & 0xffff); 1488 1489 /* loop through all the known PHY types, and find one that */ 1490 /* matches the ID we read from the PHY. */ 1491 for (i = 0; phy_info[i]; i++) { 1492 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1493 theInfo = phy_info[i]; 1494 break; 1495 } 1496 } 1497 1498 if (theInfo == NULL) { 1499 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); 1500 return NULL; 1501 } else { 1502 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1503 } 1504 1505 return theInfo; 1506 } 1507 1508 /* Execute the given series of commands on the given device's 1509 * PHY, running functions as necessary 1510 */ 1511 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1512 { 1513 int i; 1514 uint result; 1515 volatile tsec_t *phyregs = priv->phyregs; 1516 1517 phyregs->miimcfg = MIIMCFG_RESET; 1518 1519 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1520 1521 while (phyregs->miimind & MIIMIND_BUSY) ; 1522 1523 for (i = 0; cmd->mii_reg != miim_end; i++) { 1524 if (cmd->mii_data == miim_read) { 1525 result = read_phy_reg(priv, cmd->mii_reg); 1526 1527 if (cmd->funct != NULL) 1528 (*(cmd->funct)) (result, priv); 1529 1530 } else { 1531 if (cmd->funct != NULL) 1532 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1533 else 1534 result = cmd->mii_data; 1535 1536 write_phy_reg(priv, cmd->mii_reg, result); 1537 1538 } 1539 cmd++; 1540 } 1541 } 1542 1543 /* Relocate the function pointers in the phy cmd lists */ 1544 static void relocate_cmds(void) 1545 { 1546 struct phy_cmd **cmdlistptr; 1547 struct phy_cmd *cmd; 1548 int i, j, k; 1549 1550 for (i = 0; phy_info[i]; i++) { 1551 /* First thing's first: relocate the pointers to the 1552 * PHY command structures (the structs were done) */ 1553 phy_info[i] = (struct phy_info *)((uint) phy_info[i] 1554 + gd->reloc_off); 1555 phy_info[i]->name += gd->reloc_off; 1556 phy_info[i]->config = 1557 (struct phy_cmd *)((uint) phy_info[i]->config 1558 + gd->reloc_off); 1559 phy_info[i]->startup = 1560 (struct phy_cmd *)((uint) phy_info[i]->startup 1561 + gd->reloc_off); 1562 phy_info[i]->shutdown = 1563 (struct phy_cmd *)((uint) phy_info[i]->shutdown 1564 + gd->reloc_off); 1565 1566 cmdlistptr = &phy_info[i]->config; 1567 j = 0; 1568 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { 1569 k = 0; 1570 for (cmd = *cmdlistptr; 1571 cmd->mii_reg != miim_end; 1572 cmd++) { 1573 /* Only relocate non-NULL pointers */ 1574 if (cmd->funct) 1575 cmd->funct += gd->reloc_off; 1576 1577 k++; 1578 } 1579 j++; 1580 } 1581 } 1582 1583 relocated = 1; 1584 } 1585 1586 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1587 && !defined(BITBANGMII) 1588 1589 /* 1590 * Read a MII PHY register. 1591 * 1592 * Returns: 1593 * 0 on success 1594 */ 1595 static int tsec_miiphy_read(char *devname, unsigned char addr, 1596 unsigned char reg, unsigned short *value) 1597 { 1598 unsigned short ret; 1599 struct tsec_private *priv = privlist[0]; 1600 1601 if (NULL == priv) { 1602 printf("Can't read PHY at address %d\n", addr); 1603 return -1; 1604 } 1605 1606 ret = (unsigned short)read_any_phy_reg(priv, addr, reg); 1607 *value = ret; 1608 1609 return 0; 1610 } 1611 1612 /* 1613 * Write a MII PHY register. 1614 * 1615 * Returns: 1616 * 0 on success 1617 */ 1618 static int tsec_miiphy_write(char *devname, unsigned char addr, 1619 unsigned char reg, unsigned short value) 1620 { 1621 struct tsec_private *priv = privlist[0]; 1622 1623 if (NULL == priv) { 1624 printf("Can't write PHY at address %d\n", addr); 1625 return -1; 1626 } 1627 1628 write_any_phy_reg(priv, addr, reg, value); 1629 1630 return 0; 1631 } 1632 1633 #endif 1634 1635 #ifdef CONFIG_MCAST_TFTP 1636 1637 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1638 1639 /* Set the appropriate hash bit for the given addr */ 1640 1641 /* The algorithm works like so: 1642 * 1) Take the Destination Address (ie the multicast address), and 1643 * do a CRC on it (little endian), and reverse the bits of the 1644 * result. 1645 * 2) Use the 8 most significant bits as a hash into a 256-entry 1646 * table. The table is controlled through 8 32-bit registers: 1647 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1648 * gaddr7. This means that the 3 most significant bits in the 1649 * hash index which gaddr register to use, and the 5 other bits 1650 * indicate which bit (assuming an IBM numbering scheme, which 1651 * for PowerPC (tm) is usually the case) in the tregister holds 1652 * the entry. */ 1653 static int 1654 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1655 { 1656 struct tsec_private *priv = privlist[1]; 1657 volatile tsec_t *regs = priv->regs; 1658 volatile u32 *reg_array, value; 1659 u8 result, whichbit, whichreg; 1660 1661 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1662 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1663 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1664 value = (1 << (31-whichbit)); 1665 1666 reg_array = &(regs->hash.gaddr0); 1667 1668 if (set) { 1669 reg_array[whichreg] |= value; 1670 } else { 1671 reg_array[whichreg] &= ~value; 1672 } 1673 return 0; 1674 } 1675 #endif /* Multicast TFTP ? */ 1676 1677 #endif /* CONFIG_TSEC_ENET */ 1678