xref: /openbmc/u-boot/drivers/net/tsec.c (revision e31fb4db)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Freescale Three Speed Ethernet Controller driver
4  *
5  * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
6  * (C) Copyright 2003, Motorola, Inc.
7  * author Andy Fleming
8  */
9 
10 #include <config.h>
11 #include <common.h>
12 #include <dm.h>
13 #include <malloc.h>
14 #include <net.h>
15 #include <command.h>
16 #include <tsec.h>
17 #include <fsl_mdio.h>
18 #include <linux/errno.h>
19 #include <asm/processor.h>
20 #include <asm/io.h>
21 
22 #ifndef CONFIG_DM_ETH
23 /* Default initializations for TSEC controllers. */
24 
25 static struct tsec_info_struct tsec_info[] = {
26 #ifdef CONFIG_TSEC1
27 	STD_TSEC_INFO(1),	/* TSEC1 */
28 #endif
29 #ifdef CONFIG_TSEC2
30 	STD_TSEC_INFO(2),	/* TSEC2 */
31 #endif
32 #ifdef CONFIG_MPC85XX_FEC
33 	{
34 		.regs = TSEC_GET_REGS(2, 0x2000),
35 		.devname = CONFIG_MPC85XX_FEC_NAME,
36 		.phyaddr = FEC_PHY_ADDR,
37 		.flags = FEC_FLAGS,
38 		.mii_devname = DEFAULT_MII_NAME
39 	},			/* FEC */
40 #endif
41 #ifdef CONFIG_TSEC3
42 	STD_TSEC_INFO(3),	/* TSEC3 */
43 #endif
44 #ifdef CONFIG_TSEC4
45 	STD_TSEC_INFO(4),	/* TSEC4 */
46 #endif
47 };
48 #endif /* CONFIG_DM_ETH */
49 
50 #define TBIANA_SETTINGS ( \
51 		TBIANA_ASYMMETRIC_PAUSE \
52 		| TBIANA_SYMMETRIC_PAUSE \
53 		| TBIANA_FULL_DUPLEX \
54 		)
55 
56 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
57 #ifndef CONFIG_TSEC_TBICR_SETTINGS
58 #define CONFIG_TSEC_TBICR_SETTINGS ( \
59 		TBICR_PHY_RESET \
60 		| TBICR_ANEG_ENABLE \
61 		| TBICR_FULL_DUPLEX \
62 		| TBICR_SPEED1_SET \
63 		)
64 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
65 
66 /* Configure the TBI for SGMII operation */
67 static void tsec_configure_serdes(struct tsec_private *priv)
68 {
69 	/*
70 	 * Access TBI PHY registers at given TSEC register offset as opposed
71 	 * to the register offset used for external PHY accesses
72 	 */
73 	tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
74 			      0, TBI_ANA, TBIANA_SETTINGS);
75 	tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
76 			      0, TBI_TBICON, TBICON_CLK_SELECT);
77 	tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
78 			      0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
79 }
80 
81 #ifdef CONFIG_MCAST_TFTP
82 
83 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
84 
85 /* Set the appropriate hash bit for the given addr */
86 
87 /*
88  * The algorithm works like so:
89  * 1) Take the Destination Address (ie the multicast address), and
90  * do a CRC on it (little endian), and reverse the bits of the
91  * result.
92  * 2) Use the 8 most significant bits as a hash into a 256-entry
93  * table.  The table is controlled through 8 32-bit registers:
94  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is entry
95  * 255.  This means that the 3 most significant bits in the
96  * hash index which gaddr register to use, and the 5 other bits
97  * indicate which bit (assuming an IBM numbering scheme, which
98  * for PowerPC (tm) is usually the case) in the register holds
99  * the entry.
100  */
101 #ifndef CONFIG_DM_ETH
102 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
103 #else
104 static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set)
105 #endif
106 {
107 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
108 	struct tsec __iomem *regs = priv->regs;
109 	u32 result, value;
110 	u8 whichbit, whichreg;
111 
112 	result = ether_crc(MAC_ADDR_LEN, mcast_mac);
113 	whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
114 	whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
115 
116 	value = BIT(31 - whichbit);
117 
118 	if (set)
119 		setbits_be32(&regs->hash.gaddr0 + whichreg, value);
120 	else
121 		clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
122 
123 	return 0;
124 }
125 #endif /* Multicast TFTP ? */
126 
127 /*
128  * Initialized required registers to appropriate values, zeroing
129  * those we don't care about (unless zero is bad, in which case,
130  * choose a more appropriate value)
131  */
132 static void init_registers(struct tsec __iomem *regs)
133 {
134 	/* Clear IEVENT */
135 	out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
136 
137 	out_be32(&regs->imask, IMASK_INIT_CLEAR);
138 
139 	out_be32(&regs->hash.iaddr0, 0);
140 	out_be32(&regs->hash.iaddr1, 0);
141 	out_be32(&regs->hash.iaddr2, 0);
142 	out_be32(&regs->hash.iaddr3, 0);
143 	out_be32(&regs->hash.iaddr4, 0);
144 	out_be32(&regs->hash.iaddr5, 0);
145 	out_be32(&regs->hash.iaddr6, 0);
146 	out_be32(&regs->hash.iaddr7, 0);
147 
148 	out_be32(&regs->hash.gaddr0, 0);
149 	out_be32(&regs->hash.gaddr1, 0);
150 	out_be32(&regs->hash.gaddr2, 0);
151 	out_be32(&regs->hash.gaddr3, 0);
152 	out_be32(&regs->hash.gaddr4, 0);
153 	out_be32(&regs->hash.gaddr5, 0);
154 	out_be32(&regs->hash.gaddr6, 0);
155 	out_be32(&regs->hash.gaddr7, 0);
156 
157 	out_be32(&regs->rctrl, 0x00000000);
158 
159 	/* Init RMON mib registers */
160 	memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
161 
162 	out_be32(&regs->rmon.cam1, 0xffffffff);
163 	out_be32(&regs->rmon.cam2, 0xffffffff);
164 
165 	out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
166 
167 	out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
168 
169 	out_be32(&regs->attr, ATTR_INIT_SETTINGS);
170 	out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
171 }
172 
173 /*
174  * Configure maccfg2 based on negotiated speed and duplex
175  * reported by PHY handling code
176  */
177 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
178 {
179 	struct tsec __iomem *regs = priv->regs;
180 	u32 ecntrl, maccfg2;
181 
182 	if (!phydev->link) {
183 		printf("%s: No link.\n", phydev->dev->name);
184 		return;
185 	}
186 
187 	/* clear all bits relative with interface mode */
188 	ecntrl = in_be32(&regs->ecntrl);
189 	ecntrl &= ~ECNTRL_R100;
190 
191 	maccfg2 = in_be32(&regs->maccfg2);
192 	maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
193 
194 	if (phydev->duplex)
195 		maccfg2 |= MACCFG2_FULL_DUPLEX;
196 
197 	switch (phydev->speed) {
198 	case 1000:
199 		maccfg2 |= MACCFG2_GMII;
200 		break;
201 	case 100:
202 	case 10:
203 		maccfg2 |= MACCFG2_MII;
204 
205 		/*
206 		 * Set R100 bit in all modes although
207 		 * it is only used in RGMII mode
208 		 */
209 		if (phydev->speed == 100)
210 			ecntrl |= ECNTRL_R100;
211 		break;
212 	default:
213 		printf("%s: Speed was bad\n", phydev->dev->name);
214 		break;
215 	}
216 
217 	out_be32(&regs->ecntrl, ecntrl);
218 	out_be32(&regs->maccfg2, maccfg2);
219 
220 	printf("Speed: %d, %s duplex%s\n", phydev->speed,
221 	       (phydev->duplex) ? "full" : "half",
222 	       (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
223 }
224 
225 /*
226  * This returns the status bits of the device. The return value
227  * is never checked, and this is what the 8260 driver did, so we
228  * do the same. Presumably, this would be zero if there were no
229  * errors
230  */
231 #ifndef CONFIG_DM_ETH
232 static int tsec_send(struct eth_device *dev, void *packet, int length)
233 #else
234 static int tsec_send(struct udevice *dev, void *packet, int length)
235 #endif
236 {
237 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
238 	struct tsec __iomem *regs = priv->regs;
239 	u16 status;
240 	int result = 0;
241 	int i;
242 
243 	/* Find an empty buffer descriptor */
244 	for (i = 0;
245 	     in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
246 	     i++) {
247 		if (i >= TOUT_LOOP) {
248 			debug("%s: tsec: tx buffers full\n", dev->name);
249 			return result;
250 		}
251 	}
252 
253 	out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
254 	out_be16(&priv->txbd[priv->tx_idx].length, length);
255 	status = in_be16(&priv->txbd[priv->tx_idx].status);
256 	out_be16(&priv->txbd[priv->tx_idx].status, status |
257 		(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
258 
259 	/* Tell the DMA to go */
260 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
261 
262 	/* Wait for buffer to be transmitted */
263 	for (i = 0;
264 	     in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
265 	     i++) {
266 		if (i >= TOUT_LOOP) {
267 			debug("%s: tsec: tx error\n", dev->name);
268 			return result;
269 		}
270 	}
271 
272 	priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
273 	result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
274 
275 	return result;
276 }
277 
278 #ifndef CONFIG_DM_ETH
279 static int tsec_recv(struct eth_device *dev)
280 {
281 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
282 	struct tsec __iomem *regs = priv->regs;
283 
284 	while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
285 		int length = in_be16(&priv->rxbd[priv->rx_idx].length);
286 		u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
287 		uchar *packet = net_rx_packets[priv->rx_idx];
288 
289 		/* Send the packet up if there were no errors */
290 		if (!(status & RXBD_STATS))
291 			net_process_received_packet(packet, length - 4);
292 		else
293 			printf("Got error %x\n", (status & RXBD_STATS));
294 
295 		out_be16(&priv->rxbd[priv->rx_idx].length, 0);
296 
297 		status = RXBD_EMPTY;
298 		/* Set the wrap bit if this is the last element in the list */
299 		if ((priv->rx_idx + 1) == PKTBUFSRX)
300 			status |= RXBD_WRAP;
301 		out_be16(&priv->rxbd[priv->rx_idx].status, status);
302 
303 		priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
304 	}
305 
306 	if (in_be32(&regs->ievent) & IEVENT_BSY) {
307 		out_be32(&regs->ievent, IEVENT_BSY);
308 		out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
309 	}
310 
311 	return -1;
312 }
313 #else
314 static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
315 {
316 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
317 	struct tsec __iomem *regs = priv->regs;
318 	int ret = -1;
319 
320 	if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
321 		int length = in_be16(&priv->rxbd[priv->rx_idx].length);
322 		u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
323 		u32 buf;
324 
325 		/* Send the packet up if there were no errors */
326 		if (!(status & RXBD_STATS)) {
327 			buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
328 			*packetp = (uchar *)buf;
329 			ret = length - 4;
330 		} else {
331 			printf("Got error %x\n", (status & RXBD_STATS));
332 		}
333 	}
334 
335 	if (in_be32(&regs->ievent) & IEVENT_BSY) {
336 		out_be32(&regs->ievent, IEVENT_BSY);
337 		out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
338 	}
339 
340 	return ret;
341 }
342 
343 static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
344 {
345 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
346 	u16 status;
347 
348 	out_be16(&priv->rxbd[priv->rx_idx].length, 0);
349 
350 	status = RXBD_EMPTY;
351 	/* Set the wrap bit if this is the last element in the list */
352 	if ((priv->rx_idx + 1) == PKTBUFSRX)
353 		status |= RXBD_WRAP;
354 	out_be16(&priv->rxbd[priv->rx_idx].status, status);
355 
356 	priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
357 
358 	return 0;
359 }
360 #endif
361 
362 /* Stop the interface */
363 #ifndef CONFIG_DM_ETH
364 static void tsec_halt(struct eth_device *dev)
365 #else
366 static void tsec_halt(struct udevice *dev)
367 #endif
368 {
369 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
370 	struct tsec __iomem *regs = priv->regs;
371 
372 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
373 	setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
374 
375 	while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
376 			!= (IEVENT_GRSC | IEVENT_GTSC))
377 		;
378 
379 	clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
380 
381 	/* Shut down the PHY, as needed */
382 	phy_shutdown(priv->phydev);
383 }
384 
385 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
386 /*
387  * When MACCFG1[Rx_EN] is enabled during system boot as part
388  * of the eTSEC port initialization sequence,
389  * the eTSEC Rx logic may not be properly initialized.
390  */
391 void redundant_init(struct tsec_private *priv)
392 {
393 	struct tsec __iomem *regs = priv->regs;
394 	uint t, count = 0;
395 	int fail = 1;
396 	static const u8 pkt[] = {
397 		0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
398 		0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
399 		0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
400 		0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
401 		0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
402 		0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
403 		0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
404 		0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
405 		0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
406 		0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
407 		0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
408 		0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
409 		0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
410 		0x71, 0x72};
411 
412 	/* Enable promiscuous mode */
413 	setbits_be32(&regs->rctrl, 0x8);
414 	/* Enable loopback mode */
415 	setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
416 	/* Enable transmit and receive */
417 	setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
418 
419 	/* Tell the DMA it is clear to go */
420 	setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
421 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
422 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
423 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
424 
425 	do {
426 		u16 status;
427 
428 		tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
429 
430 		/* Wait for buffer to be received */
431 		for (t = 0;
432 		     in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
433 		     t++) {
434 			if (t >= 10 * TOUT_LOOP) {
435 				printf("%s: tsec: rx error\n", priv->dev->name);
436 				break;
437 			}
438 		}
439 
440 		if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
441 			fail = 0;
442 
443 		out_be16(&priv->rxbd[priv->rx_idx].length, 0);
444 		status = RXBD_EMPTY;
445 		if ((priv->rx_idx + 1) == PKTBUFSRX)
446 			status |= RXBD_WRAP;
447 		out_be16(&priv->rxbd[priv->rx_idx].status, status);
448 		priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
449 
450 		if (in_be32(&regs->ievent) & IEVENT_BSY) {
451 			out_be32(&regs->ievent, IEVENT_BSY);
452 			out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
453 		}
454 		if (fail) {
455 			printf("loopback recv packet error!\n");
456 			clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
457 			udelay(1000);
458 			setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
459 		}
460 	} while ((count++ < 4) && (fail == 1));
461 
462 	if (fail)
463 		panic("eTSEC init fail!\n");
464 	/* Disable promiscuous mode */
465 	clrbits_be32(&regs->rctrl, 0x8);
466 	/* Disable loopback mode */
467 	clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
468 }
469 #endif
470 
471 /*
472  * Set up the buffers and their descriptors, and bring up the
473  * interface
474  */
475 static void startup_tsec(struct tsec_private *priv)
476 {
477 	struct tsec __iomem *regs = priv->regs;
478 	u16 status;
479 	int i;
480 
481 	/* reset the indices to zero */
482 	priv->rx_idx = 0;
483 	priv->tx_idx = 0;
484 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
485 	uint svr;
486 #endif
487 
488 	/* Point to the buffer descriptors */
489 	out_be32(&regs->tbase, (u32)&priv->txbd[0]);
490 	out_be32(&regs->rbase, (u32)&priv->rxbd[0]);
491 
492 	/* Initialize the Rx Buffer descriptors */
493 	for (i = 0; i < PKTBUFSRX; i++) {
494 		out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
495 		out_be16(&priv->rxbd[i].length, 0);
496 		out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
497 	}
498 	status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
499 	out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
500 
501 	/* Initialize the TX Buffer Descriptors */
502 	for (i = 0; i < TX_BUF_CNT; i++) {
503 		out_be16(&priv->txbd[i].status, 0);
504 		out_be16(&priv->txbd[i].length, 0);
505 		out_be32(&priv->txbd[i].bufptr, 0);
506 	}
507 	status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
508 	out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
509 
510 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
511 	svr = get_svr();
512 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
513 		redundant_init(priv);
514 #endif
515 	/* Enable Transmit and Receive */
516 	setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
517 
518 	/* Tell the DMA it is clear to go */
519 	setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
520 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
521 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
522 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
523 }
524 
525 /*
526  * Initializes data structures and registers for the controller,
527  * and brings the interface up. Returns the link status, meaning
528  * that it returns success if the link is up, failure otherwise.
529  * This allows U-Boot to find the first active controller.
530  */
531 #ifndef CONFIG_DM_ETH
532 static int tsec_init(struct eth_device *dev, bd_t *bd)
533 #else
534 static int tsec_init(struct udevice *dev)
535 #endif
536 {
537 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
538 #ifdef CONFIG_DM_ETH
539 	struct eth_pdata *pdata = dev_get_platdata(dev);
540 #endif
541 	struct tsec __iomem *regs = priv->regs;
542 	u32 tempval;
543 	int ret;
544 
545 	/* Make sure the controller is stopped */
546 	tsec_halt(dev);
547 
548 	/* Init MACCFG2.  Defaults to GMII */
549 	out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
550 
551 	/* Init ECNTRL */
552 	out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
553 
554 	/*
555 	 * Copy the station address into the address registers.
556 	 * For a station address of 0x12345678ABCD in transmission
557 	 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
558 	 * MACnADDR2 is set to 0x34120000.
559 	 */
560 #ifndef CONFIG_DM_ETH
561 	tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
562 		  (dev->enetaddr[3] << 8)  |  dev->enetaddr[2];
563 #else
564 	tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
565 		  (pdata->enetaddr[3] << 8)  |  pdata->enetaddr[2];
566 #endif
567 
568 	out_be32(&regs->macstnaddr1, tempval);
569 
570 #ifndef CONFIG_DM_ETH
571 	tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
572 #else
573 	tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
574 #endif
575 
576 	out_be32(&regs->macstnaddr2, tempval);
577 
578 	/* Clear out (for the most part) the other registers */
579 	init_registers(regs);
580 
581 	/* Ready the device for tx/rx */
582 	startup_tsec(priv);
583 
584 	/* Start up the PHY */
585 	ret = phy_startup(priv->phydev);
586 	if (ret) {
587 		printf("Could not initialize PHY %s\n",
588 		       priv->phydev->dev->name);
589 		return ret;
590 	}
591 
592 	adjust_link(priv, priv->phydev);
593 
594 	/* If there's no link, fail */
595 	return priv->phydev->link ? 0 : -1;
596 }
597 
598 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
599 {
600 	struct tsec __iomem *regs = priv->regs;
601 	u32 ecntrl;
602 
603 	ecntrl = in_be32(&regs->ecntrl);
604 
605 	if (ecntrl & ECNTRL_SGMII_MODE)
606 		return PHY_INTERFACE_MODE_SGMII;
607 
608 	if (ecntrl & ECNTRL_TBI_MODE) {
609 		if (ecntrl & ECNTRL_REDUCED_MODE)
610 			return PHY_INTERFACE_MODE_RTBI;
611 		else
612 			return PHY_INTERFACE_MODE_TBI;
613 	}
614 
615 	if (ecntrl & ECNTRL_REDUCED_MODE) {
616 		phy_interface_t interface;
617 
618 		if (ecntrl & ECNTRL_REDUCED_MII_MODE)
619 			return PHY_INTERFACE_MODE_RMII;
620 
621 		interface = priv->interface;
622 
623 		/*
624 		 * This isn't autodetected, so it must
625 		 * be set by the platform code.
626 		 */
627 		if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
628 		    interface == PHY_INTERFACE_MODE_RGMII_TXID ||
629 		    interface == PHY_INTERFACE_MODE_RGMII_RXID)
630 			return interface;
631 
632 		return PHY_INTERFACE_MODE_RGMII;
633 	}
634 
635 	if (priv->flags & TSEC_GIGABIT)
636 		return PHY_INTERFACE_MODE_GMII;
637 
638 	return PHY_INTERFACE_MODE_MII;
639 }
640 
641 /*
642  * Discover which PHY is attached to the device, and configure it
643  * properly.  If the PHY is not recognized, then return 0
644  * (failure).  Otherwise, return 1
645  */
646 static int init_phy(struct tsec_private *priv)
647 {
648 	struct phy_device *phydev;
649 	struct tsec __iomem *regs = priv->regs;
650 	u32 supported = (SUPPORTED_10baseT_Half |
651 			SUPPORTED_10baseT_Full |
652 			SUPPORTED_100baseT_Half |
653 			SUPPORTED_100baseT_Full);
654 
655 	if (priv->flags & TSEC_GIGABIT)
656 		supported |= SUPPORTED_1000baseT_Full;
657 
658 	/* Assign a Physical address to the TBI */
659 	out_be32(&regs->tbipa, priv->tbiaddr);
660 
661 	priv->interface = tsec_get_interface(priv);
662 
663 	if (priv->interface == PHY_INTERFACE_MODE_SGMII)
664 		tsec_configure_serdes(priv);
665 
666 	phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
667 			     priv->interface);
668 	if (!phydev)
669 		return 0;
670 
671 	phydev->supported &= supported;
672 	phydev->advertising = phydev->supported;
673 
674 	priv->phydev = phydev;
675 
676 	phy_config(phydev);
677 
678 	return 1;
679 }
680 
681 #ifndef CONFIG_DM_ETH
682 /*
683  * Initialize device structure. Returns success if PHY
684  * initialization succeeded (i.e. if it recognizes the PHY)
685  */
686 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
687 {
688 	struct eth_device *dev;
689 	int i;
690 	struct tsec_private *priv;
691 
692 	dev = (struct eth_device *)malloc(sizeof(*dev));
693 
694 	if (!dev)
695 		return 0;
696 
697 	memset(dev, 0, sizeof(*dev));
698 
699 	priv = (struct tsec_private *)malloc(sizeof(*priv));
700 
701 	if (!priv) {
702 		free(dev);
703 		return 0;
704 	}
705 
706 	priv->regs = tsec_info->regs;
707 	priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
708 
709 	priv->phyaddr = tsec_info->phyaddr;
710 	priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
711 	priv->flags = tsec_info->flags;
712 
713 	strcpy(dev->name, tsec_info->devname);
714 	priv->interface = tsec_info->interface;
715 	priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
716 	priv->dev = dev;
717 	dev->iobase = 0;
718 	dev->priv = priv;
719 	dev->init = tsec_init;
720 	dev->halt = tsec_halt;
721 	dev->send = tsec_send;
722 	dev->recv = tsec_recv;
723 #ifdef CONFIG_MCAST_TFTP
724 	dev->mcast = tsec_mcast_addr;
725 #endif
726 
727 	/* Tell U-Boot to get the addr from the env */
728 	for (i = 0; i < 6; i++)
729 		dev->enetaddr[i] = 0;
730 
731 	eth_register(dev);
732 
733 	/* Reset the MAC */
734 	setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
735 	udelay(2);  /* Soft Reset must be asserted for 3 TX clocks */
736 	clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
737 
738 	/* Try to initialize PHY here, and return */
739 	return init_phy(priv);
740 }
741 
742 /*
743  * Initialize all the TSEC devices
744  *
745  * Returns the number of TSEC devices that were initialized
746  */
747 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
748 {
749 	int i;
750 	int count = 0;
751 
752 	for (i = 0; i < num; i++) {
753 		int ret = tsec_initialize(bis, &tsecs[i]);
754 
755 		if (ret > 0)
756 			count += ret;
757 	}
758 
759 	return count;
760 }
761 
762 int tsec_standard_init(bd_t *bis)
763 {
764 	struct fsl_pq_mdio_info info;
765 
766 	info.regs = TSEC_GET_MDIO_REGS_BASE(1);
767 	info.name = DEFAULT_MII_NAME;
768 
769 	fsl_pq_mdio_init(bis, &info);
770 
771 	return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
772 }
773 #else /* CONFIG_DM_ETH */
774 int tsec_probe(struct udevice *dev)
775 {
776 	struct tsec_private *priv = dev_get_priv(dev);
777 	struct eth_pdata *pdata = dev_get_platdata(dev);
778 	struct fsl_pq_mdio_info mdio_info;
779 	struct ofnode_phandle_args phandle_args;
780 	ofnode parent;
781 	const char *phy_mode;
782 	int ret;
783 
784 	pdata->iobase = (phys_addr_t)dev_read_addr(dev);
785 	priv->regs = (struct tsec *)pdata->iobase;
786 
787 	if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
788 				       &phandle_args)) {
789 		debug("phy-handle does not exist under tsec %s\n", dev->name);
790 		return -ENOENT;
791 	} else {
792 		int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
793 
794 		priv->phyaddr = reg;
795 	}
796 
797 	parent = ofnode_get_parent(phandle_args.node);
798 	if (ofnode_valid(parent)) {
799 		int reg = ofnode_get_addr_index(parent, 0);
800 
801 		priv->phyregs_sgmii = (struct tsec_mii_mng *)reg;
802 	} else {
803 		debug("No parent node for PHY?\n");
804 		return -ENOENT;
805 	}
806 
807 	if (dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
808 				       &phandle_args)) {
809 		priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
810 	} else {
811 		int reg = ofnode_read_u32_default(phandle_args.node, "reg",
812 						  CONFIG_SYS_TBIPA_VALUE);
813 		priv->tbiaddr = reg;
814 	}
815 
816 	phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
817 	if (phy_mode)
818 		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
819 	if (pdata->phy_interface == -1) {
820 		debug("Invalid PHY interface '%s'\n", phy_mode);
821 		return -EINVAL;
822 	}
823 	priv->interface = pdata->phy_interface;
824 
825 	/* Initialize flags */
826 	priv->flags = TSEC_GIGABIT;
827 	if (priv->interface == PHY_INTERFACE_MODE_SGMII)
828 		priv->flags |= TSEC_SGMII;
829 
830 	mdio_info.regs = priv->phyregs_sgmii;
831 	mdio_info.name = (char *)dev->name;
832 	ret = fsl_pq_mdio_init(NULL, &mdio_info);
833 	if (ret)
834 		return ret;
835 
836 	/* Reset the MAC */
837 	setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
838 	udelay(2);  /* Soft Reset must be asserted for 3 TX clocks */
839 	clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
840 
841 	priv->dev = dev;
842 	priv->bus = miiphy_get_dev_by_name(dev->name);
843 
844 	/* Try to initialize PHY here, and return */
845 	return !init_phy(priv);
846 }
847 
848 int tsec_remove(struct udevice *dev)
849 {
850 	struct tsec_private *priv = dev->priv;
851 
852 	free(priv->phydev);
853 	mdio_unregister(priv->bus);
854 	mdio_free(priv->bus);
855 
856 	return 0;
857 }
858 
859 static const struct eth_ops tsec_ops = {
860 	.start = tsec_init,
861 	.send = tsec_send,
862 	.recv = tsec_recv,
863 	.free_pkt = tsec_free_pkt,
864 	.stop = tsec_halt,
865 #ifdef CONFIG_MCAST_TFTP
866 	.mcast = tsec_mcast_addr,
867 #endif
868 };
869 
870 static const struct udevice_id tsec_ids[] = {
871 	{ .compatible = "fsl,tsec" },
872 	{ }
873 };
874 
875 U_BOOT_DRIVER(eth_tsec) = {
876 	.name = "tsec",
877 	.id = UCLASS_ETH,
878 	.of_match = tsec_ids,
879 	.probe = tsec_probe,
880 	.remove = tsec_remove,
881 	.ops = &tsec_ops,
882 	.priv_auto_alloc_size = sizeof(struct tsec_private),
883 	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
884 	.flags = DM_FLAG_ALLOC_PRIV_DMA,
885 };
886 #endif /* CONFIG_DM_ETH */
887