1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004-2009 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 #include <tsec.h> 20 #include <asm/errno.h> 21 22 #include "miiphy.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define TX_BUF_CNT 2 27 28 static uint rxIdx; /* index of the current RX buffer */ 29 static uint txIdx; /* index of the current TX buffer */ 30 31 typedef volatile struct rtxbd { 32 txbd8_t txbd[TX_BUF_CNT]; 33 rxbd8_t rxbd[PKTBUFSRX]; 34 } RTXBD; 35 36 #define MAXCONTROLLERS (8) 37 38 static struct tsec_private *privlist[MAXCONTROLLERS]; 39 static int num_tsecs = 0; 40 41 #ifdef __GNUC__ 42 static RTXBD rtx __attribute__ ((aligned(8))); 43 #else 44 #error "rtx must be 64-bit aligned" 45 #endif 46 47 static int tsec_send(struct eth_device *dev, 48 volatile void *packet, int length); 49 static int tsec_recv(struct eth_device *dev); 50 static int tsec_init(struct eth_device *dev, bd_t * bd); 51 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info); 52 static void tsec_halt(struct eth_device *dev); 53 static void init_registers(volatile tsec_t * regs); 54 static void startup_tsec(struct eth_device *dev); 55 static int init_phy(struct eth_device *dev); 56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 57 uint read_phy_reg(struct tsec_private *priv, uint regnum); 58 static struct phy_info *get_phy_info(struct eth_device *dev); 59 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 60 static void adjust_link(struct eth_device *dev); 61 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 62 && !defined(BITBANGMII) 63 static int tsec_miiphy_write(char *devname, unsigned char addr, 64 unsigned char reg, unsigned short value); 65 static int tsec_miiphy_read(char *devname, unsigned char addr, 66 unsigned char reg, unsigned short *value); 67 #endif 68 #ifdef CONFIG_MCAST_TFTP 69 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 70 #endif 71 72 /* Default initializations for TSEC controllers. */ 73 74 static struct tsec_info_struct tsec_info[] = { 75 #ifdef CONFIG_TSEC1 76 STD_TSEC_INFO(1), /* TSEC1 */ 77 #endif 78 #ifdef CONFIG_TSEC2 79 STD_TSEC_INFO(2), /* TSEC2 */ 80 #endif 81 #ifdef CONFIG_MPC85XX_FEC 82 { 83 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), 84 .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), 85 .devname = CONFIG_MPC85XX_FEC_NAME, 86 .phyaddr = FEC_PHY_ADDR, 87 .flags = FEC_FLAGS 88 }, /* FEC */ 89 #endif 90 #ifdef CONFIG_TSEC3 91 STD_TSEC_INFO(3), /* TSEC3 */ 92 #endif 93 #ifdef CONFIG_TSEC4 94 STD_TSEC_INFO(4), /* TSEC4 */ 95 #endif 96 }; 97 98 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) 99 { 100 int i; 101 102 for (i = 0; i < num; i++) 103 tsec_initialize(bis, &tsecs[i]); 104 105 return 0; 106 } 107 108 int tsec_standard_init(bd_t *bis) 109 { 110 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); 111 } 112 113 /* Initialize device structure. Returns success if PHY 114 * initialization succeeded (i.e. if it recognizes the PHY) 115 */ 116 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) 117 { 118 struct eth_device *dev; 119 int i; 120 struct tsec_private *priv; 121 122 dev = (struct eth_device *)malloc(sizeof *dev); 123 124 if (NULL == dev) 125 return 0; 126 127 memset(dev, 0, sizeof *dev); 128 129 priv = (struct tsec_private *)malloc(sizeof(*priv)); 130 131 if (NULL == priv) 132 return 0; 133 134 privlist[num_tsecs++] = priv; 135 priv->regs = tsec_info->regs; 136 priv->phyregs = tsec_info->miiregs; 137 priv->phyregs_sgmii = tsec_info->miiregs_sgmii; 138 139 priv->phyaddr = tsec_info->phyaddr; 140 priv->flags = tsec_info->flags; 141 142 sprintf(dev->name, tsec_info->devname); 143 dev->iobase = 0; 144 dev->priv = priv; 145 dev->init = tsec_init; 146 dev->halt = tsec_halt; 147 dev->send = tsec_send; 148 dev->recv = tsec_recv; 149 #ifdef CONFIG_MCAST_TFTP 150 dev->mcast = tsec_mcast_addr; 151 #endif 152 153 /* Tell u-boot to get the addr from the env */ 154 for (i = 0; i < 6; i++) 155 dev->enetaddr[i] = 0; 156 157 eth_register(dev); 158 159 /* Reset the MAC */ 160 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 161 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ 162 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 163 164 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 165 && !defined(BITBANGMII) 166 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 167 #endif 168 169 /* Try to initialize PHY here, and return */ 170 return init_phy(dev); 171 } 172 173 /* Initializes data structures and registers for the controller, 174 * and brings the interface up. Returns the link status, meaning 175 * that it returns success if the link is up, failure otherwise. 176 * This allows u-boot to find the first active controller. 177 */ 178 static int tsec_init(struct eth_device *dev, bd_t * bd) 179 { 180 uint tempval; 181 char tmpbuf[MAC_ADDR_LEN]; 182 int i; 183 struct tsec_private *priv = (struct tsec_private *)dev->priv; 184 volatile tsec_t *regs = priv->regs; 185 186 /* Make sure the controller is stopped */ 187 tsec_halt(dev); 188 189 /* Init MACCFG2. Defaults to GMII */ 190 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 191 192 /* Init ECNTRL */ 193 regs->ecntrl = ECNTRL_INIT_SETTINGS; 194 195 /* Copy the station address into the address registers. 196 * Backwards, because little endian MACS are dumb */ 197 for (i = 0; i < MAC_ADDR_LEN; i++) { 198 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 199 } 200 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) | 201 tmpbuf[3]; 202 203 regs->macstnaddr1 = tempval; 204 205 tempval = *((uint *) (tmpbuf + 4)); 206 207 regs->macstnaddr2 = tempval; 208 209 /* reset the indices to zero */ 210 rxIdx = 0; 211 txIdx = 0; 212 213 /* Clear out (for the most part) the other registers */ 214 init_registers(regs); 215 216 /* Ready the device for tx/rx */ 217 startup_tsec(dev); 218 219 /* If there's no link, fail */ 220 return (priv->link ? 0 : -1); 221 } 222 223 /* Writes the given phy's reg with value, using the specified MDIO regs */ 224 static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr, 225 uint reg, uint value) 226 { 227 int timeout = 1000000; 228 229 phyregs->miimadd = (addr << 8) | reg; 230 phyregs->miimcon = value; 231 asm("sync"); 232 233 timeout = 1000000; 234 while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ; 235 } 236 237 238 /* Provide the default behavior of writing the PHY of this ethernet device */ 239 #define write_phy_reg(priv, regnum, value) \ 240 tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value) 241 242 /* Reads register regnum on the device's PHY through the 243 * specified registers. It lowers and raises the read 244 * command, and waits for the data to become valid (miimind 245 * notvalid bit cleared), and the bus to cease activity (miimind 246 * busy bit cleared), and then returns the value 247 */ 248 static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, 249 uint phyid, uint regnum) 250 { 251 uint value; 252 253 /* Put the address of the phy, and the register 254 * number into MIIMADD */ 255 phyregs->miimadd = (phyid << 8) | regnum; 256 257 /* Clear the command register, and wait */ 258 phyregs->miimcom = 0; 259 asm("sync"); 260 261 /* Initiate a read command, and wait */ 262 phyregs->miimcom = MIIM_READ_COMMAND; 263 asm("sync"); 264 265 /* Wait for the the indication that the read is done */ 266 while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 267 268 /* Grab the value read from the PHY */ 269 value = phyregs->miimstat; 270 271 return value; 272 } 273 274 /* #define to provide old read_phy_reg functionality without duplicating code */ 275 #define read_phy_reg(priv,regnum) \ 276 tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum) 277 278 #define TBIANA_SETTINGS ( \ 279 TBIANA_ASYMMETRIC_PAUSE \ 280 | TBIANA_SYMMETRIC_PAUSE \ 281 | TBIANA_FULL_DUPLEX \ 282 ) 283 284 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ 285 #ifndef CONFIG_TSEC_TBICR_SETTINGS 286 #define TBICR_SETTINGS ( \ 287 TBICR_PHY_RESET \ 288 | TBICR_FULL_DUPLEX \ 289 | TBICR_SPEED1_SET \ 290 ) 291 #else 292 #define TBICR_SETTINGS CONFIG_TSEC_TBICR_SETTINGS 293 #endif /* CONFIG_TSEC_TBICR_SETTINGS */ 294 295 /* Configure the TBI for SGMII operation */ 296 static void tsec_configure_serdes(struct tsec_private *priv) 297 { 298 /* Access TBI PHY registers at given TSEC register offset as opposed 299 * to the register offset used for external PHY accesses */ 300 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA, 301 TBIANA_SETTINGS); 302 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, 303 TBICON_CLK_SELECT); 304 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR, 305 TBICR_SETTINGS); 306 } 307 308 /* Discover which PHY is attached to the device, and configure it 309 * properly. If the PHY is not recognized, then return 0 310 * (failure). Otherwise, return 1 311 */ 312 static int init_phy(struct eth_device *dev) 313 { 314 struct tsec_private *priv = (struct tsec_private *)dev->priv; 315 struct phy_info *curphy; 316 volatile tsec_t *regs = priv->regs; 317 318 /* Assign a Physical address to the TBI */ 319 regs->tbipa = CONFIG_SYS_TBIPA_VALUE; 320 asm("sync"); 321 322 /* Reset MII (due to new addresses) */ 323 priv->phyregs->miimcfg = MIIMCFG_RESET; 324 asm("sync"); 325 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 326 asm("sync"); 327 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 328 329 /* Get the cmd structure corresponding to the attached 330 * PHY */ 331 curphy = get_phy_info(dev); 332 333 if (curphy == NULL) { 334 priv->phyinfo = NULL; 335 printf("%s: No PHY found\n", dev->name); 336 337 return 0; 338 } 339 340 if (regs->ecntrl & ECNTRL_SGMII_MODE) 341 tsec_configure_serdes(priv); 342 343 priv->phyinfo = curphy; 344 345 phy_run_commands(priv, priv->phyinfo->config); 346 347 return 1; 348 } 349 350 /* 351 * Returns which value to write to the control register. 352 * For 10/100, the value is slightly different 353 */ 354 static uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 355 { 356 if (priv->flags & TSEC_GIGABIT) 357 return MIIM_CONTROL_INIT; 358 else 359 return MIIM_CR_INIT; 360 } 361 362 /* 363 * Wait for auto-negotiation to complete, then determine link 364 */ 365 static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 366 { 367 /* 368 * Wait if the link is up, and autonegotiation is in progress 369 * (ie - we're capable and it's not done) 370 */ 371 mii_reg = read_phy_reg(priv, MIIM_STATUS); 372 if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 373 int i = 0; 374 375 puts("Waiting for PHY auto negotiation to complete"); 376 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 377 /* 378 * Timeout reached ? 379 */ 380 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 381 puts(" TIMEOUT !\n"); 382 priv->link = 0; 383 return 0; 384 } 385 386 if (ctrlc()) { 387 puts("user interrupt!\n"); 388 priv->link = 0; 389 return -EINTR; 390 } 391 392 if ((i++ % 1000) == 0) { 393 putc('.'); 394 } 395 udelay(1000); /* 1 ms */ 396 mii_reg = read_phy_reg(priv, MIIM_STATUS); 397 } 398 puts(" done\n"); 399 400 /* Link status bit is latched low, read it again */ 401 mii_reg = read_phy_reg(priv, MIIM_STATUS); 402 403 udelay(500000); /* another 500 ms (results in faster booting) */ 404 } 405 406 priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0; 407 408 return 0; 409 } 410 411 /* Generic function which updates the speed and duplex. If 412 * autonegotiation is enabled, it uses the AND of the link 413 * partner's advertised capabilities and our advertised 414 * capabilities. If autonegotiation is disabled, we use the 415 * appropriate bits in the control register. 416 * 417 * Stolen from Linux's mii.c and phy_device.c 418 */ 419 static uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 420 { 421 /* We're using autonegotiation */ 422 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 423 uint lpa = 0; 424 uint gblpa = 0; 425 426 /* Check for gigabit capability */ 427 if (mii_reg & PHY_BMSR_EXT) { 428 /* We want a list of states supported by 429 * both PHYs in the link 430 */ 431 gblpa = read_phy_reg(priv, PHY_1000BTSR); 432 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 433 } 434 435 /* Set the baseline so we only have to set them 436 * if they're different 437 */ 438 priv->speed = 10; 439 priv->duplexity = 0; 440 441 /* Check the gigabit fields */ 442 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 443 priv->speed = 1000; 444 445 if (gblpa & PHY_1000BTSR_1000FD) 446 priv->duplexity = 1; 447 448 /* We're done! */ 449 return 0; 450 } 451 452 lpa = read_phy_reg(priv, PHY_ANAR); 453 lpa &= read_phy_reg(priv, PHY_ANLPAR); 454 455 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 456 priv->speed = 100; 457 458 if (lpa & PHY_ANLPAR_TXFD) 459 priv->duplexity = 1; 460 461 } else if (lpa & PHY_ANLPAR_10FD) 462 priv->duplexity = 1; 463 } else { 464 uint bmcr = read_phy_reg(priv, PHY_BMCR); 465 466 priv->speed = 10; 467 priv->duplexity = 0; 468 469 if (bmcr & PHY_BMCR_DPLX) 470 priv->duplexity = 1; 471 472 if (bmcr & PHY_BMCR_1000_MBPS) 473 priv->speed = 1000; 474 else if (bmcr & PHY_BMCR_100_MBPS) 475 priv->speed = 100; 476 } 477 478 return 0; 479 } 480 481 /* 482 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain 483 * circumstances. eg a gigabit TSEC connected to a gigabit switch with 484 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't 485 * link. "Ethernet@Wirespeed" reduces advertised speed until link 486 * can be achieved. 487 */ 488 static uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv) 489 { 490 return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010; 491 } 492 493 /* 494 * Parse the BCM54xx status register for speed and duplex information. 495 * The linux sungem_phy has this information, but in a table format. 496 */ 497 static uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 498 { 499 /* If there is no link, speed and duplex don't matter */ 500 if (!priv->link) 501 return 0; 502 503 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> 504 MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) { 505 case 1: 506 priv->duplexity = 0; 507 priv->speed = 10; 508 break; 509 case 2: 510 priv->duplexity = 1; 511 priv->speed = 10; 512 break; 513 case 3: 514 priv->duplexity = 0; 515 priv->speed = 100; 516 break; 517 case 5: 518 priv->duplexity = 1; 519 priv->speed = 100; 520 break; 521 case 6: 522 priv->duplexity = 0; 523 priv->speed = 1000; 524 break; 525 case 7: 526 priv->duplexity = 1; 527 priv->speed = 1000; 528 break; 529 default: 530 printf("Auto-neg error, defaulting to 10BT/HD\n"); 531 priv->duplexity = 0; 532 priv->speed = 10; 533 break; 534 } 535 536 return 0; 537 } 538 539 /* 540 * Find out if PHY is in copper or serdes mode by looking at Expansion Reg 541 * 0x42 - "Operating Mode Status Register" 542 */ 543 static int BCM8482_is_serdes(struct tsec_private *priv) 544 { 545 u16 val; 546 int serdes = 0; 547 548 write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_ER | 0x42); 549 val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA); 550 551 switch (val & 0x1f) { 552 case 0x0d: /* RGMII-to-100Base-FX */ 553 case 0x0e: /* RGMII-to-SGMII */ 554 case 0x0f: /* RGMII-to-SerDes */ 555 case 0x12: /* SGMII-to-SerDes */ 556 case 0x13: /* SGMII-to-100Base-FX */ 557 case 0x16: /* SerDes-to-Serdes */ 558 serdes = 1; 559 break; 560 case 0x6: /* RGMII-to-Copper */ 561 case 0x14: /* SGMII-to-Copper */ 562 case 0x17: /* SerDes-to-Copper */ 563 break; 564 default: 565 printf("ERROR, invalid PHY mode (0x%x\n)", val); 566 break; 567 } 568 569 return serdes; 570 } 571 572 /* 573 * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating 574 * Mode Status Register" 575 */ 576 uint mii_parse_BCM5482_serdes_sr(struct tsec_private *priv) 577 { 578 u16 val; 579 int i = 0; 580 581 /* Wait 1s for link - Clause 37 autonegotiation happens very fast */ 582 while (1) { 583 write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, 584 MIIM_BCM54XX_EXP_SEL_ER | 0x42); 585 val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA); 586 587 if (val & 0x8000) 588 break; 589 590 if (i++ > 1000) { 591 priv->link = 0; 592 return 1; 593 } 594 595 udelay(1000); /* 1 ms */ 596 } 597 598 priv->link = 1; 599 switch ((val >> 13) & 0x3) { 600 case (0x00): 601 priv->speed = 10; 602 break; 603 case (0x01): 604 priv->speed = 100; 605 break; 606 case (0x02): 607 priv->speed = 1000; 608 break; 609 } 610 611 priv->duplexity = (val & 0x1000) == 0x1000; 612 613 return 0; 614 } 615 616 /* 617 * Figure out if BCM5482 is in serdes or copper mode and determine link 618 * configuration accordingly 619 */ 620 static uint mii_parse_BCM5482_sr(uint mii_reg, struct tsec_private *priv) 621 { 622 if (BCM8482_is_serdes(priv)) { 623 mii_parse_BCM5482_serdes_sr(priv); 624 priv->flags |= TSEC_FIBER; 625 } else { 626 /* Wait for auto-negotiation to complete or fail */ 627 mii_parse_sr(mii_reg, priv); 628 629 /* Parse BCM54xx copper aux status register */ 630 mii_reg = read_phy_reg(priv, MIIM_BCM54xx_AUXSTATUS); 631 mii_parse_BCM54xx_sr(mii_reg, priv); 632 } 633 634 return 0; 635 } 636 637 /* Parse the 88E1011's status register for speed and duplex 638 * information 639 */ 640 static uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 641 { 642 uint speed; 643 644 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 645 646 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 647 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 648 int i = 0; 649 650 puts("Waiting for PHY realtime link"); 651 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 652 /* Timeout reached ? */ 653 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 654 puts(" TIMEOUT !\n"); 655 priv->link = 0; 656 break; 657 } 658 659 if ((i++ % 1000) == 0) { 660 putc('.'); 661 } 662 udelay(1000); /* 1 ms */ 663 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 664 } 665 puts(" done\n"); 666 udelay(500000); /* another 500 ms (results in faster booting) */ 667 } else { 668 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 669 priv->link = 1; 670 else 671 priv->link = 0; 672 } 673 674 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 675 priv->duplexity = 1; 676 else 677 priv->duplexity = 0; 678 679 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 680 681 switch (speed) { 682 case MIIM_88E1011_PHYSTAT_GBIT: 683 priv->speed = 1000; 684 break; 685 case MIIM_88E1011_PHYSTAT_100: 686 priv->speed = 100; 687 break; 688 default: 689 priv->speed = 10; 690 } 691 692 return 0; 693 } 694 695 /* Parse the RTL8211B's status register for speed and duplex 696 * information 697 */ 698 static uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 699 { 700 uint speed; 701 702 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 703 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 704 int i = 0; 705 706 /* in case of timeout ->link is cleared */ 707 priv->link = 1; 708 puts("Waiting for PHY realtime link"); 709 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 710 /* Timeout reached ? */ 711 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 712 puts(" TIMEOUT !\n"); 713 priv->link = 0; 714 break; 715 } 716 717 if ((i++ % 1000) == 0) { 718 putc('.'); 719 } 720 udelay(1000); /* 1 ms */ 721 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 722 } 723 puts(" done\n"); 724 udelay(500000); /* another 500 ms (results in faster booting) */ 725 } else { 726 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 727 priv->link = 1; 728 else 729 priv->link = 0; 730 } 731 732 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 733 priv->duplexity = 1; 734 else 735 priv->duplexity = 0; 736 737 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 738 739 switch (speed) { 740 case MIIM_RTL8211B_PHYSTAT_GBIT: 741 priv->speed = 1000; 742 break; 743 case MIIM_RTL8211B_PHYSTAT_100: 744 priv->speed = 100; 745 break; 746 default: 747 priv->speed = 10; 748 } 749 750 return 0; 751 } 752 753 /* Parse the cis8201's status register for speed and duplex 754 * information 755 */ 756 static uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 757 { 758 uint speed; 759 760 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 761 priv->duplexity = 1; 762 else 763 priv->duplexity = 0; 764 765 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 766 switch (speed) { 767 case MIIM_CIS8201_AUXCONSTAT_GBIT: 768 priv->speed = 1000; 769 break; 770 case MIIM_CIS8201_AUXCONSTAT_100: 771 priv->speed = 100; 772 break; 773 default: 774 priv->speed = 10; 775 break; 776 } 777 778 return 0; 779 } 780 781 /* Parse the vsc8244's status register for speed and duplex 782 * information 783 */ 784 static uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 785 { 786 uint speed; 787 788 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 789 priv->duplexity = 1; 790 else 791 priv->duplexity = 0; 792 793 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 794 switch (speed) { 795 case MIIM_VSC8244_AUXCONSTAT_GBIT: 796 priv->speed = 1000; 797 break; 798 case MIIM_VSC8244_AUXCONSTAT_100: 799 priv->speed = 100; 800 break; 801 default: 802 priv->speed = 10; 803 break; 804 } 805 806 return 0; 807 } 808 809 /* Parse the DM9161's status register for speed and duplex 810 * information 811 */ 812 static uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 813 { 814 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 815 priv->speed = 100; 816 else 817 priv->speed = 10; 818 819 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 820 priv->duplexity = 1; 821 else 822 priv->duplexity = 0; 823 824 return 0; 825 } 826 827 /* 828 * Hack to write all 4 PHYs with the LED values 829 */ 830 static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 831 { 832 uint phyid; 833 volatile tsec_mdio_t *regbase = priv->phyregs; 834 int timeout = 1000000; 835 836 for (phyid = 0; phyid < 4; phyid++) { 837 regbase->miimadd = (phyid << 8) | mii_reg; 838 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 839 asm("sync"); 840 841 timeout = 1000000; 842 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 843 } 844 845 return MIIM_CIS8204_SLEDCON_INIT; 846 } 847 848 static uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 849 { 850 if (priv->flags & TSEC_REDUCED) 851 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 852 else 853 return MIIM_CIS8204_EPHYCON_INIT; 854 } 855 856 static uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 857 { 858 uint mii_data = read_phy_reg(priv, mii_reg); 859 860 if (priv->flags & TSEC_REDUCED) 861 mii_data = (mii_data & 0xfff0) | 0x000b; 862 return mii_data; 863 } 864 865 /* Initialized required registers to appropriate values, zeroing 866 * those we don't care about (unless zero is bad, in which case, 867 * choose a more appropriate value) 868 */ 869 static void init_registers(volatile tsec_t * regs) 870 { 871 /* Clear IEVENT */ 872 regs->ievent = IEVENT_INIT_CLEAR; 873 874 regs->imask = IMASK_INIT_CLEAR; 875 876 regs->hash.iaddr0 = 0; 877 regs->hash.iaddr1 = 0; 878 regs->hash.iaddr2 = 0; 879 regs->hash.iaddr3 = 0; 880 regs->hash.iaddr4 = 0; 881 regs->hash.iaddr5 = 0; 882 regs->hash.iaddr6 = 0; 883 regs->hash.iaddr7 = 0; 884 885 regs->hash.gaddr0 = 0; 886 regs->hash.gaddr1 = 0; 887 regs->hash.gaddr2 = 0; 888 regs->hash.gaddr3 = 0; 889 regs->hash.gaddr4 = 0; 890 regs->hash.gaddr5 = 0; 891 regs->hash.gaddr6 = 0; 892 regs->hash.gaddr7 = 0; 893 894 regs->rctrl = 0x00000000; 895 896 /* Init RMON mib registers */ 897 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 898 899 regs->rmon.cam1 = 0xffffffff; 900 regs->rmon.cam2 = 0xffffffff; 901 902 regs->mrblr = MRBLR_INIT_SETTINGS; 903 904 regs->minflr = MINFLR_INIT_SETTINGS; 905 906 regs->attr = ATTR_INIT_SETTINGS; 907 regs->attreli = ATTRELI_INIT_SETTINGS; 908 909 } 910 911 /* Configure maccfg2 based on negotiated speed and duplex 912 * reported by PHY handling code 913 */ 914 static void adjust_link(struct eth_device *dev) 915 { 916 struct tsec_private *priv = (struct tsec_private *)dev->priv; 917 volatile tsec_t *regs = priv->regs; 918 919 if (priv->link) { 920 if (priv->duplexity != 0) 921 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 922 else 923 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 924 925 switch (priv->speed) { 926 case 1000: 927 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 928 | MACCFG2_GMII); 929 break; 930 case 100: 931 case 10: 932 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 933 | MACCFG2_MII); 934 935 /* Set R100 bit in all modes although 936 * it is only used in RGMII mode 937 */ 938 if (priv->speed == 100) 939 regs->ecntrl |= ECNTRL_R100; 940 else 941 regs->ecntrl &= ~(ECNTRL_R100); 942 break; 943 default: 944 printf("%s: Speed was bad\n", dev->name); 945 break; 946 } 947 948 printf("Speed: %d, %s duplex%s\n", priv->speed, 949 (priv->duplexity) ? "full" : "half", 950 (priv->flags & TSEC_FIBER) ? ", fiber mode" : ""); 951 952 } else { 953 printf("%s: No link.\n", dev->name); 954 } 955 } 956 957 /* Set up the buffers and their descriptors, and bring up the 958 * interface 959 */ 960 static void startup_tsec(struct eth_device *dev) 961 { 962 int i; 963 struct tsec_private *priv = (struct tsec_private *)dev->priv; 964 volatile tsec_t *regs = priv->regs; 965 966 /* Point to the buffer descriptors */ 967 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 968 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 969 970 /* Initialize the Rx Buffer descriptors */ 971 for (i = 0; i < PKTBUFSRX; i++) { 972 rtx.rxbd[i].status = RXBD_EMPTY; 973 rtx.rxbd[i].length = 0; 974 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 975 } 976 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 977 978 /* Initialize the TX Buffer Descriptors */ 979 for (i = 0; i < TX_BUF_CNT; i++) { 980 rtx.txbd[i].status = 0; 981 rtx.txbd[i].length = 0; 982 rtx.txbd[i].bufPtr = 0; 983 } 984 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 985 986 /* Start up the PHY */ 987 if(priv->phyinfo) 988 phy_run_commands(priv, priv->phyinfo->startup); 989 990 adjust_link(dev); 991 992 /* Enable Transmit and Receive */ 993 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 994 995 /* Tell the DMA it is clear to go */ 996 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 997 regs->tstat = TSTAT_CLEAR_THALT; 998 regs->rstat = RSTAT_CLEAR_RHALT; 999 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 1000 } 1001 1002 /* This returns the status bits of the device. The return value 1003 * is never checked, and this is what the 8260 driver did, so we 1004 * do the same. Presumably, this would be zero if there were no 1005 * errors 1006 */ 1007 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 1008 { 1009 int i; 1010 int result = 0; 1011 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1012 volatile tsec_t *regs = priv->regs; 1013 1014 /* Find an empty buffer descriptor */ 1015 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 1016 if (i >= TOUT_LOOP) { 1017 debug("%s: tsec: tx buffers full\n", dev->name); 1018 return result; 1019 } 1020 } 1021 1022 rtx.txbd[txIdx].bufPtr = (uint) packet; 1023 rtx.txbd[txIdx].length = length; 1024 rtx.txbd[txIdx].status |= 1025 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 1026 1027 /* Tell the DMA to go */ 1028 regs->tstat = TSTAT_CLEAR_THALT; 1029 1030 /* Wait for buffer to be transmitted */ 1031 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 1032 if (i >= TOUT_LOOP) { 1033 debug("%s: tsec: tx error\n", dev->name); 1034 return result; 1035 } 1036 } 1037 1038 txIdx = (txIdx + 1) % TX_BUF_CNT; 1039 result = rtx.txbd[txIdx].status & TXBD_STATS; 1040 1041 return result; 1042 } 1043 1044 static int tsec_recv(struct eth_device *dev) 1045 { 1046 int length; 1047 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1048 volatile tsec_t *regs = priv->regs; 1049 1050 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 1051 1052 length = rtx.rxbd[rxIdx].length; 1053 1054 /* Send the packet up if there were no errors */ 1055 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 1056 NetReceive(NetRxPackets[rxIdx], length - 4); 1057 } else { 1058 printf("Got error %x\n", 1059 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 1060 } 1061 1062 rtx.rxbd[rxIdx].length = 0; 1063 1064 /* Set the wrap bit if this is the last element in the list */ 1065 rtx.rxbd[rxIdx].status = 1066 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 1067 1068 rxIdx = (rxIdx + 1) % PKTBUFSRX; 1069 } 1070 1071 if (regs->ievent & IEVENT_BSY) { 1072 regs->ievent = IEVENT_BSY; 1073 regs->rstat = RSTAT_CLEAR_RHALT; 1074 } 1075 1076 return -1; 1077 1078 } 1079 1080 /* Stop the interface */ 1081 static void tsec_halt(struct eth_device *dev) 1082 { 1083 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1084 volatile tsec_t *regs = priv->regs; 1085 1086 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 1087 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 1088 1089 while ((regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)) 1090 != (IEVENT_GRSC | IEVENT_GTSC)) ; 1091 1092 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 1093 1094 /* Shut down the PHY, as needed */ 1095 if(priv->phyinfo) 1096 phy_run_commands(priv, priv->phyinfo->shutdown); 1097 } 1098 1099 static struct phy_info phy_info_M88E1149S = { 1100 0x1410ca, 1101 "Marvell 88E1149S", 1102 4, 1103 (struct phy_cmd[]) { /* config */ 1104 /* Reset and configure the PHY */ 1105 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1106 {0x1d, 0x1f, NULL}, 1107 {0x1e, 0x200c, NULL}, 1108 {0x1d, 0x5, NULL}, 1109 {0x1e, 0x0, NULL}, 1110 {0x1e, 0x100, NULL}, 1111 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1112 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1113 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1114 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1115 {miim_end,} 1116 }, 1117 (struct phy_cmd[]) { /* startup */ 1118 /* Status is read once to clear old link state */ 1119 {MIIM_STATUS, miim_read, NULL}, 1120 /* Auto-negotiate */ 1121 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1122 /* Read the status */ 1123 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1124 {miim_end,} 1125 }, 1126 (struct phy_cmd[]) { /* shutdown */ 1127 {miim_end,} 1128 }, 1129 }; 1130 1131 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 1132 static struct phy_info phy_info_BCM5461S = { 1133 0x02060c1, /* 5461 ID */ 1134 "Broadcom BCM5461S", 1135 0, /* not clear to me what minor revisions we can shift away */ 1136 (struct phy_cmd[]) { /* config */ 1137 /* Reset and configure the PHY */ 1138 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1139 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1140 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1141 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1142 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1143 {miim_end,} 1144 }, 1145 (struct phy_cmd[]) { /* startup */ 1146 /* Status is read once to clear old link state */ 1147 {MIIM_STATUS, miim_read, NULL}, 1148 /* Auto-negotiate */ 1149 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1150 /* Read the status */ 1151 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1152 {miim_end,} 1153 }, 1154 (struct phy_cmd[]) { /* shutdown */ 1155 {miim_end,} 1156 }, 1157 }; 1158 1159 static struct phy_info phy_info_BCM5464S = { 1160 0x02060b1, /* 5464 ID */ 1161 "Broadcom BCM5464S", 1162 0, /* not clear to me what minor revisions we can shift away */ 1163 (struct phy_cmd[]) { /* config */ 1164 /* Reset and configure the PHY */ 1165 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1166 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1167 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1168 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1169 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1170 {miim_end,} 1171 }, 1172 (struct phy_cmd[]) { /* startup */ 1173 /* Status is read once to clear old link state */ 1174 {MIIM_STATUS, miim_read, NULL}, 1175 /* Auto-negotiate */ 1176 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1177 /* Read the status */ 1178 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1179 {miim_end,} 1180 }, 1181 (struct phy_cmd[]) { /* shutdown */ 1182 {miim_end,} 1183 }, 1184 }; 1185 1186 static struct phy_info phy_info_BCM5482S = { 1187 0x0143bcb, 1188 "Broadcom BCM5482S", 1189 4, 1190 (struct phy_cmd[]) { /* config */ 1191 /* Reset and configure the PHY */ 1192 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1193 /* Setup read from auxilary control shadow register 7 */ 1194 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL}, 1195 /* Read Misc Control register and or in Ethernet@Wirespeed */ 1196 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed}, 1197 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1198 /* Initial config/enable of secondary SerDes interface */ 1199 {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf), NULL}, 1200 /* Write intial value to secondary SerDes Contol */ 1201 {MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_SSD | 0, NULL}, 1202 {MIIM_BCM54XX_EXP_DATA, MIIM_CONTROL_RESTART, NULL}, 1203 /* Enable copper/fiber auto-detect */ 1204 {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)}, 1205 {miim_end,} 1206 }, 1207 (struct phy_cmd[]) { /* startup */ 1208 /* Status is read once to clear old link state */ 1209 {MIIM_STATUS, miim_read, NULL}, 1210 /* Determine copper/fiber, auto-negotiate, and read the result */ 1211 {MIIM_STATUS, miim_read, &mii_parse_BCM5482_sr}, 1212 {miim_end,} 1213 }, 1214 (struct phy_cmd[]) { /* shutdown */ 1215 {miim_end,} 1216 }, 1217 }; 1218 1219 static struct phy_info phy_info_M88E1011S = { 1220 0x01410c6, 1221 "Marvell 88E1011S", 1222 4, 1223 (struct phy_cmd[]) { /* config */ 1224 /* Reset and configure the PHY */ 1225 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1226 {0x1d, 0x1f, NULL}, 1227 {0x1e, 0x200c, NULL}, 1228 {0x1d, 0x5, NULL}, 1229 {0x1e, 0x0, NULL}, 1230 {0x1e, 0x100, NULL}, 1231 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1232 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1233 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1234 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1235 {miim_end,} 1236 }, 1237 (struct phy_cmd[]) { /* startup */ 1238 /* Status is read once to clear old link state */ 1239 {MIIM_STATUS, miim_read, NULL}, 1240 /* Auto-negotiate */ 1241 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1242 /* Read the status */ 1243 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1244 {miim_end,} 1245 }, 1246 (struct phy_cmd[]) { /* shutdown */ 1247 {miim_end,} 1248 }, 1249 }; 1250 1251 static struct phy_info phy_info_M88E1111S = { 1252 0x01410cc, 1253 "Marvell 88E1111S", 1254 4, 1255 (struct phy_cmd[]) { /* config */ 1256 /* Reset and configure the PHY */ 1257 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1258 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1259 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1260 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1261 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1262 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1263 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1264 {miim_end,} 1265 }, 1266 (struct phy_cmd[]) { /* startup */ 1267 /* Status is read once to clear old link state */ 1268 {MIIM_STATUS, miim_read, NULL}, 1269 /* Auto-negotiate */ 1270 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1271 /* Read the status */ 1272 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1273 {miim_end,} 1274 }, 1275 (struct phy_cmd[]) { /* shutdown */ 1276 {miim_end,} 1277 }, 1278 }; 1279 1280 static struct phy_info phy_info_M88E1118 = { 1281 0x01410e1, 1282 "Marvell 88E1118", 1283 4, 1284 (struct phy_cmd[]) { /* config */ 1285 /* Reset and configure the PHY */ 1286 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1287 {0x16, 0x0002, NULL}, /* Change Page Number */ 1288 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ 1289 {0x16, 0x0003, NULL}, /* Change Page Number */ 1290 {0x10, 0x021e, NULL}, /* Adjust LED control */ 1291 {0x16, 0x0000, NULL}, /* Change Page Number */ 1292 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1293 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1294 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1295 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1296 {miim_end,} 1297 }, 1298 (struct phy_cmd[]) { /* startup */ 1299 {0x16, 0x0000, NULL}, /* Change Page Number */ 1300 /* Status is read once to clear old link state */ 1301 {MIIM_STATUS, miim_read, NULL}, 1302 /* Auto-negotiate */ 1303 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1304 /* Read the status */ 1305 {MIIM_88E1011_PHY_STATUS, miim_read, 1306 &mii_parse_88E1011_psr}, 1307 {miim_end,} 1308 }, 1309 (struct phy_cmd[]) { /* shutdown */ 1310 {miim_end,} 1311 }, 1312 }; 1313 1314 /* 1315 * Since to access LED register we need do switch the page, we 1316 * do LED configuring in the miim_read-like function as follows 1317 */ 1318 static uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) 1319 { 1320 uint pg; 1321 1322 /* Switch the page to access the led register */ 1323 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE); 1324 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE); 1325 1326 /* Configure leds */ 1327 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL, 1328 MIIM_88E1121_PHY_LED_DEF); 1329 1330 /* Restore the page pointer */ 1331 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg); 1332 return 0; 1333 } 1334 1335 static struct phy_info phy_info_M88E1121R = { 1336 0x01410cb, 1337 "Marvell 88E1121R", 1338 4, 1339 (struct phy_cmd[]) { /* config */ 1340 /* Reset and configure the PHY */ 1341 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1342 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1343 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1344 /* Configure leds */ 1345 {MIIM_88E1121_PHY_LED_CTRL, miim_read, &mii_88E1121_set_led}, 1346 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1347 /* Disable IRQs and de-assert interrupt */ 1348 {MIIM_88E1121_PHY_IRQ_EN, 0, NULL}, 1349 {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL}, 1350 {miim_end,} 1351 }, 1352 (struct phy_cmd[]) { /* startup */ 1353 /* Status is read once to clear old link state */ 1354 {MIIM_STATUS, miim_read, NULL}, 1355 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1356 {MIIM_STATUS, miim_read, &mii_parse_link}, 1357 {miim_end,} 1358 }, 1359 (struct phy_cmd[]) { /* shutdown */ 1360 {miim_end,} 1361 }, 1362 }; 1363 1364 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1365 { 1366 uint mii_data = read_phy_reg(priv, mii_reg); 1367 1368 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1369 if (priv->flags & TSEC_REDUCED) 1370 return mii_data | 1371 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1372 else 1373 return mii_data; 1374 } 1375 1376 static struct phy_info phy_info_M88E1145 = { 1377 0x01410cd, 1378 "Marvell 88E1145", 1379 4, 1380 (struct phy_cmd[]) { /* config */ 1381 /* Reset the PHY */ 1382 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1383 1384 /* Errata E0, E1 */ 1385 {29, 0x001b, NULL}, 1386 {30, 0x418f, NULL}, 1387 {29, 0x0016, NULL}, 1388 {30, 0xa2da, NULL}, 1389 1390 /* Configure the PHY */ 1391 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1392 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1393 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL}, 1394 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1395 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1396 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1397 {miim_end,} 1398 }, 1399 (struct phy_cmd[]) { /* startup */ 1400 /* Status is read once to clear old link state */ 1401 {MIIM_STATUS, miim_read, NULL}, 1402 /* Auto-negotiate */ 1403 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1404 {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1405 /* Read the Status */ 1406 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1407 {miim_end,} 1408 }, 1409 (struct phy_cmd[]) { /* shutdown */ 1410 {miim_end,} 1411 }, 1412 }; 1413 1414 static struct phy_info phy_info_cis8204 = { 1415 0x3f11, 1416 "Cicada Cis8204", 1417 6, 1418 (struct phy_cmd[]) { /* config */ 1419 /* Override PHY config settings */ 1420 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1421 /* Configure some basic stuff */ 1422 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1423 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1424 &mii_cis8204_fixled}, 1425 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1426 &mii_cis8204_setmode}, 1427 {miim_end,} 1428 }, 1429 (struct phy_cmd[]) { /* startup */ 1430 /* Read the Status (2x to make sure link is right) */ 1431 {MIIM_STATUS, miim_read, NULL}, 1432 /* Auto-negotiate */ 1433 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1434 /* Read the status */ 1435 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, 1436 {miim_end,} 1437 }, 1438 (struct phy_cmd[]) { /* shutdown */ 1439 {miim_end,} 1440 }, 1441 }; 1442 1443 /* Cicada 8201 */ 1444 static struct phy_info phy_info_cis8201 = { 1445 0xfc41, 1446 "CIS8201", 1447 4, 1448 (struct phy_cmd[]) { /* config */ 1449 /* Override PHY config settings */ 1450 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1451 /* Set up the interface mode */ 1452 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, 1453 /* Configure some basic stuff */ 1454 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1455 {miim_end,} 1456 }, 1457 (struct phy_cmd[]) { /* startup */ 1458 /* Read the Status (2x to make sure link is right) */ 1459 {MIIM_STATUS, miim_read, NULL}, 1460 /* Auto-negotiate */ 1461 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1462 /* Read the status */ 1463 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, 1464 {miim_end,} 1465 }, 1466 (struct phy_cmd[]) { /* shutdown */ 1467 {miim_end,} 1468 }, 1469 }; 1470 1471 static struct phy_info phy_info_VSC8211 = { 1472 0xfc4b, 1473 "Vitesse VSC8211", 1474 4, 1475 (struct phy_cmd[]) { /* config */ 1476 /* Override PHY config settings */ 1477 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1478 /* Set up the interface mode */ 1479 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, 1480 /* Configure some basic stuff */ 1481 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1482 {miim_end,} 1483 }, 1484 (struct phy_cmd[]) { /* startup */ 1485 /* Read the Status (2x to make sure link is right) */ 1486 {MIIM_STATUS, miim_read, NULL}, 1487 /* Auto-negotiate */ 1488 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1489 /* Read the status */ 1490 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, 1491 {miim_end,} 1492 }, 1493 (struct phy_cmd[]) { /* shutdown */ 1494 {miim_end,} 1495 }, 1496 }; 1497 1498 static struct phy_info phy_info_VSC8244 = { 1499 0x3f1b, 1500 "Vitesse VSC8244", 1501 6, 1502 (struct phy_cmd[]) { /* config */ 1503 /* Override PHY config settings */ 1504 /* Configure some basic stuff */ 1505 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1506 {miim_end,} 1507 }, 1508 (struct phy_cmd[]) { /* startup */ 1509 /* Read the Status (2x to make sure link is right) */ 1510 {MIIM_STATUS, miim_read, NULL}, 1511 /* Auto-negotiate */ 1512 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1513 /* Read the status */ 1514 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1515 {miim_end,} 1516 }, 1517 (struct phy_cmd[]) { /* shutdown */ 1518 {miim_end,} 1519 }, 1520 }; 1521 1522 static struct phy_info phy_info_VSC8641 = { 1523 0x7043, 1524 "Vitesse VSC8641", 1525 4, 1526 (struct phy_cmd[]) { /* config */ 1527 /* Configure some basic stuff */ 1528 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1529 {miim_end,} 1530 }, 1531 (struct phy_cmd[]) { /* startup */ 1532 /* Read the Status (2x to make sure link is right) */ 1533 {MIIM_STATUS, miim_read, NULL}, 1534 /* Auto-negotiate */ 1535 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1536 /* Read the status */ 1537 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1538 {miim_end,} 1539 }, 1540 (struct phy_cmd[]) { /* shutdown */ 1541 {miim_end,} 1542 }, 1543 }; 1544 1545 static struct phy_info phy_info_VSC8221 = { 1546 0xfc55, 1547 "Vitesse VSC8221", 1548 4, 1549 (struct phy_cmd[]) { /* config */ 1550 /* Configure some basic stuff */ 1551 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1552 {miim_end,} 1553 }, 1554 (struct phy_cmd[]) { /* startup */ 1555 /* Read the Status (2x to make sure link is right) */ 1556 {MIIM_STATUS, miim_read, NULL}, 1557 /* Auto-negotiate */ 1558 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1559 /* Read the status */ 1560 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1561 {miim_end,} 1562 }, 1563 (struct phy_cmd[]) { /* shutdown */ 1564 {miim_end,} 1565 }, 1566 }; 1567 1568 static struct phy_info phy_info_VSC8601 = { 1569 0x00007042, 1570 "Vitesse VSC8601", 1571 4, 1572 (struct phy_cmd[]) { /* config */ 1573 /* Override PHY config settings */ 1574 /* Configure some basic stuff */ 1575 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1576 #ifdef CONFIG_SYS_VSC8601_SKEWFIX 1577 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, 1578 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX) 1579 {MIIM_EXT_PAGE_ACCESS,1,NULL}, 1580 #define VSC8101_SKEW \ 1581 (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12) 1582 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, 1583 {MIIM_EXT_PAGE_ACCESS,0,NULL}, 1584 #endif 1585 #endif 1586 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1587 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init}, 1588 {miim_end,} 1589 }, 1590 (struct phy_cmd[]) { /* startup */ 1591 /* Read the Status (2x to make sure link is right) */ 1592 {MIIM_STATUS, miim_read, NULL}, 1593 /* Auto-negotiate */ 1594 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1595 /* Read the status */ 1596 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1597 {miim_end,} 1598 }, 1599 (struct phy_cmd[]) { /* shutdown */ 1600 {miim_end,} 1601 }, 1602 }; 1603 1604 static struct phy_info phy_info_dm9161 = { 1605 0x0181b88, 1606 "Davicom DM9161E", 1607 4, 1608 (struct phy_cmd[]) { /* config */ 1609 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1610 /* Do not bypass the scrambler/descrambler */ 1611 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1612 /* Clear 10BTCSR to default */ 1613 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL}, 1614 /* Configure some basic stuff */ 1615 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1616 /* Restart Auto Negotiation */ 1617 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1618 {miim_end,} 1619 }, 1620 (struct phy_cmd[]) { /* startup */ 1621 /* Status is read once to clear old link state */ 1622 {MIIM_STATUS, miim_read, NULL}, 1623 /* Auto-negotiate */ 1624 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1625 /* Read the status */ 1626 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr}, 1627 {miim_end,} 1628 }, 1629 (struct phy_cmd[]) { /* shutdown */ 1630 {miim_end,} 1631 }, 1632 }; 1633 1634 /* a generic flavor. */ 1635 static struct phy_info phy_info_generic = { 1636 0, 1637 "Unknown/Generic PHY", 1638 32, 1639 (struct phy_cmd[]) { /* config */ 1640 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1641 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1642 {miim_end,} 1643 }, 1644 (struct phy_cmd[]) { /* startup */ 1645 {PHY_BMSR, miim_read, NULL}, 1646 {PHY_BMSR, miim_read, &mii_parse_sr}, 1647 {PHY_BMSR, miim_read, &mii_parse_link}, 1648 {miim_end,} 1649 }, 1650 (struct phy_cmd[]) { /* shutdown */ 1651 {miim_end,} 1652 } 1653 }; 1654 1655 static uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1656 { 1657 unsigned int speed; 1658 if (priv->link) { 1659 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1660 1661 switch (speed) { 1662 case MIIM_LXT971_SR2_10HDX: 1663 priv->speed = 10; 1664 priv->duplexity = 0; 1665 break; 1666 case MIIM_LXT971_SR2_10FDX: 1667 priv->speed = 10; 1668 priv->duplexity = 1; 1669 break; 1670 case MIIM_LXT971_SR2_100HDX: 1671 priv->speed = 100; 1672 priv->duplexity = 0; 1673 break; 1674 default: 1675 priv->speed = 100; 1676 priv->duplexity = 1; 1677 } 1678 } else { 1679 priv->speed = 0; 1680 priv->duplexity = 0; 1681 } 1682 1683 return 0; 1684 } 1685 1686 static struct phy_info phy_info_lxt971 = { 1687 0x0001378e, 1688 "LXT971", 1689 4, 1690 (struct phy_cmd[]) { /* config */ 1691 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1692 {miim_end,} 1693 }, 1694 (struct phy_cmd[]) { /* startup - enable interrupts */ 1695 /* { 0x12, 0x00f2, NULL }, */ 1696 {MIIM_STATUS, miim_read, NULL}, 1697 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1698 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1699 {miim_end,} 1700 }, 1701 (struct phy_cmd[]) { /* shutdown - disable interrupts */ 1702 {miim_end,} 1703 }, 1704 }; 1705 1706 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1707 * information 1708 */ 1709 static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1710 { 1711 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1712 1713 case MIIM_DP83865_SPD_1000: 1714 priv->speed = 1000; 1715 break; 1716 1717 case MIIM_DP83865_SPD_100: 1718 priv->speed = 100; 1719 break; 1720 1721 default: 1722 priv->speed = 10; 1723 break; 1724 1725 } 1726 1727 if (mii_reg & MIIM_DP83865_DPX_FULL) 1728 priv->duplexity = 1; 1729 else 1730 priv->duplexity = 0; 1731 1732 return 0; 1733 } 1734 1735 static struct phy_info phy_info_dp83865 = { 1736 0x20005c7, 1737 "NatSemi DP83865", 1738 4, 1739 (struct phy_cmd[]) { /* config */ 1740 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1741 {miim_end,} 1742 }, 1743 (struct phy_cmd[]) { /* startup */ 1744 /* Status is read once to clear old link state */ 1745 {MIIM_STATUS, miim_read, NULL}, 1746 /* Auto-negotiate */ 1747 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1748 /* Read the link and auto-neg status */ 1749 {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr}, 1750 {miim_end,} 1751 }, 1752 (struct phy_cmd[]) { /* shutdown */ 1753 {miim_end,} 1754 }, 1755 }; 1756 1757 static struct phy_info phy_info_rtl8211b = { 1758 0x001cc91, 1759 "RealTek RTL8211B", 1760 4, 1761 (struct phy_cmd[]) { /* config */ 1762 /* Reset and configure the PHY */ 1763 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1764 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1765 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1766 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1767 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1768 {miim_end,} 1769 }, 1770 (struct phy_cmd[]) { /* startup */ 1771 /* Status is read once to clear old link state */ 1772 {MIIM_STATUS, miim_read, NULL}, 1773 /* Auto-negotiate */ 1774 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1775 /* Read the status */ 1776 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1777 {miim_end,} 1778 }, 1779 (struct phy_cmd[]) { /* shutdown */ 1780 {miim_end,} 1781 }, 1782 }; 1783 1784 static struct phy_info *phy_info[] = { 1785 &phy_info_cis8204, 1786 &phy_info_cis8201, 1787 &phy_info_BCM5461S, 1788 &phy_info_BCM5464S, 1789 &phy_info_BCM5482S, 1790 &phy_info_M88E1011S, 1791 &phy_info_M88E1111S, 1792 &phy_info_M88E1118, 1793 &phy_info_M88E1121R, 1794 &phy_info_M88E1145, 1795 &phy_info_M88E1149S, 1796 &phy_info_dm9161, 1797 &phy_info_lxt971, 1798 &phy_info_VSC8211, 1799 &phy_info_VSC8244, 1800 &phy_info_VSC8601, 1801 &phy_info_VSC8641, 1802 &phy_info_VSC8221, 1803 &phy_info_dp83865, 1804 &phy_info_rtl8211b, 1805 &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */ 1806 NULL 1807 }; 1808 1809 /* Grab the identifier of the device's PHY, and search through 1810 * all of the known PHYs to see if one matches. If so, return 1811 * it, if not, return NULL 1812 */ 1813 static struct phy_info *get_phy_info(struct eth_device *dev) 1814 { 1815 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1816 uint phy_reg, phy_ID; 1817 int i; 1818 struct phy_info *theInfo = NULL; 1819 1820 /* Grab the bits from PHYIR1, and put them in the upper half */ 1821 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1822 phy_ID = (phy_reg & 0xffff) << 16; 1823 1824 /* Grab the bits from PHYIR2, and put them in the lower half */ 1825 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1826 phy_ID |= (phy_reg & 0xffff); 1827 1828 /* loop through all the known PHY types, and find one that */ 1829 /* matches the ID we read from the PHY. */ 1830 for (i = 0; phy_info[i]; i++) { 1831 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1832 theInfo = phy_info[i]; 1833 break; 1834 } 1835 } 1836 1837 if (theInfo == &phy_info_generic) { 1838 printf("%s: No support for PHY id %x; assuming generic\n", 1839 dev->name, phy_ID); 1840 } else { 1841 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1842 } 1843 1844 return theInfo; 1845 } 1846 1847 /* Execute the given series of commands on the given device's 1848 * PHY, running functions as necessary 1849 */ 1850 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1851 { 1852 int i; 1853 uint result; 1854 volatile tsec_mdio_t *phyregs = priv->phyregs; 1855 1856 phyregs->miimcfg = MIIMCFG_RESET; 1857 1858 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1859 1860 while (phyregs->miimind & MIIMIND_BUSY) ; 1861 1862 for (i = 0; cmd->mii_reg != miim_end; i++) { 1863 if (cmd->mii_data == miim_read) { 1864 result = read_phy_reg(priv, cmd->mii_reg); 1865 1866 if (cmd->funct != NULL) 1867 (*(cmd->funct)) (result, priv); 1868 1869 } else { 1870 if (cmd->funct != NULL) 1871 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1872 else 1873 result = cmd->mii_data; 1874 1875 write_phy_reg(priv, cmd->mii_reg, result); 1876 1877 } 1878 cmd++; 1879 } 1880 } 1881 1882 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1883 && !defined(BITBANGMII) 1884 1885 /* 1886 * Read a MII PHY register. 1887 * 1888 * Returns: 1889 * 0 on success 1890 */ 1891 static int tsec_miiphy_read(char *devname, unsigned char addr, 1892 unsigned char reg, unsigned short *value) 1893 { 1894 unsigned short ret; 1895 struct tsec_private *priv = privlist[0]; 1896 1897 if (NULL == priv) { 1898 printf("Can't read PHY at address %d\n", addr); 1899 return -1; 1900 } 1901 1902 ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg); 1903 *value = ret; 1904 1905 return 0; 1906 } 1907 1908 /* 1909 * Write a MII PHY register. 1910 * 1911 * Returns: 1912 * 0 on success 1913 */ 1914 static int tsec_miiphy_write(char *devname, unsigned char addr, 1915 unsigned char reg, unsigned short value) 1916 { 1917 struct tsec_private *priv = privlist[0]; 1918 1919 if (NULL == priv) { 1920 printf("Can't write PHY at address %d\n", addr); 1921 return -1; 1922 } 1923 1924 tsec_local_mdio_write(priv->phyregs, addr, reg, value); 1925 1926 return 0; 1927 } 1928 1929 #endif 1930 1931 #ifdef CONFIG_MCAST_TFTP 1932 1933 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1934 1935 /* Set the appropriate hash bit for the given addr */ 1936 1937 /* The algorithm works like so: 1938 * 1) Take the Destination Address (ie the multicast address), and 1939 * do a CRC on it (little endian), and reverse the bits of the 1940 * result. 1941 * 2) Use the 8 most significant bits as a hash into a 256-entry 1942 * table. The table is controlled through 8 32-bit registers: 1943 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1944 * gaddr7. This means that the 3 most significant bits in the 1945 * hash index which gaddr register to use, and the 5 other bits 1946 * indicate which bit (assuming an IBM numbering scheme, which 1947 * for PowerPC (tm) is usually the case) in the tregister holds 1948 * the entry. */ 1949 static int 1950 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1951 { 1952 struct tsec_private *priv = privlist[1]; 1953 volatile tsec_t *regs = priv->regs; 1954 volatile u32 *reg_array, value; 1955 u8 result, whichbit, whichreg; 1956 1957 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1958 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1959 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1960 value = (1 << (31-whichbit)); 1961 1962 reg_array = &(regs->hash.gaddr0); 1963 1964 if (set) { 1965 reg_array[whichreg] |= value; 1966 } else { 1967 reg_array[whichreg] &= ~value; 1968 } 1969 return 0; 1970 } 1971 #endif /* Multicast TFTP ? */ 1972