1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004, 2007 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 20 #if defined(CONFIG_TSEC_ENET) 21 #include "tsec.h" 22 #include "miiphy.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define TX_BUF_CNT 2 27 28 static uint rxIdx; /* index of the current RX buffer */ 29 static uint txIdx; /* index of the current TX buffer */ 30 31 typedef volatile struct rtxbd { 32 txbd8_t txbd[TX_BUF_CNT]; 33 rxbd8_t rxbd[PKTBUFSRX]; 34 } RTXBD; 35 36 struct tsec_info_struct { 37 unsigned int phyaddr; 38 u32 flags; 39 unsigned int phyregidx; 40 }; 41 42 /* The tsec_info structure contains 3 values which the 43 * driver uses to determine how to operate a given ethernet 44 * device. The information needed is: 45 * phyaddr - The address of the PHY which is attached to 46 * the given device. 47 * 48 * flags - This variable indicates whether the device 49 * supports gigabit speed ethernet, and whether it should be 50 * in reduced mode. 51 * 52 * phyregidx - This variable specifies which ethernet device 53 * controls the MII Management registers which are connected 54 * to the PHY. For now, only TSEC1 (index 0) has 55 * access to the PHYs, so all of the entries have "0". 56 * 57 * The values specified in the table are taken from the board's 58 * config file in include/configs/. When implementing a new 59 * board with ethernet capability, it is necessary to define: 60 * TSECn_PHY_ADDR 61 * TSECn_PHYIDX 62 * 63 * for n = 1,2,3, etc. And for FEC: 64 * FEC_PHY_ADDR 65 * FEC_PHYIDX 66 */ 67 static struct tsec_info_struct tsec_info[] = { 68 #ifdef CONFIG_TSEC1 69 {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX}, 70 #else 71 {0, 0, 0}, 72 #endif 73 #ifdef CONFIG_TSEC2 74 {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX}, 75 #else 76 {0, 0, 0}, 77 #endif 78 #ifdef CONFIG_MPC85XX_FEC 79 {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX}, 80 #else 81 #ifdef CONFIG_TSEC3 82 {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX}, 83 #else 84 {0, 0, 0}, 85 #endif 86 #ifdef CONFIG_TSEC4 87 {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX}, 88 #else 89 {0, 0, 0}, 90 #endif /* CONFIG_TSEC4 */ 91 #endif /* CONFIG_MPC85XX_FEC */ 92 }; 93 94 #define MAXCONTROLLERS (4) 95 96 static int relocated = 0; 97 98 static struct tsec_private *privlist[MAXCONTROLLERS]; 99 100 #ifdef __GNUC__ 101 static RTXBD rtx __attribute__ ((aligned(8))); 102 #else 103 #error "rtx must be 64-bit aligned" 104 #endif 105 106 static int tsec_send(struct eth_device *dev, 107 volatile void *packet, int length); 108 static int tsec_recv(struct eth_device *dev); 109 static int tsec_init(struct eth_device *dev, bd_t * bd); 110 static void tsec_halt(struct eth_device *dev); 111 static void init_registers(volatile tsec_t * regs); 112 static void startup_tsec(struct eth_device *dev); 113 static int init_phy(struct eth_device *dev); 114 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 115 uint read_phy_reg(struct tsec_private *priv, uint regnum); 116 struct phy_info *get_phy_info(struct eth_device *dev); 117 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 118 static void adjust_link(struct eth_device *dev); 119 static void relocate_cmds(void); 120 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 121 && !defined(BITBANGMII) 122 static int tsec_miiphy_write(char *devname, unsigned char addr, 123 unsigned char reg, unsigned short value); 124 static int tsec_miiphy_read(char *devname, unsigned char addr, 125 unsigned char reg, unsigned short *value); 126 #endif 127 #ifdef CONFIG_MCAST_TFTP 128 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 129 #endif 130 131 /* Initialize device structure. Returns success if PHY 132 * initialization succeeded (i.e. if it recognizes the PHY) 133 */ 134 int tsec_initialize(bd_t * bis, int index, char *devname) 135 { 136 struct eth_device *dev; 137 int i; 138 struct tsec_private *priv; 139 140 dev = (struct eth_device *)malloc(sizeof *dev); 141 142 if (NULL == dev) 143 return 0; 144 145 memset(dev, 0, sizeof *dev); 146 147 priv = (struct tsec_private *)malloc(sizeof(*priv)); 148 149 if (NULL == priv) 150 return 0; 151 152 privlist[index] = priv; 153 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE); 154 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR + 155 tsec_info[index].phyregidx * 156 TSEC_SIZE); 157 158 priv->phyaddr = tsec_info[index].phyaddr; 159 priv->flags = tsec_info[index].flags; 160 161 sprintf(dev->name, devname); 162 dev->iobase = 0; 163 dev->priv = priv; 164 dev->init = tsec_init; 165 dev->halt = tsec_halt; 166 dev->send = tsec_send; 167 dev->recv = tsec_recv; 168 #ifdef CONFIG_MCAST_TFTP 169 dev->mcast = tsec_mcast_addr; 170 #endif 171 172 /* Tell u-boot to get the addr from the env */ 173 for (i = 0; i < 6; i++) 174 dev->enetaddr[i] = 0; 175 176 eth_register(dev); 177 178 /* Reset the MAC */ 179 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 180 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 181 182 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 183 && !defined(BITBANGMII) 184 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 185 #endif 186 187 /* Try to initialize PHY here, and return */ 188 return init_phy(dev); 189 } 190 191 /* Initializes data structures and registers for the controller, 192 * and brings the interface up. Returns the link status, meaning 193 * that it returns success if the link is up, failure otherwise. 194 * This allows u-boot to find the first active controller. 195 */ 196 int tsec_init(struct eth_device *dev, bd_t * bd) 197 { 198 uint tempval; 199 char tmpbuf[MAC_ADDR_LEN]; 200 int i; 201 struct tsec_private *priv = (struct tsec_private *)dev->priv; 202 volatile tsec_t *regs = priv->regs; 203 204 /* Make sure the controller is stopped */ 205 tsec_halt(dev); 206 207 /* Init MACCFG2. Defaults to GMII */ 208 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 209 210 /* Init ECNTRL */ 211 regs->ecntrl = ECNTRL_INIT_SETTINGS; 212 213 /* Copy the station address into the address registers. 214 * Backwards, because little endian MACS are dumb */ 215 for (i = 0; i < MAC_ADDR_LEN; i++) { 216 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 217 } 218 regs->macstnaddr1 = *((uint *) (tmpbuf)); 219 220 tempval = *((uint *) (tmpbuf + 4)); 221 222 regs->macstnaddr2 = tempval; 223 224 /* reset the indices to zero */ 225 rxIdx = 0; 226 txIdx = 0; 227 228 /* Clear out (for the most part) the other registers */ 229 init_registers(regs); 230 231 /* Ready the device for tx/rx */ 232 startup_tsec(dev); 233 234 /* If there's no link, fail */ 235 return (priv->link ? 0 : -1); 236 237 } 238 239 /* Write value to the device's PHY through the registers 240 * specified in priv, modifying the register specified in regnum. 241 * It will wait for the write to be done (or for a timeout to 242 * expire) before exiting 243 */ 244 void write_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum, uint value) 245 { 246 volatile tsec_t *regbase = priv->phyregs; 247 int timeout = 1000000; 248 249 regbase->miimadd = (phyid << 8) | regnum; 250 regbase->miimcon = value; 251 asm("sync"); 252 253 timeout = 1000000; 254 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 255 } 256 257 /* #define to provide old write_phy_reg functionality without duplicating code */ 258 #define write_phy_reg(priv, regnum, value) write_any_phy_reg(priv,priv->phyaddr,regnum,value) 259 260 /* Reads register regnum on the device's PHY through the 261 * registers specified in priv. It lowers and raises the read 262 * command, and waits for the data to become valid (miimind 263 * notvalid bit cleared), and the bus to cease activity (miimind 264 * busy bit cleared), and then returns the value 265 */ 266 uint read_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum) 267 { 268 uint value; 269 volatile tsec_t *regbase = priv->phyregs; 270 271 /* Put the address of the phy, and the register 272 * number into MIIMADD */ 273 regbase->miimadd = (phyid << 8) | regnum; 274 275 /* Clear the command register, and wait */ 276 regbase->miimcom = 0; 277 asm("sync"); 278 279 /* Initiate a read command, and wait */ 280 regbase->miimcom = MIIM_READ_COMMAND; 281 asm("sync"); 282 283 /* Wait for the the indication that the read is done */ 284 while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 285 286 /* Grab the value read from the PHY */ 287 value = regbase->miimstat; 288 289 return value; 290 } 291 292 /* #define to provide old read_phy_reg functionality without duplicating code */ 293 #define read_phy_reg(priv,regnum) read_any_phy_reg(priv,priv->phyaddr,regnum) 294 295 /* Discover which PHY is attached to the device, and configure it 296 * properly. If the PHY is not recognized, then return 0 297 * (failure). Otherwise, return 1 298 */ 299 static int init_phy(struct eth_device *dev) 300 { 301 struct tsec_private *priv = (struct tsec_private *)dev->priv; 302 struct phy_info *curphy; 303 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); 304 305 /* Assign a Physical address to the TBI */ 306 regs->tbipa = CFG_TBIPA_VALUE; 307 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); 308 regs->tbipa = CFG_TBIPA_VALUE; 309 asm("sync"); 310 311 /* Reset MII (due to new addresses) */ 312 priv->phyregs->miimcfg = MIIMCFG_RESET; 313 asm("sync"); 314 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 315 asm("sync"); 316 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 317 318 if (0 == relocated) 319 relocate_cmds(); 320 321 /* Get the cmd structure corresponding to the attached 322 * PHY */ 323 curphy = get_phy_info(dev); 324 325 if (curphy == NULL) { 326 priv->phyinfo = NULL; 327 printf("%s: No PHY found\n", dev->name); 328 329 return 0; 330 } 331 332 priv->phyinfo = curphy; 333 334 phy_run_commands(priv, priv->phyinfo->config); 335 336 return 1; 337 } 338 339 /* 340 * Returns which value to write to the control register. 341 * For 10/100, the value is slightly different 342 */ 343 uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 344 { 345 if (priv->flags & TSEC_GIGABIT) 346 return MIIM_CONTROL_INIT; 347 else 348 return MIIM_CR_INIT; 349 } 350 351 /* Parse the status register for link, and then do 352 * auto-negotiation 353 */ 354 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 355 { 356 /* 357 * Wait if the link is up, and autonegotiation is in progress 358 * (ie - we're capable and it's not done) 359 */ 360 mii_reg = read_phy_reg(priv, MIIM_STATUS); 361 if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) 362 && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 363 int i = 0; 364 365 puts("Waiting for PHY auto negotiation to complete"); 366 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 367 /* 368 * Timeout reached ? 369 */ 370 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 371 puts(" TIMEOUT !\n"); 372 priv->link = 0; 373 return 0; 374 } 375 376 if ((i++ % 1000) == 0) { 377 putc('.'); 378 } 379 udelay(1000); /* 1 ms */ 380 mii_reg = read_phy_reg(priv, MIIM_STATUS); 381 } 382 puts(" done\n"); 383 priv->link = 1; 384 udelay(500000); /* another 500 ms (results in faster booting) */ 385 } else { 386 if (mii_reg & MIIM_STATUS_LINK) 387 priv->link = 1; 388 else 389 priv->link = 0; 390 } 391 392 return 0; 393 } 394 395 /* Generic function which updates the speed and duplex. If 396 * autonegotiation is enabled, it uses the AND of the link 397 * partner's advertised capabilities and our advertised 398 * capabilities. If autonegotiation is disabled, we use the 399 * appropriate bits in the control register. 400 * 401 * Stolen from Linux's mii.c and phy_device.c 402 */ 403 uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 404 { 405 /* We're using autonegotiation */ 406 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 407 uint lpa = 0; 408 uint gblpa = 0; 409 410 /* Check for gigabit capability */ 411 if (mii_reg & PHY_BMSR_EXT) { 412 /* We want a list of states supported by 413 * both PHYs in the link 414 */ 415 gblpa = read_phy_reg(priv, PHY_1000BTSR); 416 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 417 } 418 419 /* Set the baseline so we only have to set them 420 * if they're different 421 */ 422 priv->speed = 10; 423 priv->duplexity = 0; 424 425 /* Check the gigabit fields */ 426 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 427 priv->speed = 1000; 428 429 if (gblpa & PHY_1000BTSR_1000FD) 430 priv->duplexity = 1; 431 432 /* We're done! */ 433 return 0; 434 } 435 436 lpa = read_phy_reg(priv, PHY_ANAR); 437 lpa &= read_phy_reg(priv, PHY_ANLPAR); 438 439 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 440 priv->speed = 100; 441 442 if (lpa & PHY_ANLPAR_TXFD) 443 priv->duplexity = 1; 444 445 } else if (lpa & PHY_ANLPAR_10FD) 446 priv->duplexity = 1; 447 } else { 448 uint bmcr = read_phy_reg(priv, PHY_BMCR); 449 450 priv->speed = 10; 451 priv->duplexity = 0; 452 453 if (bmcr & PHY_BMCR_DPLX) 454 priv->duplexity = 1; 455 456 if (bmcr & PHY_BMCR_1000_MBPS) 457 priv->speed = 1000; 458 else if (bmcr & PHY_BMCR_100_MBPS) 459 priv->speed = 100; 460 } 461 462 return 0; 463 } 464 465 /* 466 * Parse the BCM54xx status register for speed and duplex information. 467 * The linux sungem_phy has this information, but in a table format. 468 */ 469 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 470 { 471 472 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ 473 474 case 1: 475 printf("Enet starting in 10BT/HD\n"); 476 priv->duplexity = 0; 477 priv->speed = 10; 478 break; 479 480 case 2: 481 printf("Enet starting in 10BT/FD\n"); 482 priv->duplexity = 1; 483 priv->speed = 10; 484 break; 485 486 case 3: 487 printf("Enet starting in 100BT/HD\n"); 488 priv->duplexity = 0; 489 priv->speed = 100; 490 break; 491 492 case 5: 493 printf("Enet starting in 100BT/FD\n"); 494 priv->duplexity = 1; 495 priv->speed = 100; 496 break; 497 498 case 6: 499 printf("Enet starting in 1000BT/HD\n"); 500 priv->duplexity = 0; 501 priv->speed = 1000; 502 break; 503 504 case 7: 505 printf("Enet starting in 1000BT/FD\n"); 506 priv->duplexity = 1; 507 priv->speed = 1000; 508 break; 509 510 default: 511 printf("Auto-neg error, defaulting to 10BT/HD\n"); 512 priv->duplexity = 0; 513 priv->speed = 10; 514 break; 515 } 516 517 return 0; 518 519 } 520 /* Parse the 88E1011's status register for speed and duplex 521 * information 522 */ 523 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 524 { 525 uint speed; 526 527 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 528 529 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 530 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 531 int i = 0; 532 533 puts("Waiting for PHY realtime link"); 534 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 535 /* Timeout reached ? */ 536 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 537 puts(" TIMEOUT !\n"); 538 priv->link = 0; 539 break; 540 } 541 542 if ((i++ % 1000) == 0) { 543 putc('.'); 544 } 545 udelay(1000); /* 1 ms */ 546 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 547 } 548 puts(" done\n"); 549 udelay(500000); /* another 500 ms (results in faster booting) */ 550 } else { 551 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 552 priv->link = 1; 553 else 554 priv->link = 0; 555 } 556 557 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 558 priv->duplexity = 1; 559 else 560 priv->duplexity = 0; 561 562 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 563 564 switch (speed) { 565 case MIIM_88E1011_PHYSTAT_GBIT: 566 priv->speed = 1000; 567 break; 568 case MIIM_88E1011_PHYSTAT_100: 569 priv->speed = 100; 570 break; 571 default: 572 priv->speed = 10; 573 } 574 575 return 0; 576 } 577 578 /* Parse the RTL8211B's status register for speed and duplex 579 * information 580 */ 581 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 582 { 583 uint speed; 584 585 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 586 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 587 int i = 0; 588 589 /* in case of timeout ->link is cleared */ 590 priv->link = 1; 591 puts("Waiting for PHY realtime link"); 592 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 593 /* Timeout reached ? */ 594 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 595 puts(" TIMEOUT !\n"); 596 priv->link = 0; 597 break; 598 } 599 600 if ((i++ % 1000) == 0) { 601 putc('.'); 602 } 603 udelay(1000); /* 1 ms */ 604 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 605 } 606 puts(" done\n"); 607 udelay(500000); /* another 500 ms (results in faster booting) */ 608 } else { 609 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 610 priv->link = 1; 611 else 612 priv->link = 0; 613 } 614 615 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 616 priv->duplexity = 1; 617 else 618 priv->duplexity = 0; 619 620 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 621 622 switch (speed) { 623 case MIIM_RTL8211B_PHYSTAT_GBIT: 624 priv->speed = 1000; 625 break; 626 case MIIM_RTL8211B_PHYSTAT_100: 627 priv->speed = 100; 628 break; 629 default: 630 priv->speed = 10; 631 } 632 633 return 0; 634 } 635 636 /* Parse the cis8201's status register for speed and duplex 637 * information 638 */ 639 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 640 { 641 uint speed; 642 643 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 644 priv->duplexity = 1; 645 else 646 priv->duplexity = 0; 647 648 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 649 switch (speed) { 650 case MIIM_CIS8201_AUXCONSTAT_GBIT: 651 priv->speed = 1000; 652 break; 653 case MIIM_CIS8201_AUXCONSTAT_100: 654 priv->speed = 100; 655 break; 656 default: 657 priv->speed = 10; 658 break; 659 } 660 661 return 0; 662 } 663 664 /* Parse the vsc8244's status register for speed and duplex 665 * information 666 */ 667 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 668 { 669 uint speed; 670 671 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 672 priv->duplexity = 1; 673 else 674 priv->duplexity = 0; 675 676 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 677 switch (speed) { 678 case MIIM_VSC8244_AUXCONSTAT_GBIT: 679 priv->speed = 1000; 680 break; 681 case MIIM_VSC8244_AUXCONSTAT_100: 682 priv->speed = 100; 683 break; 684 default: 685 priv->speed = 10; 686 break; 687 } 688 689 return 0; 690 } 691 692 /* Parse the DM9161's status register for speed and duplex 693 * information 694 */ 695 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 696 { 697 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 698 priv->speed = 100; 699 else 700 priv->speed = 10; 701 702 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 703 priv->duplexity = 1; 704 else 705 priv->duplexity = 0; 706 707 return 0; 708 } 709 710 /* 711 * Hack to write all 4 PHYs with the LED values 712 */ 713 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 714 { 715 uint phyid; 716 volatile tsec_t *regbase = priv->phyregs; 717 int timeout = 1000000; 718 719 for (phyid = 0; phyid < 4; phyid++) { 720 regbase->miimadd = (phyid << 8) | mii_reg; 721 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 722 asm("sync"); 723 724 timeout = 1000000; 725 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 726 } 727 728 return MIIM_CIS8204_SLEDCON_INIT; 729 } 730 731 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 732 { 733 if (priv->flags & TSEC_REDUCED) 734 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 735 else 736 return MIIM_CIS8204_EPHYCON_INIT; 737 } 738 739 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 740 { 741 uint mii_data = read_phy_reg(priv, mii_reg); 742 743 if (priv->flags & TSEC_REDUCED) 744 mii_data = (mii_data & 0xfff0) | 0x000b; 745 return mii_data; 746 } 747 748 /* Initialized required registers to appropriate values, zeroing 749 * those we don't care about (unless zero is bad, in which case, 750 * choose a more appropriate value) 751 */ 752 static void init_registers(volatile tsec_t * regs) 753 { 754 /* Clear IEVENT */ 755 regs->ievent = IEVENT_INIT_CLEAR; 756 757 regs->imask = IMASK_INIT_CLEAR; 758 759 regs->hash.iaddr0 = 0; 760 regs->hash.iaddr1 = 0; 761 regs->hash.iaddr2 = 0; 762 regs->hash.iaddr3 = 0; 763 regs->hash.iaddr4 = 0; 764 regs->hash.iaddr5 = 0; 765 regs->hash.iaddr6 = 0; 766 regs->hash.iaddr7 = 0; 767 768 regs->hash.gaddr0 = 0; 769 regs->hash.gaddr1 = 0; 770 regs->hash.gaddr2 = 0; 771 regs->hash.gaddr3 = 0; 772 regs->hash.gaddr4 = 0; 773 regs->hash.gaddr5 = 0; 774 regs->hash.gaddr6 = 0; 775 regs->hash.gaddr7 = 0; 776 777 regs->rctrl = 0x00000000; 778 779 /* Init RMON mib registers */ 780 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 781 782 regs->rmon.cam1 = 0xffffffff; 783 regs->rmon.cam2 = 0xffffffff; 784 785 regs->mrblr = MRBLR_INIT_SETTINGS; 786 787 regs->minflr = MINFLR_INIT_SETTINGS; 788 789 regs->attr = ATTR_INIT_SETTINGS; 790 regs->attreli = ATTRELI_INIT_SETTINGS; 791 792 } 793 794 /* Configure maccfg2 based on negotiated speed and duplex 795 * reported by PHY handling code 796 */ 797 static void adjust_link(struct eth_device *dev) 798 { 799 struct tsec_private *priv = (struct tsec_private *)dev->priv; 800 volatile tsec_t *regs = priv->regs; 801 802 if (priv->link) { 803 if (priv->duplexity != 0) 804 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 805 else 806 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 807 808 switch (priv->speed) { 809 case 1000: 810 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 811 | MACCFG2_GMII); 812 break; 813 case 100: 814 case 10: 815 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 816 | MACCFG2_MII); 817 818 /* Set R100 bit in all modes although 819 * it is only used in RGMII mode 820 */ 821 if (priv->speed == 100) 822 regs->ecntrl |= ECNTRL_R100; 823 else 824 regs->ecntrl &= ~(ECNTRL_R100); 825 break; 826 default: 827 printf("%s: Speed was bad\n", dev->name); 828 break; 829 } 830 831 printf("Speed: %d, %s duplex\n", priv->speed, 832 (priv->duplexity) ? "full" : "half"); 833 834 } else { 835 printf("%s: No link.\n", dev->name); 836 } 837 } 838 839 /* Set up the buffers and their descriptors, and bring up the 840 * interface 841 */ 842 static void startup_tsec(struct eth_device *dev) 843 { 844 int i; 845 struct tsec_private *priv = (struct tsec_private *)dev->priv; 846 volatile tsec_t *regs = priv->regs; 847 848 /* Point to the buffer descriptors */ 849 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 850 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 851 852 /* Initialize the Rx Buffer descriptors */ 853 for (i = 0; i < PKTBUFSRX; i++) { 854 rtx.rxbd[i].status = RXBD_EMPTY; 855 rtx.rxbd[i].length = 0; 856 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 857 } 858 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 859 860 /* Initialize the TX Buffer Descriptors */ 861 for (i = 0; i < TX_BUF_CNT; i++) { 862 rtx.txbd[i].status = 0; 863 rtx.txbd[i].length = 0; 864 rtx.txbd[i].bufPtr = 0; 865 } 866 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 867 868 /* Start up the PHY */ 869 if(priv->phyinfo) 870 phy_run_commands(priv, priv->phyinfo->startup); 871 872 adjust_link(dev); 873 874 /* Enable Transmit and Receive */ 875 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 876 877 /* Tell the DMA it is clear to go */ 878 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 879 regs->tstat = TSTAT_CLEAR_THALT; 880 regs->rstat = RSTAT_CLEAR_RHALT; 881 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 882 } 883 884 /* This returns the status bits of the device. The return value 885 * is never checked, and this is what the 8260 driver did, so we 886 * do the same. Presumably, this would be zero if there were no 887 * errors 888 */ 889 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 890 { 891 int i; 892 int result = 0; 893 struct tsec_private *priv = (struct tsec_private *)dev->priv; 894 volatile tsec_t *regs = priv->regs; 895 896 /* Find an empty buffer descriptor */ 897 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 898 if (i >= TOUT_LOOP) { 899 debug("%s: tsec: tx buffers full\n", dev->name); 900 return result; 901 } 902 } 903 904 rtx.txbd[txIdx].bufPtr = (uint) packet; 905 rtx.txbd[txIdx].length = length; 906 rtx.txbd[txIdx].status |= 907 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 908 909 /* Tell the DMA to go */ 910 regs->tstat = TSTAT_CLEAR_THALT; 911 912 /* Wait for buffer to be transmitted */ 913 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 914 if (i >= TOUT_LOOP) { 915 debug("%s: tsec: tx error\n", dev->name); 916 return result; 917 } 918 } 919 920 txIdx = (txIdx + 1) % TX_BUF_CNT; 921 result = rtx.txbd[txIdx].status & TXBD_STATS; 922 923 return result; 924 } 925 926 static int tsec_recv(struct eth_device *dev) 927 { 928 int length; 929 struct tsec_private *priv = (struct tsec_private *)dev->priv; 930 volatile tsec_t *regs = priv->regs; 931 932 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 933 934 length = rtx.rxbd[rxIdx].length; 935 936 /* Send the packet up if there were no errors */ 937 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 938 NetReceive(NetRxPackets[rxIdx], length - 4); 939 } else { 940 printf("Got error %x\n", 941 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 942 } 943 944 rtx.rxbd[rxIdx].length = 0; 945 946 /* Set the wrap bit if this is the last element in the list */ 947 rtx.rxbd[rxIdx].status = 948 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 949 950 rxIdx = (rxIdx + 1) % PKTBUFSRX; 951 } 952 953 if (regs->ievent & IEVENT_BSY) { 954 regs->ievent = IEVENT_BSY; 955 regs->rstat = RSTAT_CLEAR_RHALT; 956 } 957 958 return -1; 959 960 } 961 962 /* Stop the interface */ 963 static void tsec_halt(struct eth_device *dev) 964 { 965 struct tsec_private *priv = (struct tsec_private *)dev->priv; 966 volatile tsec_t *regs = priv->regs; 967 968 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 969 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 970 971 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; 972 973 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 974 975 /* Shut down the PHY, as needed */ 976 if(priv->phyinfo) 977 phy_run_commands(priv, priv->phyinfo->shutdown); 978 } 979 980 struct phy_info phy_info_M88E1149S = { 981 0x1410ca, 982 "Marvell 88E1149S", 983 4, 984 (struct phy_cmd[]){ /* config */ 985 /* Reset and configure the PHY */ 986 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 987 {0x1d, 0x1f, NULL}, 988 {0x1e, 0x200c, NULL}, 989 {0x1d, 0x5, NULL}, 990 {0x1e, 0x0, NULL}, 991 {0x1e, 0x100, NULL}, 992 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 993 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 994 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 995 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 996 {miim_end,} 997 }, 998 (struct phy_cmd[]){ /* startup */ 999 /* Status is read once to clear old link state */ 1000 {MIIM_STATUS, miim_read, NULL}, 1001 /* Auto-negotiate */ 1002 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1003 /* Read the status */ 1004 {MIIM_88E1011_PHY_STATUS, miim_read, 1005 &mii_parse_88E1011_psr}, 1006 {miim_end,} 1007 }, 1008 (struct phy_cmd[]){ /* shutdown */ 1009 {miim_end,} 1010 }, 1011 }; 1012 1013 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 1014 struct phy_info phy_info_BCM5461S = { 1015 0x02060c1, /* 5461 ID */ 1016 "Broadcom BCM5461S", 1017 0, /* not clear to me what minor revisions we can shift away */ 1018 (struct phy_cmd[]) { /* config */ 1019 /* Reset and configure the PHY */ 1020 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1021 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1022 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1023 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1024 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1025 {miim_end,} 1026 }, 1027 (struct phy_cmd[]) { /* startup */ 1028 /* Status is read once to clear old link state */ 1029 {MIIM_STATUS, miim_read, NULL}, 1030 /* Auto-negotiate */ 1031 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1032 /* Read the status */ 1033 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1034 {miim_end,} 1035 }, 1036 (struct phy_cmd[]) { /* shutdown */ 1037 {miim_end,} 1038 }, 1039 }; 1040 1041 struct phy_info phy_info_BCM5464S = { 1042 0x02060b1, /* 5464 ID */ 1043 "Broadcom BCM5464S", 1044 0, /* not clear to me what minor revisions we can shift away */ 1045 (struct phy_cmd[]) { /* config */ 1046 /* Reset and configure the PHY */ 1047 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1048 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1049 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1050 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1051 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1052 {miim_end,} 1053 }, 1054 (struct phy_cmd[]) { /* startup */ 1055 /* Status is read once to clear old link state */ 1056 {MIIM_STATUS, miim_read, NULL}, 1057 /* Auto-negotiate */ 1058 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1059 /* Read the status */ 1060 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1061 {miim_end,} 1062 }, 1063 (struct phy_cmd[]) { /* shutdown */ 1064 {miim_end,} 1065 }, 1066 }; 1067 1068 struct phy_info phy_info_M88E1011S = { 1069 0x01410c6, 1070 "Marvell 88E1011S", 1071 4, 1072 (struct phy_cmd[]){ /* config */ 1073 /* Reset and configure the PHY */ 1074 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1075 {0x1d, 0x1f, NULL}, 1076 {0x1e, 0x200c, NULL}, 1077 {0x1d, 0x5, NULL}, 1078 {0x1e, 0x0, NULL}, 1079 {0x1e, 0x100, NULL}, 1080 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1081 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1082 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1083 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1084 {miim_end,} 1085 }, 1086 (struct phy_cmd[]){ /* startup */ 1087 /* Status is read once to clear old link state */ 1088 {MIIM_STATUS, miim_read, NULL}, 1089 /* Auto-negotiate */ 1090 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1091 /* Read the status */ 1092 {MIIM_88E1011_PHY_STATUS, miim_read, 1093 &mii_parse_88E1011_psr}, 1094 {miim_end,} 1095 }, 1096 (struct phy_cmd[]){ /* shutdown */ 1097 {miim_end,} 1098 }, 1099 }; 1100 1101 struct phy_info phy_info_M88E1111S = { 1102 0x01410cc, 1103 "Marvell 88E1111S", 1104 4, 1105 (struct phy_cmd[]){ /* config */ 1106 /* Reset and configure the PHY */ 1107 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1108 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1109 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1110 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1111 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1112 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1113 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1114 {miim_end,} 1115 }, 1116 (struct phy_cmd[]){ /* startup */ 1117 /* Status is read once to clear old link state */ 1118 {MIIM_STATUS, miim_read, NULL}, 1119 /* Auto-negotiate */ 1120 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1121 /* Read the status */ 1122 {MIIM_88E1011_PHY_STATUS, miim_read, 1123 &mii_parse_88E1011_psr}, 1124 {miim_end,} 1125 }, 1126 (struct phy_cmd[]){ /* shutdown */ 1127 {miim_end,} 1128 }, 1129 }; 1130 1131 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1132 { 1133 uint mii_data = read_phy_reg(priv, mii_reg); 1134 1135 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1136 if (priv->flags & TSEC_REDUCED) 1137 return mii_data | 1138 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1139 else 1140 return mii_data; 1141 } 1142 1143 static struct phy_info phy_info_M88E1145 = { 1144 0x01410cd, 1145 "Marvell 88E1145", 1146 4, 1147 (struct phy_cmd[]){ /* config */ 1148 /* Reset the PHY */ 1149 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1150 1151 /* Errata E0, E1 */ 1152 {29, 0x001b, NULL}, 1153 {30, 0x418f, NULL}, 1154 {29, 0x0016, NULL}, 1155 {30, 0xa2da, NULL}, 1156 1157 /* Configure the PHY */ 1158 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1159 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1160 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, 1161 NULL}, 1162 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1163 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1164 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1165 {miim_end,} 1166 }, 1167 (struct phy_cmd[]){ /* startup */ 1168 /* Status is read once to clear old link state */ 1169 {MIIM_STATUS, miim_read, NULL}, 1170 /* Auto-negotiate */ 1171 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1172 {MIIM_88E1111_PHY_LED_CONTROL, 1173 MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1174 /* Read the Status */ 1175 {MIIM_88E1011_PHY_STATUS, miim_read, 1176 &mii_parse_88E1011_psr}, 1177 {miim_end,} 1178 }, 1179 (struct phy_cmd[]){ /* shutdown */ 1180 {miim_end,} 1181 }, 1182 }; 1183 1184 struct phy_info phy_info_cis8204 = { 1185 0x3f11, 1186 "Cicada Cis8204", 1187 6, 1188 (struct phy_cmd[]){ /* config */ 1189 /* Override PHY config settings */ 1190 {MIIM_CIS8201_AUX_CONSTAT, 1191 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1192 /* Configure some basic stuff */ 1193 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1194 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1195 &mii_cis8204_fixled}, 1196 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1197 &mii_cis8204_setmode}, 1198 {miim_end,} 1199 }, 1200 (struct phy_cmd[]){ /* startup */ 1201 /* Read the Status (2x to make sure link is right) */ 1202 {MIIM_STATUS, miim_read, NULL}, 1203 /* Auto-negotiate */ 1204 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1205 /* Read the status */ 1206 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1207 &mii_parse_cis8201}, 1208 {miim_end,} 1209 }, 1210 (struct phy_cmd[]){ /* shutdown */ 1211 {miim_end,} 1212 }, 1213 }; 1214 1215 /* Cicada 8201 */ 1216 struct phy_info phy_info_cis8201 = { 1217 0xfc41, 1218 "CIS8201", 1219 4, 1220 (struct phy_cmd[]){ /* config */ 1221 /* Override PHY config settings */ 1222 {MIIM_CIS8201_AUX_CONSTAT, 1223 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1224 /* Set up the interface mode */ 1225 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, 1226 NULL}, 1227 /* Configure some basic stuff */ 1228 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1229 {miim_end,} 1230 }, 1231 (struct phy_cmd[]){ /* startup */ 1232 /* Read the Status (2x to make sure link is right) */ 1233 {MIIM_STATUS, miim_read, NULL}, 1234 /* Auto-negotiate */ 1235 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1236 /* Read the status */ 1237 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1238 &mii_parse_cis8201}, 1239 {miim_end,} 1240 }, 1241 (struct phy_cmd[]){ /* shutdown */ 1242 {miim_end,} 1243 }, 1244 }; 1245 struct phy_info phy_info_VSC8244 = { 1246 0x3f1b, 1247 "Vitesse VSC8244", 1248 6, 1249 (struct phy_cmd[]){ /* config */ 1250 /* Override PHY config settings */ 1251 /* Configure some basic stuff */ 1252 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1253 {miim_end,} 1254 }, 1255 (struct phy_cmd[]){ /* startup */ 1256 /* Read the Status (2x to make sure link is right) */ 1257 {MIIM_STATUS, miim_read, NULL}, 1258 /* Auto-negotiate */ 1259 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1260 /* Read the status */ 1261 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1262 &mii_parse_vsc8244}, 1263 {miim_end,} 1264 }, 1265 (struct phy_cmd[]){ /* shutdown */ 1266 {miim_end,} 1267 }, 1268 }; 1269 1270 struct phy_info phy_info_VSC8601 = { 1271 0x00007042, 1272 "Vitesse VSC8601", 1273 4, 1274 (struct phy_cmd[]){ /* config */ 1275 /* Override PHY config settings */ 1276 /* Configure some basic stuff */ 1277 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1278 #ifdef CFG_VSC8601_SKEWFIX 1279 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, 1280 #endif 1281 {miim_end,} 1282 }, 1283 (struct phy_cmd[]){ /* startup */ 1284 /* Read the Status (2x to make sure link is right) */ 1285 {MIIM_STATUS, miim_read, NULL}, 1286 /* Auto-negotiate */ 1287 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1288 /* Read the status */ 1289 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1290 &mii_parse_vsc8244}, 1291 {miim_end,} 1292 }, 1293 (struct phy_cmd[]){ /* shutdown */ 1294 {miim_end,} 1295 }, 1296 }; 1297 1298 1299 struct phy_info phy_info_dm9161 = { 1300 0x0181b88, 1301 "Davicom DM9161E", 1302 4, 1303 (struct phy_cmd[]){ /* config */ 1304 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1305 /* Do not bypass the scrambler/descrambler */ 1306 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1307 /* Clear 10BTCSR to default */ 1308 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, 1309 NULL}, 1310 /* Configure some basic stuff */ 1311 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1312 /* Restart Auto Negotiation */ 1313 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1314 {miim_end,} 1315 }, 1316 (struct phy_cmd[]){ /* startup */ 1317 /* Status is read once to clear old link state */ 1318 {MIIM_STATUS, miim_read, NULL}, 1319 /* Auto-negotiate */ 1320 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1321 /* Read the status */ 1322 {MIIM_DM9161_SCSR, miim_read, 1323 &mii_parse_dm9161_scsr}, 1324 {miim_end,} 1325 }, 1326 (struct phy_cmd[]){ /* shutdown */ 1327 {miim_end,} 1328 }, 1329 }; 1330 /* a generic flavor. */ 1331 struct phy_info phy_info_generic = { 1332 0, 1333 "Unknown/Generic PHY", 1334 32, 1335 (struct phy_cmd[]) { /* config */ 1336 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1337 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1338 {miim_end,} 1339 }, 1340 (struct phy_cmd[]) { /* startup */ 1341 {PHY_BMSR, miim_read, NULL}, 1342 {PHY_BMSR, miim_read, &mii_parse_sr}, 1343 {PHY_BMSR, miim_read, &mii_parse_link}, 1344 {miim_end,} 1345 }, 1346 (struct phy_cmd[]) { /* shutdown */ 1347 {miim_end,} 1348 } 1349 }; 1350 1351 1352 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1353 { 1354 unsigned int speed; 1355 if (priv->link) { 1356 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1357 1358 switch (speed) { 1359 case MIIM_LXT971_SR2_10HDX: 1360 priv->speed = 10; 1361 priv->duplexity = 0; 1362 break; 1363 case MIIM_LXT971_SR2_10FDX: 1364 priv->speed = 10; 1365 priv->duplexity = 1; 1366 break; 1367 case MIIM_LXT971_SR2_100HDX: 1368 priv->speed = 100; 1369 priv->duplexity = 0; 1370 break; 1371 default: 1372 priv->speed = 100; 1373 priv->duplexity = 1; 1374 } 1375 } else { 1376 priv->speed = 0; 1377 priv->duplexity = 0; 1378 } 1379 1380 return 0; 1381 } 1382 1383 static struct phy_info phy_info_lxt971 = { 1384 0x0001378e, 1385 "LXT971", 1386 4, 1387 (struct phy_cmd[]){ /* config */ 1388 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1389 {miim_end,} 1390 }, 1391 (struct phy_cmd[]){ /* startup - enable interrupts */ 1392 /* { 0x12, 0x00f2, NULL }, */ 1393 {MIIM_STATUS, miim_read, NULL}, 1394 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1395 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1396 {miim_end,} 1397 }, 1398 (struct phy_cmd[]){ /* shutdown - disable interrupts */ 1399 {miim_end,} 1400 }, 1401 }; 1402 1403 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1404 * information 1405 */ 1406 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1407 { 1408 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1409 1410 case MIIM_DP83865_SPD_1000: 1411 priv->speed = 1000; 1412 break; 1413 1414 case MIIM_DP83865_SPD_100: 1415 priv->speed = 100; 1416 break; 1417 1418 default: 1419 priv->speed = 10; 1420 break; 1421 1422 } 1423 1424 if (mii_reg & MIIM_DP83865_DPX_FULL) 1425 priv->duplexity = 1; 1426 else 1427 priv->duplexity = 0; 1428 1429 return 0; 1430 } 1431 1432 struct phy_info phy_info_dp83865 = { 1433 0x20005c7, 1434 "NatSemi DP83865", 1435 4, 1436 (struct phy_cmd[]){ /* config */ 1437 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1438 {miim_end,} 1439 }, 1440 (struct phy_cmd[]){ /* startup */ 1441 /* Status is read once to clear old link state */ 1442 {MIIM_STATUS, miim_read, NULL}, 1443 /* Auto-negotiate */ 1444 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1445 /* Read the link and auto-neg status */ 1446 {MIIM_DP83865_LANR, miim_read, 1447 &mii_parse_dp83865_lanr}, 1448 {miim_end,} 1449 }, 1450 (struct phy_cmd[]){ /* shutdown */ 1451 {miim_end,} 1452 }, 1453 }; 1454 1455 struct phy_info phy_info_rtl8211b = { 1456 0x001cc91, 1457 "RealTek RTL8211B", 1458 4, 1459 (struct phy_cmd[]){ /* config */ 1460 /* Reset and configure the PHY */ 1461 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1462 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1463 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1464 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1465 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1466 {miim_end,} 1467 }, 1468 (struct phy_cmd[]){ /* startup */ 1469 /* Status is read once to clear old link state */ 1470 {MIIM_STATUS, miim_read, NULL}, 1471 /* Auto-negotiate */ 1472 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1473 /* Read the status */ 1474 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1475 {miim_end,} 1476 }, 1477 (struct phy_cmd[]){ /* shutdown */ 1478 {miim_end,} 1479 }, 1480 }; 1481 1482 struct phy_info *phy_info[] = { 1483 &phy_info_cis8204, 1484 &phy_info_cis8201, 1485 &phy_info_BCM5461S, 1486 &phy_info_BCM5464S, 1487 &phy_info_M88E1011S, 1488 &phy_info_M88E1111S, 1489 &phy_info_M88E1145, 1490 &phy_info_M88E1149S, 1491 &phy_info_dm9161, 1492 &phy_info_lxt971, 1493 &phy_info_VSC8244, 1494 &phy_info_VSC8601, 1495 &phy_info_dp83865, 1496 &phy_info_rtl8211b, 1497 &phy_info_generic, 1498 NULL 1499 }; 1500 1501 /* Grab the identifier of the device's PHY, and search through 1502 * all of the known PHYs to see if one matches. If so, return 1503 * it, if not, return NULL 1504 */ 1505 struct phy_info *get_phy_info(struct eth_device *dev) 1506 { 1507 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1508 uint phy_reg, phy_ID; 1509 int i; 1510 struct phy_info *theInfo = NULL; 1511 1512 /* Grab the bits from PHYIR1, and put them in the upper half */ 1513 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1514 phy_ID = (phy_reg & 0xffff) << 16; 1515 1516 /* Grab the bits from PHYIR2, and put them in the lower half */ 1517 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1518 phy_ID |= (phy_reg & 0xffff); 1519 1520 /* loop through all the known PHY types, and find one that */ 1521 /* matches the ID we read from the PHY. */ 1522 for (i = 0; phy_info[i]; i++) { 1523 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1524 theInfo = phy_info[i]; 1525 break; 1526 } 1527 } 1528 1529 if (theInfo == NULL) { 1530 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); 1531 return NULL; 1532 } else { 1533 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1534 } 1535 1536 return theInfo; 1537 } 1538 1539 /* Execute the given series of commands on the given device's 1540 * PHY, running functions as necessary 1541 */ 1542 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1543 { 1544 int i; 1545 uint result; 1546 volatile tsec_t *phyregs = priv->phyregs; 1547 1548 phyregs->miimcfg = MIIMCFG_RESET; 1549 1550 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1551 1552 while (phyregs->miimind & MIIMIND_BUSY) ; 1553 1554 for (i = 0; cmd->mii_reg != miim_end; i++) { 1555 if (cmd->mii_data == miim_read) { 1556 result = read_phy_reg(priv, cmd->mii_reg); 1557 1558 if (cmd->funct != NULL) 1559 (*(cmd->funct)) (result, priv); 1560 1561 } else { 1562 if (cmd->funct != NULL) 1563 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1564 else 1565 result = cmd->mii_data; 1566 1567 write_phy_reg(priv, cmd->mii_reg, result); 1568 1569 } 1570 cmd++; 1571 } 1572 } 1573 1574 /* Relocate the function pointers in the phy cmd lists */ 1575 static void relocate_cmds(void) 1576 { 1577 struct phy_cmd **cmdlistptr; 1578 struct phy_cmd *cmd; 1579 int i, j, k; 1580 1581 for (i = 0; phy_info[i]; i++) { 1582 /* First thing's first: relocate the pointers to the 1583 * PHY command structures (the structs were done) */ 1584 phy_info[i] = (struct phy_info *)((uint) phy_info[i] 1585 + gd->reloc_off); 1586 phy_info[i]->name += gd->reloc_off; 1587 phy_info[i]->config = 1588 (struct phy_cmd *)((uint) phy_info[i]->config 1589 + gd->reloc_off); 1590 phy_info[i]->startup = 1591 (struct phy_cmd *)((uint) phy_info[i]->startup 1592 + gd->reloc_off); 1593 phy_info[i]->shutdown = 1594 (struct phy_cmd *)((uint) phy_info[i]->shutdown 1595 + gd->reloc_off); 1596 1597 cmdlistptr = &phy_info[i]->config; 1598 j = 0; 1599 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { 1600 k = 0; 1601 for (cmd = *cmdlistptr; 1602 cmd->mii_reg != miim_end; 1603 cmd++) { 1604 /* Only relocate non-NULL pointers */ 1605 if (cmd->funct) 1606 cmd->funct += gd->reloc_off; 1607 1608 k++; 1609 } 1610 j++; 1611 } 1612 } 1613 1614 relocated = 1; 1615 } 1616 1617 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1618 && !defined(BITBANGMII) 1619 1620 /* 1621 * Read a MII PHY register. 1622 * 1623 * Returns: 1624 * 0 on success 1625 */ 1626 static int tsec_miiphy_read(char *devname, unsigned char addr, 1627 unsigned char reg, unsigned short *value) 1628 { 1629 unsigned short ret; 1630 struct tsec_private *priv = privlist[0]; 1631 1632 if (NULL == priv) { 1633 printf("Can't read PHY at address %d\n", addr); 1634 return -1; 1635 } 1636 1637 ret = (unsigned short)read_any_phy_reg(priv, addr, reg); 1638 *value = ret; 1639 1640 return 0; 1641 } 1642 1643 /* 1644 * Write a MII PHY register. 1645 * 1646 * Returns: 1647 * 0 on success 1648 */ 1649 static int tsec_miiphy_write(char *devname, unsigned char addr, 1650 unsigned char reg, unsigned short value) 1651 { 1652 struct tsec_private *priv = privlist[0]; 1653 1654 if (NULL == priv) { 1655 printf("Can't write PHY at address %d\n", addr); 1656 return -1; 1657 } 1658 1659 write_any_phy_reg(priv, addr, reg, value); 1660 1661 return 0; 1662 } 1663 1664 #endif 1665 1666 #ifdef CONFIG_MCAST_TFTP 1667 1668 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1669 1670 /* Set the appropriate hash bit for the given addr */ 1671 1672 /* The algorithm works like so: 1673 * 1) Take the Destination Address (ie the multicast address), and 1674 * do a CRC on it (little endian), and reverse the bits of the 1675 * result. 1676 * 2) Use the 8 most significant bits as a hash into a 256-entry 1677 * table. The table is controlled through 8 32-bit registers: 1678 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1679 * gaddr7. This means that the 3 most significant bits in the 1680 * hash index which gaddr register to use, and the 5 other bits 1681 * indicate which bit (assuming an IBM numbering scheme, which 1682 * for PowerPC (tm) is usually the case) in the tregister holds 1683 * the entry. */ 1684 static int 1685 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1686 { 1687 struct tsec_private *priv = privlist[1]; 1688 volatile tsec_t *regs = priv->regs; 1689 volatile u32 *reg_array, value; 1690 u8 result, whichbit, whichreg; 1691 1692 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1693 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1694 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1695 value = (1 << (31-whichbit)); 1696 1697 reg_array = &(regs->hash.gaddr0); 1698 1699 if (set) { 1700 reg_array[whichreg] |= value; 1701 } else { 1702 reg_array[whichreg] &= ~value; 1703 } 1704 return 0; 1705 } 1706 #endif /* Multicast TFTP ? */ 1707 1708 #endif /* CONFIG_TSEC_ENET */ 1709